From b1d758a5badf9af229934d505545e7695dee3bc2 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Tue, 15 Aug 2023 01:03:55 +0200 Subject: [PATCH 1/4] cpu/efm32: add family EFM32GG11 (generated with EFM2RIOT) --- cpu/efm32/families/efm32gg11b/Kconfig | 320 + cpu/efm32/families/efm32gg11b/Makefile | 6 + .../families/efm32gg11b/Makefile.include | 7 + cpu/efm32/families/efm32gg11b/efm32-info.mk | 65 + .../include/vendor/efm32gg11b110f2048gm64.h | 9940 ++++++++++++++++ .../include/vendor/efm32gg11b110f2048gq64.h | 9940 ++++++++++++++++ .../include/vendor/efm32gg11b110f2048im64.h | 9940 ++++++++++++++++ .../include/vendor/efm32gg11b110f2048iq64.h | 9940 ++++++++++++++++ .../include/vendor/efm32gg11b120f2048gm64.h | 9940 ++++++++++++++++ .../include/vendor/efm32gg11b120f2048gq64.h | 9940 ++++++++++++++++ .../include/vendor/efm32gg11b120f2048im64.h | 9940 ++++++++++++++++ .../include/vendor/efm32gg11b120f2048iq64.h | 9940 ++++++++++++++++ .../include/vendor/efm32gg11b310f2048gl112.h | 9976 ++++++++++++++++ .../include/vendor/efm32gg11b310f2048gq100.h | 9976 ++++++++++++++++ .../include/vendor/efm32gg11b320f2048gl112.h | 9976 ++++++++++++++++ .../include/vendor/efm32gg11b320f2048gq100.h | 9976 ++++++++++++++++ .../include/vendor/efm32gg11b420f2048gl112.h | 1921 ++++ .../include/vendor/efm32gg11b420f2048gl120.h | 1921 ++++ .../include/vendor/efm32gg11b420f2048gm64.h | 1921 ++++ .../include/vendor/efm32gg11b420f2048gq100.h | 1921 ++++ .../include/vendor/efm32gg11b420f2048gq64.h | 1921 ++++ .../include/vendor/efm32gg11b420f2048il112.h | 1921 ++++ .../include/vendor/efm32gg11b420f2048il120.h | 1921 ++++ .../include/vendor/efm32gg11b420f2048im64.h | 1921 ++++ .../include/vendor/efm32gg11b420f2048iq100.h | 1921 ++++ .../include/vendor/efm32gg11b420f2048iq64.h | 1921 ++++ .../include/vendor/efm32gg11b510f2048gl120.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b510f2048gm64.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b510f2048gq100.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b510f2048gq64.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b510f2048il120.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b510f2048im64.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b510f2048iq100.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b510f2048iq64.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b520f2048gl120.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b520f2048gm64.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b520f2048gq100.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b520f2048gq64.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b520f2048il120.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b520f2048im64.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b520f2048iq100.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b520f2048iq64.h | 9978 +++++++++++++++++ .../include/vendor/efm32gg11b820f2048gl120.h | 1923 ++++ .../include/vendor/efm32gg11b820f2048gl152.h | 1923 ++++ .../include/vendor/efm32gg11b820f2048gl192.h | 1923 ++++ .../include/vendor/efm32gg11b820f2048gm64.h | 1923 ++++ .../include/vendor/efm32gg11b820f2048gq100.h | 1923 ++++ .../include/vendor/efm32gg11b820f2048gq64.h | 1923 ++++ .../include/vendor/efm32gg11b820f2048il120.h | 1923 ++++ .../include/vendor/efm32gg11b820f2048il152.h | 1923 ++++ .../include/vendor/efm32gg11b820f2048im64.h | 1923 ++++ .../include/vendor/efm32gg11b820f2048iq100.h | 1923 ++++ .../include/vendor/efm32gg11b820f2048iq64.h | 1923 ++++ .../include/vendor/efm32gg11b840f1024gl120.h | 1923 ++++ .../include/vendor/efm32gg11b840f1024gl152.h | 1923 ++++ .../include/vendor/efm32gg11b840f1024gl192.h | 1923 ++++ .../include/vendor/efm32gg11b840f1024gm64.h | 1923 ++++ .../include/vendor/efm32gg11b840f1024gq100.h | 1923 ++++ .../include/vendor/efm32gg11b840f1024gq64.h | 1923 ++++ .../include/vendor/efm32gg11b840f1024il120.h | 1923 ++++ .../include/vendor/efm32gg11b840f1024il152.h | 1923 ++++ .../include/vendor/efm32gg11b840f1024im64.h | 1923 ++++ .../include/vendor/efm32gg11b840f1024iq100.h | 1923 ++++ .../include/vendor/efm32gg11b840f1024iq64.h | 1923 ++++ .../include/vendor/efm32gg11b_acmp.h | 1390 +++ .../include/vendor/efm32gg11b_adc.h | 2435 ++++ .../include/vendor/efm32gg11b_af_pins.h | 403 + .../include/vendor/efm32gg11b_af_ports.h | 403 + .../include/vendor/efm32gg11b_can.h | 652 ++ .../include/vendor/efm32gg11b_can_mir.h | 65 + .../include/vendor/efm32gg11b_cmu.h | 2698 +++++ .../include/vendor/efm32gg11b_cryotimer.h | 183 + .../include/vendor/efm32gg11b_crypto.h | 1218 ++ .../include/vendor/efm32gg11b_csen.h | 1010 ++ .../include/vendor/efm32gg11b_devinfo.h | 1798 +++ .../vendor/efm32gg11b_dma_descriptor.h | 64 + .../include/vendor/efm32gg11b_dmareq.h | 171 + .../include/vendor/efm32gg11b_ebi.h | 1712 +++ .../include/vendor/efm32gg11b_emu.h | 1978 ++++ .../include/vendor/efm32gg11b_eth.h | 2365 ++++ .../include/vendor/efm32gg11b_etm.h | 797 ++ .../include/vendor/efm32gg11b_fpueh.h | 208 + .../include/vendor/efm32gg11b_gpcrc.h | 201 + .../include/vendor/efm32gg11b_gpio.h | 1557 +++ .../include/vendor/efm32gg11b_gpio_p.h | 68 + .../include/vendor/efm32gg11b_i2c.h | 841 ++ .../include/vendor/efm32gg11b_idac.h | 392 + .../include/vendor/efm32gg11b_lcd.h | 636 ++ .../include/vendor/efm32gg11b_ldma.h | 781 ++ .../include/vendor/efm32gg11b_ldma_ch.h | 65 + .../include/vendor/efm32gg11b_lesense.h | 2003 ++++ .../include/vendor/efm32gg11b_lesense_buf.h | 58 + .../include/vendor/efm32gg11b_lesense_ch.h | 61 + .../include/vendor/efm32gg11b_lesense_st.h | 59 + .../include/vendor/efm32gg11b_letimer.h | 612 + .../include/vendor/efm32gg11b_leuart.h | 771 ++ .../include/vendor/efm32gg11b_msc.h | 847 ++ .../include/vendor/efm32gg11b_pcnt.h | 698 ++ .../include/vendor/efm32gg11b_prs.h | 1579 +++ .../include/vendor/efm32gg11b_prs_ch.h | 58 + .../include/vendor/efm32gg11b_prs_signals.h | 266 + .../include/vendor/efm32gg11b_qspi.h | 1098 ++ .../include/vendor/efm32gg11b_rmu.h | 212 + .../include/vendor/efm32gg11b_romtable.h | 88 + .../include/vendor/efm32gg11b_rtc.h | 168 + .../include/vendor/efm32gg11b_rtc_comp.h | 58 + .../include/vendor/efm32gg11b_rtcc.h | 745 ++ .../include/vendor/efm32gg11b_rtcc_cc.h | 61 + .../include/vendor/efm32gg11b_rtcc_ret.h | 58 + .../include/vendor/efm32gg11b_sdio.h | 1925 ++++ .../include/vendor/efm32gg11b_smu.h | 596 + .../include/vendor/efm32gg11b_timer.h | 1338 +++ .../include/vendor/efm32gg11b_timer_cc.h | 61 + .../include/vendor/efm32gg11b_trng.h | 295 + .../include/vendor/efm32gg11b_uart.h | 1744 +++ .../include/vendor/efm32gg11b_usart.h | 1784 +++ .../include/vendor/efm32gg11b_usb.h | 3115 +++++ .../include/vendor/efm32gg11b_usb_diep.h | 65 + .../include/vendor/efm32gg11b_usb_doep.h | 64 + .../include/vendor/efm32gg11b_usb_hc.h | 64 + .../include/vendor/efm32gg11b_vdac.h | 1717 +++ .../include/vendor/efm32gg11b_vdac_opa.h | 65 + .../include/vendor/efm32gg11b_wdog.h | 375 + .../include/vendor/efm32gg11b_wdog_pch.h | 58 + .../efm32gg11b/include/vendor/em_device.h | 236 + .../include/vendor/system_efm32gg11b.h | 198 + cpu/efm32/families/efm32gg11b/system.c | 410 + cpu/efm32/families/efm32gg11b/vectors.c | 171 + 128 files changed, 388858 insertions(+) create mode 100644 cpu/efm32/families/efm32gg11b/Kconfig create mode 100644 cpu/efm32/families/efm32gg11b/Makefile create mode 100644 cpu/efm32/families/efm32gg11b/Makefile.include create mode 100644 cpu/efm32/families/efm32gg11b/efm32-info.mk create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gm64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048im64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048iq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gm64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048im64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048iq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gl112.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gl112.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl112.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl120.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gm64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il112.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il120.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048im64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gl120.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gm64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048il120.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048im64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gl120.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gm64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048il120.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048im64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl120.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl152.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl192.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gm64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il120.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il152.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048im64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl120.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl152.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl192.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gm64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il120.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il152.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024im64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq100.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq64.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_acmp.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_adc.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_pins.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_ports.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can_mir.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cmu.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cryotimer.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_crypto.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_csen.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_devinfo.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dma_descriptor.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dmareq.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ebi.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_emu.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_eth.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_etm.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_fpueh.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpcrc.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio_p.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_i2c.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_idac.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lcd.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma_ch.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_buf.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_ch.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_st.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_letimer.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_leuart.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_msc.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_pcnt.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs_ch.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs_signals.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_qspi.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rmu.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_romtable.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtc.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtc_comp.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc_cc.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc_ret.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_sdio.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_smu.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_timer.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_timer_cc.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_trng.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_uart.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usart.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_diep.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_doep.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_hc.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_vdac.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_vdac_opa.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_wdog.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_wdog_pch.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/em_device.h create mode 100644 cpu/efm32/families/efm32gg11b/include/vendor/system_efm32gg11b.h create mode 100644 cpu/efm32/families/efm32gg11b/system.c create mode 100644 cpu/efm32/families/efm32gg11b/vectors.c diff --git a/cpu/efm32/families/efm32gg11b/Kconfig b/cpu/efm32/families/efm32gg11b/Kconfig new file mode 100644 index 0000000000000..918a00579aafe --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/Kconfig @@ -0,0 +1,320 @@ +# Copyright (c) 2020 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. + +config CPU_FAM_EFM32GG11B + bool + select CPU_CORE_CORTEX_M4F + select CPU_COMMON_EFM32 + select CPU_EFM32_SERIES1 + select HAS_PERIPH_HWRNG + select HAS_CORTEXM_MPU + +## CPU Models +config CPU_MODEL_EFM32GG11B510F2048IL120 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B120F2048GM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B120F2048IQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B820F2048GL152 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B520F2048IM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B520F2048GQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B840F1024GL120 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B420F2048IL120 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B520F2048GL120 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B840F1024GQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B840F1024IM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B820F2048GQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B420F2048GQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B420F2048IM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B420F2048IL112 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B510F2048IQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B310F2048GL112 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B840F1024GL152 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B310F2048GQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B510F2048GQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B510F2048IM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B820F2048GQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B820F2048GL120 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B820F2048IM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B420F2048IQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B840F1024GQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B110F2048IQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B110F2048GM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B520F2048GQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B820F2048IL120 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B840F1024IQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B420F2048GQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B820F2048GL192 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B320F2048GL112 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B520F2048IQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B110F2048GQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B110F2048IM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B320F2048GQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B420F2048GL112 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B510F2048GQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B820F2048IQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B820F2048GM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B510F2048IQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B510F2048GM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B840F1024IL152 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B420F2048GL120 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B840F1024IL120 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B520F2048GM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B520F2048IQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B520F2048IL120 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B840F1024GL192 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B120F2048IM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B120F2048GQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B820F2048IQ100 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B420F2048IQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B420F2048GM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B510F2048GL120 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B840F1024IQ64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B840F1024GM64 + bool + select CPU_FAM_EFM32GG11B + +config CPU_MODEL_EFM32GG11B820F2048IL152 + bool + select CPU_FAM_EFM32GG11B + +## Common CPU symbols +config CPU_FAM + default "efm32gg11b" if CPU_FAM_EFM32GG11B + +config CPU_MODEL + default "efm32gg11b510f2048il120" if CPU_MODEL_EFM32GG11B510F2048IL120 + default "efm32gg11b120f2048gm64" if CPU_MODEL_EFM32GG11B120F2048GM64 + default "efm32gg11b120f2048iq64" if CPU_MODEL_EFM32GG11B120F2048IQ64 + default "efm32gg11b820f2048gl152" if CPU_MODEL_EFM32GG11B820F2048GL152 + default "efm32gg11b520f2048im64" if CPU_MODEL_EFM32GG11B520F2048IM64 + default "efm32gg11b520f2048gq64" if CPU_MODEL_EFM32GG11B520F2048GQ64 + default "efm32gg11b840f1024gl120" if CPU_MODEL_EFM32GG11B840F1024GL120 + default "efm32gg11b420f2048il120" if CPU_MODEL_EFM32GG11B420F2048IL120 + default "efm32gg11b520f2048gl120" if CPU_MODEL_EFM32GG11B520F2048GL120 + default "efm32gg11b840f1024gq64" if CPU_MODEL_EFM32GG11B840F1024GQ64 + default "efm32gg11b840f1024im64" if CPU_MODEL_EFM32GG11B840F1024IM64 + default "efm32gg11b820f2048gq100" if CPU_MODEL_EFM32GG11B820F2048GQ100 + default "efm32gg11b420f2048gq64" if CPU_MODEL_EFM32GG11B420F2048GQ64 + default "efm32gg11b420f2048im64" if CPU_MODEL_EFM32GG11B420F2048IM64 + default "efm32gg11b420f2048il112" if CPU_MODEL_EFM32GG11B420F2048IL112 + default "efm32gg11b510f2048iq100" if CPU_MODEL_EFM32GG11B510F2048IQ100 + default "efm32gg11b310f2048gl112" if CPU_MODEL_EFM32GG11B310F2048GL112 + default "efm32gg11b840f1024gl152" if CPU_MODEL_EFM32GG11B840F1024GL152 + default "efm32gg11b310f2048gq100" if CPU_MODEL_EFM32GG11B310F2048GQ100 + default "efm32gg11b510f2048gq64" if CPU_MODEL_EFM32GG11B510F2048GQ64 + default "efm32gg11b510f2048im64" if CPU_MODEL_EFM32GG11B510F2048IM64 + default "efm32gg11b820f2048gq64" if CPU_MODEL_EFM32GG11B820F2048GQ64 + default "efm32gg11b820f2048gl120" if CPU_MODEL_EFM32GG11B820F2048GL120 + default "efm32gg11b820f2048im64" if CPU_MODEL_EFM32GG11B820F2048IM64 + default "efm32gg11b420f2048iq100" if CPU_MODEL_EFM32GG11B420F2048IQ100 + default "efm32gg11b840f1024gq100" if CPU_MODEL_EFM32GG11B840F1024GQ100 + default "efm32gg11b110f2048iq64" if CPU_MODEL_EFM32GG11B110F2048IQ64 + default "efm32gg11b110f2048gm64" if CPU_MODEL_EFM32GG11B110F2048GM64 + default "efm32gg11b520f2048gq100" if CPU_MODEL_EFM32GG11B520F2048GQ100 + default "efm32gg11b820f2048il120" if CPU_MODEL_EFM32GG11B820F2048IL120 + default "efm32gg11b840f1024iq100" if CPU_MODEL_EFM32GG11B840F1024IQ100 + default "efm32gg11b420f2048gq100" if CPU_MODEL_EFM32GG11B420F2048GQ100 + default "efm32gg11b820f2048gl192" if CPU_MODEL_EFM32GG11B820F2048GL192 + default "efm32gg11b320f2048gl112" if CPU_MODEL_EFM32GG11B320F2048GL112 + default "efm32gg11b520f2048iq100" if CPU_MODEL_EFM32GG11B520F2048IQ100 + default "efm32gg11b110f2048gq64" if CPU_MODEL_EFM32GG11B110F2048GQ64 + default "efm32gg11b110f2048im64" if CPU_MODEL_EFM32GG11B110F2048IM64 + default "efm32gg11b320f2048gq100" if CPU_MODEL_EFM32GG11B320F2048GQ100 + default "efm32gg11b420f2048gl112" if CPU_MODEL_EFM32GG11B420F2048GL112 + default "efm32gg11b510f2048gq100" if CPU_MODEL_EFM32GG11B510F2048GQ100 + default "efm32gg11b820f2048iq64" if CPU_MODEL_EFM32GG11B820F2048IQ64 + default "efm32gg11b820f2048gm64" if CPU_MODEL_EFM32GG11B820F2048GM64 + default "efm32gg11b510f2048iq64" if CPU_MODEL_EFM32GG11B510F2048IQ64 + default "efm32gg11b510f2048gm64" if CPU_MODEL_EFM32GG11B510F2048GM64 + default "efm32gg11b840f1024il152" if CPU_MODEL_EFM32GG11B840F1024IL152 + default "efm32gg11b420f2048gl120" if CPU_MODEL_EFM32GG11B420F2048GL120 + default "efm32gg11b840f1024il120" if CPU_MODEL_EFM32GG11B840F1024IL120 + default "efm32gg11b520f2048gm64" if CPU_MODEL_EFM32GG11B520F2048GM64 + default "efm32gg11b520f2048iq64" if CPU_MODEL_EFM32GG11B520F2048IQ64 + default "efm32gg11b520f2048il120" if CPU_MODEL_EFM32GG11B520F2048IL120 + default "efm32gg11b840f1024gl192" if CPU_MODEL_EFM32GG11B840F1024GL192 + default "efm32gg11b120f2048im64" if CPU_MODEL_EFM32GG11B120F2048IM64 + default "efm32gg11b120f2048gq64" if CPU_MODEL_EFM32GG11B120F2048GQ64 + default "efm32gg11b820f2048iq100" if CPU_MODEL_EFM32GG11B820F2048IQ100 + default "efm32gg11b420f2048iq64" if CPU_MODEL_EFM32GG11B420F2048IQ64 + default "efm32gg11b420f2048gm64" if CPU_MODEL_EFM32GG11B420F2048GM64 + default "efm32gg11b510f2048gl120" if CPU_MODEL_EFM32GG11B510F2048GL120 + default "efm32gg11b840f1024iq64" if CPU_MODEL_EFM32GG11B840F1024IQ64 + default "efm32gg11b840f1024gm64" if CPU_MODEL_EFM32GG11B840F1024GM64 + default "efm32gg11b820f2048il152" if CPU_MODEL_EFM32GG11B820F2048IL152 diff --git a/cpu/efm32/families/efm32gg11b/Makefile b/cpu/efm32/families/efm32gg11b/Makefile new file mode 100644 index 0000000000000..c6747fc7e09c4 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/Makefile @@ -0,0 +1,6 @@ +MODULE = cpu_efm32gg11b + +# (file triggers compiler bug. see #5775) +SRC_NOLTO += vectors.c + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/efm32/families/efm32gg11b/Makefile.include b/cpu/efm32/families/efm32gg11b/Makefile.include new file mode 100644 index 0000000000000..d95c831cd0242 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/Makefile.include @@ -0,0 +1,7 @@ +# Find the header file that should exist if the CPU is supported. Only headers +# for supported boards are included, but to support another CPU, it should be +# as easy as adding the header file only. +EFM32_HEADER = $(wildcard $(RIOTCPU)/efm32/families/efm32gg11b/include/vendor/$(CPU_MODEL).h) + +# include vendor device headers +INCLUDES += -I$(RIOTCPU)/efm32/families/efm32gg11b/include/vendor \ No newline at end of file diff --git a/cpu/efm32/families/efm32gg11b/efm32-info.mk b/cpu/efm32/families/efm32gg11b/efm32-info.mk new file mode 100644 index 0000000000000..26540efffb559 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/efm32-info.mk @@ -0,0 +1,65 @@ +# This file is automatically generated, and should not be changed. There is +# probably little reason to edit this file anyway, since it should already +# contain all information for the EFM32GG11B family of CPUs. + +# Series - Architecture - Flash base - Flash size - SRAM base - SRAM size - Crypto? - TRNG? - Radio? +EFM32_INFO_efm32gg11b510f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b120f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b120f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b820f2048gl152 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b520f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b520f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b840f1024gl120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b420f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b520f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b840f1024gq64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b840f1024im64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b820f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b420f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b420f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b420f2048il112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b510f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b310f2048gl112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b840f1024gl152 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b310f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b510f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b510f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b820f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b820f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b820f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b420f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b840f1024gq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b110f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b110f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b520f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b820f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b840f1024iq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b420f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b820f2048gl192 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b320f2048gl112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b520f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b110f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b110f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b320f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b420f2048gl112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b510f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b820f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b820f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b510f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b510f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b840f1024il152 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b420f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b840f1024il120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b520f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b520f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b520f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b840f1024gl192 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b120f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b120f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b820f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b420f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b420f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b510f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0 +EFM32_INFO_efm32gg11b840f1024iq64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b840f1024gm64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0 +EFM32_INFO_efm32gg11b820f2048il152 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0 diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gm64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gm64.h new file mode 100644 index 0000000000000..a66df2b74be21 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gm64.h @@ -0,0 +1,9940 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B110F2048GM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B110F2048GM64_H +#define EFM32GG11B110F2048GM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64 EFM32GG11B110F2048GM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B110F2048GM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B110F2048GM64) +#define EFM32GG11B110F2048GM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B110F2048GM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B110F2048GM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B110F2048GM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_MSC MSC + * @{ + * @brief EFM32GG11B110F2048GM64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_EMU EMU + * @{ + * @brief EFM32GG11B110F2048GM64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_CMU CMU + * @{ + * @brief EFM32GG11B110F2048GM64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_PRS PRS + * @{ + * @brief EFM32GG11B110F2048GM64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_SMU SMU + * @{ + * @brief EFM32GG11B110F2048GM64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B110F2048GM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B110F2048GM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B110F2048GM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B110F2048GM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GM64_PRS + * @{ + * @addtogroup EFM32GG11B110F2048GM64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GM64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GM64_WTIMER + * @{ + * @defgroup EFM32GG11B110F2048GM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GM64_MSC + * @{ + * @defgroup EFM32GG11B110F2048GM64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GM64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GM64_EMU + * @{ + * @defgroup EFM32GG11B110F2048GM64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GM64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GM64_CMU + * @{ + * @defgroup EFM32GG11B110F2048GM64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000017UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F03FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GM64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GM64_PRS + * @{ + * @defgroup EFM32GG11B110F2048GM64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GM64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GM64_SMU + * @{ + * @defgroup EFM32GG11B110F2048GM64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFDFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GM64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B110F2048GM64_UNLOCK */ + +/** @} End of group EFM32GG11B110F2048GM64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B110F2048GM64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GM64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B110F2048GM64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GM64_AF_Pins */ + +/** @} End of group EFM32GG11B110F2048GM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B110F2048GM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gq64.h new file mode 100644 index 0000000000000..e56490b56fc24 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gq64.h @@ -0,0 +1,9940 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B110F2048GQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B110F2048GQ64_H +#define EFM32GG11B110F2048GQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64 EFM32GG11B110F2048GQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B110F2048GQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B110F2048GQ64) +#define EFM32GG11B110F2048GQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B110F2048GQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B110F2048GQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B110F2048GQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_MSC MSC + * @{ + * @brief EFM32GG11B110F2048GQ64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_EMU EMU + * @{ + * @brief EFM32GG11B110F2048GQ64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_CMU CMU + * @{ + * @brief EFM32GG11B110F2048GQ64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_PRS PRS + * @{ + * @brief EFM32GG11B110F2048GQ64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_SMU SMU + * @{ + * @brief EFM32GG11B110F2048GQ64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B110F2048GQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B110F2048GQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B110F2048GQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B110F2048GQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GQ64_PRS + * @{ + * @addtogroup EFM32GG11B110F2048GQ64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GQ64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GQ64_WTIMER + * @{ + * @defgroup EFM32GG11B110F2048GQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GQ64_MSC + * @{ + * @defgroup EFM32GG11B110F2048GQ64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GQ64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GQ64_EMU + * @{ + * @defgroup EFM32GG11B110F2048GQ64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GQ64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GQ64_CMU + * @{ + * @defgroup EFM32GG11B110F2048GQ64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000017UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F03FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GQ64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GQ64_PRS + * @{ + * @defgroup EFM32GG11B110F2048GQ64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GQ64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GQ64_SMU + * @{ + * @defgroup EFM32GG11B110F2048GQ64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFDFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GQ64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048GQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B110F2048GQ64_UNLOCK */ + +/** @} End of group EFM32GG11B110F2048GQ64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B110F2048GQ64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GQ64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048GQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B110F2048GQ64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048GQ64_AF_Pins */ + +/** @} End of group EFM32GG11B110F2048GQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B110F2048GQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048im64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048im64.h new file mode 100644 index 0000000000000..272f75450e651 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048im64.h @@ -0,0 +1,9940 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B110F2048IM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B110F2048IM64_H +#define EFM32GG11B110F2048IM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64 EFM32GG11B110F2048IM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B110F2048IM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B110F2048IM64) +#define EFM32GG11B110F2048IM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B110F2048IM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B110F2048IM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B110F2048IM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_MSC MSC + * @{ + * @brief EFM32GG11B110F2048IM64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_EMU EMU + * @{ + * @brief EFM32GG11B110F2048IM64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_CMU CMU + * @{ + * @brief EFM32GG11B110F2048IM64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_PRS PRS + * @{ + * @brief EFM32GG11B110F2048IM64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_SMU SMU + * @{ + * @brief EFM32GG11B110F2048IM64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B110F2048IM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B110F2048IM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B110F2048IM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B110F2048IM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IM64_PRS + * @{ + * @addtogroup EFM32GG11B110F2048IM64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IM64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IM64_WTIMER + * @{ + * @defgroup EFM32GG11B110F2048IM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IM64_MSC + * @{ + * @defgroup EFM32GG11B110F2048IM64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IM64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IM64_EMU + * @{ + * @defgroup EFM32GG11B110F2048IM64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IM64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IM64_CMU + * @{ + * @defgroup EFM32GG11B110F2048IM64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000017UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F03FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IM64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IM64_PRS + * @{ + * @defgroup EFM32GG11B110F2048IM64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IM64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IM64_SMU + * @{ + * @defgroup EFM32GG11B110F2048IM64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFDFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IM64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B110F2048IM64_UNLOCK */ + +/** @} End of group EFM32GG11B110F2048IM64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B110F2048IM64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IM64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B110F2048IM64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IM64_AF_Pins */ + +/** @} End of group EFM32GG11B110F2048IM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B110F2048IM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048iq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048iq64.h new file mode 100644 index 0000000000000..d3a1923c6fdb9 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048iq64.h @@ -0,0 +1,9940 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B110F2048IQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B110F2048IQ64_H +#define EFM32GG11B110F2048IQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64 EFM32GG11B110F2048IQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B110F2048IQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B110F2048IQ64) +#define EFM32GG11B110F2048IQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B110F2048IQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B110F2048IQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B110F2048IQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_MSC MSC + * @{ + * @brief EFM32GG11B110F2048IQ64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_EMU EMU + * @{ + * @brief EFM32GG11B110F2048IQ64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_CMU CMU + * @{ + * @brief EFM32GG11B110F2048IQ64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_PRS PRS + * @{ + * @brief EFM32GG11B110F2048IQ64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_SMU SMU + * @{ + * @brief EFM32GG11B110F2048IQ64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B110F2048IQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B110F2048IQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B110F2048IQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B110F2048IQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IQ64_PRS + * @{ + * @addtogroup EFM32GG11B110F2048IQ64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IQ64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IQ64_WTIMER + * @{ + * @defgroup EFM32GG11B110F2048IQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IQ64_MSC + * @{ + * @defgroup EFM32GG11B110F2048IQ64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IQ64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IQ64_EMU + * @{ + * @defgroup EFM32GG11B110F2048IQ64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IQ64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IQ64_CMU + * @{ + * @defgroup EFM32GG11B110F2048IQ64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000017UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F03FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IQ64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IQ64_PRS + * @{ + * @defgroup EFM32GG11B110F2048IQ64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IQ64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IQ64_SMU + * @{ + * @defgroup EFM32GG11B110F2048IQ64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFDFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IQ64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B110F2048IQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B110F2048IQ64_UNLOCK */ + +/** @} End of group EFM32GG11B110F2048IQ64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B110F2048IQ64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IQ64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B110F2048IQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B110F2048IQ64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B110F2048IQ64_AF_Pins */ + +/** @} End of group EFM32GG11B110F2048IQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B110F2048IQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gm64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gm64.h new file mode 100644 index 0000000000000..5912ae93610ac --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gm64.h @@ -0,0 +1,9940 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B120F2048GM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B120F2048GM64_H +#define EFM32GG11B120F2048GM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64 EFM32GG11B120F2048GM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B120F2048GM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B120F2048GM64) +#define EFM32GG11B120F2048GM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B120F2048GM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B120F2048GM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B120F2048GM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_MSC MSC + * @{ + * @brief EFM32GG11B120F2048GM64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_EMU EMU + * @{ + * @brief EFM32GG11B120F2048GM64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_CMU CMU + * @{ + * @brief EFM32GG11B120F2048GM64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_PRS PRS + * @{ + * @brief EFM32GG11B120F2048GM64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_SMU SMU + * @{ + * @brief EFM32GG11B120F2048GM64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B120F2048GM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B120F2048GM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B120F2048GM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B120F2048GM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GM64_PRS + * @{ + * @addtogroup EFM32GG11B120F2048GM64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GM64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GM64_WTIMER + * @{ + * @defgroup EFM32GG11B120F2048GM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GM64_MSC + * @{ + * @defgroup EFM32GG11B120F2048GM64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GM64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GM64_EMU + * @{ + * @defgroup EFM32GG11B120F2048GM64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GM64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GM64_CMU + * @{ + * @defgroup EFM32GG11B120F2048GM64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000017UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F03FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GM64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GM64_PRS + * @{ + * @defgroup EFM32GG11B120F2048GM64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GM64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GM64_SMU + * @{ + * @defgroup EFM32GG11B120F2048GM64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFDFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GM64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B120F2048GM64_UNLOCK */ + +/** @} End of group EFM32GG11B120F2048GM64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B120F2048GM64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GM64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B120F2048GM64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GM64_AF_Pins */ + +/** @} End of group EFM32GG11B120F2048GM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B120F2048GM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gq64.h new file mode 100644 index 0000000000000..05346990e6834 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gq64.h @@ -0,0 +1,9940 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B120F2048GQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B120F2048GQ64_H +#define EFM32GG11B120F2048GQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64 EFM32GG11B120F2048GQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B120F2048GQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B120F2048GQ64) +#define EFM32GG11B120F2048GQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B120F2048GQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B120F2048GQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B120F2048GQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_MSC MSC + * @{ + * @brief EFM32GG11B120F2048GQ64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_EMU EMU + * @{ + * @brief EFM32GG11B120F2048GQ64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_CMU CMU + * @{ + * @brief EFM32GG11B120F2048GQ64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_PRS PRS + * @{ + * @brief EFM32GG11B120F2048GQ64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_SMU SMU + * @{ + * @brief EFM32GG11B120F2048GQ64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B120F2048GQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B120F2048GQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B120F2048GQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B120F2048GQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GQ64_PRS + * @{ + * @addtogroup EFM32GG11B120F2048GQ64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GQ64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GQ64_WTIMER + * @{ + * @defgroup EFM32GG11B120F2048GQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GQ64_MSC + * @{ + * @defgroup EFM32GG11B120F2048GQ64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GQ64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GQ64_EMU + * @{ + * @defgroup EFM32GG11B120F2048GQ64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GQ64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GQ64_CMU + * @{ + * @defgroup EFM32GG11B120F2048GQ64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000017UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F03FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GQ64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GQ64_PRS + * @{ + * @defgroup EFM32GG11B120F2048GQ64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GQ64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GQ64_SMU + * @{ + * @defgroup EFM32GG11B120F2048GQ64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFDFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GQ64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048GQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B120F2048GQ64_UNLOCK */ + +/** @} End of group EFM32GG11B120F2048GQ64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B120F2048GQ64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GQ64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048GQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B120F2048GQ64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048GQ64_AF_Pins */ + +/** @} End of group EFM32GG11B120F2048GQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B120F2048GQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048im64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048im64.h new file mode 100644 index 0000000000000..6275b5fabd41d --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048im64.h @@ -0,0 +1,9940 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B120F2048IM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B120F2048IM64_H +#define EFM32GG11B120F2048IM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64 EFM32GG11B120F2048IM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B120F2048IM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B120F2048IM64) +#define EFM32GG11B120F2048IM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B120F2048IM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B120F2048IM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B120F2048IM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_MSC MSC + * @{ + * @brief EFM32GG11B120F2048IM64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_EMU EMU + * @{ + * @brief EFM32GG11B120F2048IM64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_CMU CMU + * @{ + * @brief EFM32GG11B120F2048IM64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_PRS PRS + * @{ + * @brief EFM32GG11B120F2048IM64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_SMU SMU + * @{ + * @brief EFM32GG11B120F2048IM64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B120F2048IM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B120F2048IM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B120F2048IM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B120F2048IM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IM64_PRS + * @{ + * @addtogroup EFM32GG11B120F2048IM64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IM64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IM64_WTIMER + * @{ + * @defgroup EFM32GG11B120F2048IM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IM64_MSC + * @{ + * @defgroup EFM32GG11B120F2048IM64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IM64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IM64_EMU + * @{ + * @defgroup EFM32GG11B120F2048IM64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IM64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IM64_CMU + * @{ + * @defgroup EFM32GG11B120F2048IM64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000017UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F03FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IM64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IM64_PRS + * @{ + * @defgroup EFM32GG11B120F2048IM64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IM64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IM64_SMU + * @{ + * @defgroup EFM32GG11B120F2048IM64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFDFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IM64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B120F2048IM64_UNLOCK */ + +/** @} End of group EFM32GG11B120F2048IM64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B120F2048IM64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IM64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B120F2048IM64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IM64_AF_Pins */ + +/** @} End of group EFM32GG11B120F2048IM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B120F2048IM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048iq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048iq64.h new file mode 100644 index 0000000000000..b9bbeedf9e30b --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048iq64.h @@ -0,0 +1,9940 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B120F2048IQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B120F2048IQ64_H +#define EFM32GG11B120F2048IQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64 EFM32GG11B120F2048IQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B120F2048IQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B120F2048IQ64) +#define EFM32GG11B120F2048IQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B120F2048IQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B120F2048IQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B120F2048IQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_MSC MSC + * @{ + * @brief EFM32GG11B120F2048IQ64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_EMU EMU + * @{ + * @brief EFM32GG11B120F2048IQ64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_CMU CMU + * @{ + * @brief EFM32GG11B120F2048IQ64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_PRS PRS + * @{ + * @brief EFM32GG11B120F2048IQ64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_SMU SMU + * @{ + * @brief EFM32GG11B120F2048IQ64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B120F2048IQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B120F2048IQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B120F2048IQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B120F2048IQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IQ64_PRS + * @{ + * @addtogroup EFM32GG11B120F2048IQ64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IQ64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IQ64_WTIMER + * @{ + * @defgroup EFM32GG11B120F2048IQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IQ64_MSC + * @{ + * @defgroup EFM32GG11B120F2048IQ64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IQ64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IQ64_EMU + * @{ + * @defgroup EFM32GG11B120F2048IQ64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IQ64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IQ64_CMU + * @{ + * @defgroup EFM32GG11B120F2048IQ64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000017UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F03FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IQ64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IQ64_PRS + * @{ + * @defgroup EFM32GG11B120F2048IQ64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IQ64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IQ64_SMU + * @{ + * @defgroup EFM32GG11B120F2048IQ64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFDFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IQ64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B120F2048IQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B120F2048IQ64_UNLOCK */ + +/** @} End of group EFM32GG11B120F2048IQ64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B120F2048IQ64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IQ64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B120F2048IQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B120F2048IQ64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B120F2048IQ64_AF_Pins */ + +/** @} End of group EFM32GG11B120F2048IQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B120F2048IQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gl112.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gl112.h new file mode 100644 index 0000000000000..17069c5b5a124 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gl112.h @@ -0,0 +1,9976 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B310F2048GL112 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B310F2048GL112_H +#define EFM32GG11B310F2048GL112_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112 EFM32GG11B310F2048GL112 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B310F2048GL112_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B310F2048GL112) +#define EFM32GG11B310F2048GL112 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B310F2048GL112" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B310F2048GL112 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B310F2048GL112_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_MSC MSC + * @{ + * @brief EFM32GG11B310F2048GL112_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_EMU EMU + * @{ + * @brief EFM32GG11B310F2048GL112_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_CMU CMU + * @{ + * @brief EFM32GG11B310F2048GL112_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_PRS PRS + * @{ + * @brief EFM32GG11B310F2048GL112_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_SMU SMU + * @{ + * @brief EFM32GG11B310F2048GL112_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B310F2048GL112_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B310F2048GL112_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B310F2048GL112_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B310F2048GL112_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GL112_PRS + * @{ + * @addtogroup EFM32GG11B310F2048GL112_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GL112_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GL112_WTIMER + * @{ + * @defgroup EFM32GG11B310F2048GL112_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GL112_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GL112_MSC + * @{ + * @defgroup EFM32GG11B310F2048GL112_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GL112_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GL112_EMU + * @{ + * @defgroup EFM32GG11B310F2048GL112_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GL112_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GL112_CMU + * @{ + * @defgroup EFM32GG11B310F2048GL112_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GL112_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GL112_PRS + * @{ + * @defgroup EFM32GG11B310F2048GL112_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GL112_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GL112_SMU + * @{ + * @defgroup EFM32GG11B310F2048GL112_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GL112_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GL112_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B310F2048GL112_UNLOCK */ + +/** @} End of group EFM32GG11B310F2048GL112_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GL112_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B310F2048GL112_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GL112_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GL112_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B310F2048GL112_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GL112_AF_Pins */ + +/** @} End of group EFM32GG11B310F2048GL112 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B310F2048GL112_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gq100.h new file mode 100644 index 0000000000000..5c4183c125bcf --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gq100.h @@ -0,0 +1,9976 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B310F2048GQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B310F2048GQ100_H +#define EFM32GG11B310F2048GQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100 EFM32GG11B310F2048GQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B310F2048GQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B310F2048GQ100) +#define EFM32GG11B310F2048GQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B310F2048GQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B310F2048GQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B310F2048GQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_MSC MSC + * @{ + * @brief EFM32GG11B310F2048GQ100_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_EMU EMU + * @{ + * @brief EFM32GG11B310F2048GQ100_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_CMU CMU + * @{ + * @brief EFM32GG11B310F2048GQ100_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_PRS PRS + * @{ + * @brief EFM32GG11B310F2048GQ100_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_SMU SMU + * @{ + * @brief EFM32GG11B310F2048GQ100_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B310F2048GQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B310F2048GQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B310F2048GQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B310F2048GQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GQ100_PRS + * @{ + * @addtogroup EFM32GG11B310F2048GQ100_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GQ100_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GQ100_WTIMER + * @{ + * @defgroup EFM32GG11B310F2048GQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GQ100_MSC + * @{ + * @defgroup EFM32GG11B310F2048GQ100_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GQ100_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GQ100_EMU + * @{ + * @defgroup EFM32GG11B310F2048GQ100_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GQ100_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GQ100_CMU + * @{ + * @defgroup EFM32GG11B310F2048GQ100_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GQ100_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GQ100_PRS + * @{ + * @defgroup EFM32GG11B310F2048GQ100_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GQ100_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GQ100_SMU + * @{ + * @defgroup EFM32GG11B310F2048GQ100_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GQ100_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B310F2048GQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B310F2048GQ100_UNLOCK */ + +/** @} End of group EFM32GG11B310F2048GQ100_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B310F2048GQ100_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GQ100_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B310F2048GQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B310F2048GQ100_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B310F2048GQ100_AF_Pins */ + +/** @} End of group EFM32GG11B310F2048GQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B310F2048GQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gl112.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gl112.h new file mode 100644 index 0000000000000..3272abf62aa80 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gl112.h @@ -0,0 +1,9976 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B320F2048GL112 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B320F2048GL112_H +#define EFM32GG11B320F2048GL112_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112 EFM32GG11B320F2048GL112 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B320F2048GL112_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B320F2048GL112) +#define EFM32GG11B320F2048GL112 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B320F2048GL112" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B320F2048GL112 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B320F2048GL112_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_MSC MSC + * @{ + * @brief EFM32GG11B320F2048GL112_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_EMU EMU + * @{ + * @brief EFM32GG11B320F2048GL112_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_CMU CMU + * @{ + * @brief EFM32GG11B320F2048GL112_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_PRS PRS + * @{ + * @brief EFM32GG11B320F2048GL112_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_SMU SMU + * @{ + * @brief EFM32GG11B320F2048GL112_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B320F2048GL112_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B320F2048GL112_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B320F2048GL112_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B320F2048GL112_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GL112_PRS + * @{ + * @addtogroup EFM32GG11B320F2048GL112_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GL112_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GL112_WTIMER + * @{ + * @defgroup EFM32GG11B320F2048GL112_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GL112_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GL112_MSC + * @{ + * @defgroup EFM32GG11B320F2048GL112_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GL112_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GL112_EMU + * @{ + * @defgroup EFM32GG11B320F2048GL112_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GL112_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GL112_CMU + * @{ + * @defgroup EFM32GG11B320F2048GL112_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GL112_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GL112_PRS + * @{ + * @defgroup EFM32GG11B320F2048GL112_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GL112_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GL112_SMU + * @{ + * @defgroup EFM32GG11B320F2048GL112_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GL112_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GL112_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B320F2048GL112_UNLOCK */ + +/** @} End of group EFM32GG11B320F2048GL112_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GL112_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B320F2048GL112_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GL112_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GL112_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B320F2048GL112_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GL112_AF_Pins */ + +/** @} End of group EFM32GG11B320F2048GL112 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B320F2048GL112_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gq100.h new file mode 100644 index 0000000000000..f72d22bd767b9 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gq100.h @@ -0,0 +1,9976 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B320F2048GQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B320F2048GQ100_H +#define EFM32GG11B320F2048GQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100 EFM32GG11B320F2048GQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B320F2048GQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B320F2048GQ100) +#define EFM32GG11B320F2048GQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B320F2048GQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B320F2048GQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B320F2048GQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_MSC MSC + * @{ + * @brief EFM32GG11B320F2048GQ100_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_EMU EMU + * @{ + * @brief EFM32GG11B320F2048GQ100_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_CMU CMU + * @{ + * @brief EFM32GG11B320F2048GQ100_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_PRS PRS + * @{ + * @brief EFM32GG11B320F2048GQ100_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_SMU SMU + * @{ + * @brief EFM32GG11B320F2048GQ100_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B320F2048GQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B320F2048GQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B320F2048GQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B320F2048GQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GQ100_PRS + * @{ + * @addtogroup EFM32GG11B320F2048GQ100_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GQ100_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GQ100_WTIMER + * @{ + * @defgroup EFM32GG11B320F2048GQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GQ100_MSC + * @{ + * @defgroup EFM32GG11B320F2048GQ100_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GQ100_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GQ100_EMU + * @{ + * @defgroup EFM32GG11B320F2048GQ100_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GQ100_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GQ100_CMU + * @{ + * @defgroup EFM32GG11B320F2048GQ100_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GQ100_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GQ100_PRS + * @{ + * @defgroup EFM32GG11B320F2048GQ100_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GQ100_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GQ100_SMU + * @{ + * @defgroup EFM32GG11B320F2048GQ100_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GQ100_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B320F2048GQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B320F2048GQ100_UNLOCK */ + +/** @} End of group EFM32GG11B320F2048GQ100_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B320F2048GQ100_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GQ100_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B320F2048GQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B320F2048GQ100_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B320F2048GQ100_AF_Pins */ + +/** @} End of group EFM32GG11B320F2048GQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B320F2048GQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl112.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl112.h new file mode 100644 index 0000000000000..4aafc7f8909e2 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl112.h @@ -0,0 +1,1921 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B420F2048GL112 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B420F2048GL112_H +#define EFM32GG11B420F2048GL112_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL112 EFM32GG11B420F2048GL112 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL112_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B420F2048GL112_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL112_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B420F2048GL112) +#define EFM32GG11B420F2048GL112 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B420F2048GL112" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B420F2048GL112 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B420F2048GL112_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL112_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B420F2048GL112_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL112_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B420F2048GL112_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL112_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B420F2048GL112_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL112_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B420F2048GL112_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL112_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B420F2048GL112_WTIMER + * @{ + * @defgroup EFM32GG11B420F2048GL112_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B420F2048GL112_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL112_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B420F2048GL112_UNLOCK */ + +/** @} End of group EFM32GG11B420F2048GL112_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B420F2048GL112 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B420F2048GL112_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl120.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl120.h new file mode 100644 index 0000000000000..463ee7003fd7e --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl120.h @@ -0,0 +1,1921 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B420F2048GL120 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B420F2048GL120_H +#define EFM32GG11B420F2048GL120_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL120 EFM32GG11B420F2048GL120 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL120_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B420F2048GL120_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL120_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B420F2048GL120) +#define EFM32GG11B420F2048GL120 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B420F2048GL120" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B420F2048GL120 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B420F2048GL120_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL120_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B420F2048GL120_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL120_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B420F2048GL120_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL120_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B420F2048GL120_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL120_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B420F2048GL120_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL120_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B420F2048GL120_WTIMER + * @{ + * @defgroup EFM32GG11B420F2048GL120_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B420F2048GL120_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GL120_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B420F2048GL120_UNLOCK */ + +/** @} End of group EFM32GG11B420F2048GL120_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B420F2048GL120 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B420F2048GL120_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gm64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gm64.h new file mode 100644 index 0000000000000..0d5926e4a42b9 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gm64.h @@ -0,0 +1,1921 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B420F2048GM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B420F2048GM64_H +#define EFM32GG11B420F2048GM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GM64 EFM32GG11B420F2048GM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B420F2048GM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B420F2048GM64) +#define EFM32GG11B420F2048GM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B420F2048GM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B420F2048GM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B420F2048GM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B420F2048GM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B420F2048GM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B420F2048GM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B420F2048GM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B420F2048GM64_WTIMER + * @{ + * @defgroup EFM32GG11B420F2048GM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B420F2048GM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B420F2048GM64_UNLOCK */ + +/** @} End of group EFM32GG11B420F2048GM64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B420F2048GM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B420F2048GM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq100.h new file mode 100644 index 0000000000000..5865645de9e1d --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq100.h @@ -0,0 +1,1921 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B420F2048GQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B420F2048GQ100_H +#define EFM32GG11B420F2048GQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ100 EFM32GG11B420F2048GQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B420F2048GQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B420F2048GQ100) +#define EFM32GG11B420F2048GQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B420F2048GQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B420F2048GQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B420F2048GQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B420F2048GQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B420F2048GQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B420F2048GQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B420F2048GQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B420F2048GQ100_WTIMER + * @{ + * @defgroup EFM32GG11B420F2048GQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B420F2048GQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B420F2048GQ100_UNLOCK */ + +/** @} End of group EFM32GG11B420F2048GQ100_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B420F2048GQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B420F2048GQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq64.h new file mode 100644 index 0000000000000..ca3bf7942c89f --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq64.h @@ -0,0 +1,1921 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B420F2048GQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B420F2048GQ64_H +#define EFM32GG11B420F2048GQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ64 EFM32GG11B420F2048GQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B420F2048GQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B420F2048GQ64) +#define EFM32GG11B420F2048GQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B420F2048GQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B420F2048GQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B420F2048GQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B420F2048GQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B420F2048GQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B420F2048GQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B420F2048GQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B420F2048GQ64_WTIMER + * @{ + * @defgroup EFM32GG11B420F2048GQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B420F2048GQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048GQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B420F2048GQ64_UNLOCK */ + +/** @} End of group EFM32GG11B420F2048GQ64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B420F2048GQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B420F2048GQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il112.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il112.h new file mode 100644 index 0000000000000..eeb3950ffecd7 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il112.h @@ -0,0 +1,1921 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B420F2048IL112 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B420F2048IL112_H +#define EFM32GG11B420F2048IL112_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL112 EFM32GG11B420F2048IL112 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL112_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B420F2048IL112_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL112_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B420F2048IL112) +#define EFM32GG11B420F2048IL112 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B420F2048IL112" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B420F2048IL112 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B420F2048IL112_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL112_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B420F2048IL112_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL112_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B420F2048IL112_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL112_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B420F2048IL112_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL112_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B420F2048IL112_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL112_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B420F2048IL112_WTIMER + * @{ + * @defgroup EFM32GG11B420F2048IL112_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B420F2048IL112_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL112_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B420F2048IL112_UNLOCK */ + +/** @} End of group EFM32GG11B420F2048IL112_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B420F2048IL112 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B420F2048IL112_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il120.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il120.h new file mode 100644 index 0000000000000..7ac8c2f7249e4 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il120.h @@ -0,0 +1,1921 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B420F2048IL120 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B420F2048IL120_H +#define EFM32GG11B420F2048IL120_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL120 EFM32GG11B420F2048IL120 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL120_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B420F2048IL120_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL120_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B420F2048IL120) +#define EFM32GG11B420F2048IL120 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B420F2048IL120" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B420F2048IL120 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B420F2048IL120_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL120_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B420F2048IL120_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL120_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B420F2048IL120_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL120_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B420F2048IL120_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL120_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B420F2048IL120_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL120_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B420F2048IL120_WTIMER + * @{ + * @defgroup EFM32GG11B420F2048IL120_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B420F2048IL120_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IL120_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B420F2048IL120_UNLOCK */ + +/** @} End of group EFM32GG11B420F2048IL120_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B420F2048IL120 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B420F2048IL120_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048im64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048im64.h new file mode 100644 index 0000000000000..f4995289c4ff1 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048im64.h @@ -0,0 +1,1921 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B420F2048IM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B420F2048IM64_H +#define EFM32GG11B420F2048IM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IM64 EFM32GG11B420F2048IM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B420F2048IM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B420F2048IM64) +#define EFM32GG11B420F2048IM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B420F2048IM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B420F2048IM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B420F2048IM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B420F2048IM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B420F2048IM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B420F2048IM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B420F2048IM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B420F2048IM64_WTIMER + * @{ + * @defgroup EFM32GG11B420F2048IM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B420F2048IM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B420F2048IM64_UNLOCK */ + +/** @} End of group EFM32GG11B420F2048IM64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B420F2048IM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B420F2048IM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq100.h new file mode 100644 index 0000000000000..9268c86bc0545 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq100.h @@ -0,0 +1,1921 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B420F2048IQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B420F2048IQ100_H +#define EFM32GG11B420F2048IQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ100 EFM32GG11B420F2048IQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B420F2048IQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B420F2048IQ100) +#define EFM32GG11B420F2048IQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B420F2048IQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B420F2048IQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B420F2048IQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B420F2048IQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B420F2048IQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B420F2048IQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B420F2048IQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B420F2048IQ100_WTIMER + * @{ + * @defgroup EFM32GG11B420F2048IQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B420F2048IQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B420F2048IQ100_UNLOCK */ + +/** @} End of group EFM32GG11B420F2048IQ100_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B420F2048IQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B420F2048IQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq64.h new file mode 100644 index 0000000000000..490bf2129fe1e --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq64.h @@ -0,0 +1,1921 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B420F2048IQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B420F2048IQ64_H +#define EFM32GG11B420F2048IQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ64 EFM32GG11B420F2048IQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B420F2048IQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B420F2048IQ64) +#define EFM32GG11B420F2048IQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B420F2048IQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B420F2048IQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B420F2048IQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B420F2048IQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B420F2048IQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B420F2048IQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B420F2048IQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B420F2048IQ64_WTIMER + * @{ + * @defgroup EFM32GG11B420F2048IQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B420F2048IQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B420F2048IQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B420F2048IQ64_UNLOCK */ + +/** @} End of group EFM32GG11B420F2048IQ64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B420F2048IQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B420F2048IQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gl120.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gl120.h new file mode 100644 index 0000000000000..b5faf90f75046 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gl120.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B510F2048GL120 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B510F2048GL120_H +#define EFM32GG11B510F2048GL120_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120 EFM32GG11B510F2048GL120 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B510F2048GL120_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B510F2048GL120) +#define EFM32GG11B510F2048GL120 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B510F2048GL120" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B510F2048GL120 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B510F2048GL120_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_MSC MSC + * @{ + * @brief EFM32GG11B510F2048GL120_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_EMU EMU + * @{ + * @brief EFM32GG11B510F2048GL120_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_CMU CMU + * @{ + * @brief EFM32GG11B510F2048GL120_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_PRS PRS + * @{ + * @brief EFM32GG11B510F2048GL120_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_SMU SMU + * @{ + * @brief EFM32GG11B510F2048GL120_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B510F2048GL120_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B510F2048GL120_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B510F2048GL120_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B510F2048GL120_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GL120_PRS + * @{ + * @addtogroup EFM32GG11B510F2048GL120_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GL120_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GL120_WTIMER + * @{ + * @defgroup EFM32GG11B510F2048GL120_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GL120_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GL120_MSC + * @{ + * @defgroup EFM32GG11B510F2048GL120_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GL120_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GL120_EMU + * @{ + * @defgroup EFM32GG11B510F2048GL120_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GL120_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GL120_CMU + * @{ + * @defgroup EFM32GG11B510F2048GL120_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GL120_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GL120_PRS + * @{ + * @defgroup EFM32GG11B510F2048GL120_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GL120_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GL120_SMU + * @{ + * @defgroup EFM32GG11B510F2048GL120_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GL120_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GL120_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B510F2048GL120_UNLOCK */ + +/** @} End of group EFM32GG11B510F2048GL120_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GL120_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048GL120_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GL120_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GL120_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048GL120_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GL120_AF_Pins */ + +/** @} End of group EFM32GG11B510F2048GL120 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B510F2048GL120_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gm64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gm64.h new file mode 100644 index 0000000000000..be626b87d6ebc --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gm64.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B510F2048GM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B510F2048GM64_H +#define EFM32GG11B510F2048GM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64 EFM32GG11B510F2048GM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B510F2048GM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B510F2048GM64) +#define EFM32GG11B510F2048GM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B510F2048GM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B510F2048GM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B510F2048GM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_MSC MSC + * @{ + * @brief EFM32GG11B510F2048GM64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_EMU EMU + * @{ + * @brief EFM32GG11B510F2048GM64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_CMU CMU + * @{ + * @brief EFM32GG11B510F2048GM64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_PRS PRS + * @{ + * @brief EFM32GG11B510F2048GM64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_SMU SMU + * @{ + * @brief EFM32GG11B510F2048GM64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B510F2048GM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B510F2048GM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B510F2048GM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B510F2048GM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GM64_PRS + * @{ + * @addtogroup EFM32GG11B510F2048GM64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GM64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GM64_WTIMER + * @{ + * @defgroup EFM32GG11B510F2048GM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GM64_MSC + * @{ + * @defgroup EFM32GG11B510F2048GM64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GM64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GM64_EMU + * @{ + * @defgroup EFM32GG11B510F2048GM64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GM64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GM64_CMU + * @{ + * @defgroup EFM32GG11B510F2048GM64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GM64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GM64_PRS + * @{ + * @defgroup EFM32GG11B510F2048GM64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GM64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GM64_SMU + * @{ + * @defgroup EFM32GG11B510F2048GM64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GM64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B510F2048GM64_UNLOCK */ + +/** @} End of group EFM32GG11B510F2048GM64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048GM64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GM64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048GM64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GM64_AF_Pins */ + +/** @} End of group EFM32GG11B510F2048GM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B510F2048GM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq100.h new file mode 100644 index 0000000000000..9a87c9483b7ce --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq100.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B510F2048GQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B510F2048GQ100_H +#define EFM32GG11B510F2048GQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100 EFM32GG11B510F2048GQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B510F2048GQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B510F2048GQ100) +#define EFM32GG11B510F2048GQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B510F2048GQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B510F2048GQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B510F2048GQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_MSC MSC + * @{ + * @brief EFM32GG11B510F2048GQ100_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_EMU EMU + * @{ + * @brief EFM32GG11B510F2048GQ100_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_CMU CMU + * @{ + * @brief EFM32GG11B510F2048GQ100_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_PRS PRS + * @{ + * @brief EFM32GG11B510F2048GQ100_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_SMU SMU + * @{ + * @brief EFM32GG11B510F2048GQ100_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B510F2048GQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B510F2048GQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B510F2048GQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B510F2048GQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ100_PRS + * @{ + * @addtogroup EFM32GG11B510F2048GQ100_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ100_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ100_WTIMER + * @{ + * @defgroup EFM32GG11B510F2048GQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ100_MSC + * @{ + * @defgroup EFM32GG11B510F2048GQ100_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ100_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ100_EMU + * @{ + * @defgroup EFM32GG11B510F2048GQ100_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ100_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ100_CMU + * @{ + * @defgroup EFM32GG11B510F2048GQ100_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ100_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ100_PRS + * @{ + * @defgroup EFM32GG11B510F2048GQ100_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ100_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ100_SMU + * @{ + * @defgroup EFM32GG11B510F2048GQ100_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ100_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B510F2048GQ100_UNLOCK */ + +/** @} End of group EFM32GG11B510F2048GQ100_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048GQ100_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ100_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048GQ100_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ100_AF_Pins */ + +/** @} End of group EFM32GG11B510F2048GQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B510F2048GQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq64.h new file mode 100644 index 0000000000000..465bc9c6ef310 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq64.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B510F2048GQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B510F2048GQ64_H +#define EFM32GG11B510F2048GQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64 EFM32GG11B510F2048GQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B510F2048GQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B510F2048GQ64) +#define EFM32GG11B510F2048GQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B510F2048GQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B510F2048GQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B510F2048GQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_MSC MSC + * @{ + * @brief EFM32GG11B510F2048GQ64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_EMU EMU + * @{ + * @brief EFM32GG11B510F2048GQ64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_CMU CMU + * @{ + * @brief EFM32GG11B510F2048GQ64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_PRS PRS + * @{ + * @brief EFM32GG11B510F2048GQ64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_SMU SMU + * @{ + * @brief EFM32GG11B510F2048GQ64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B510F2048GQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B510F2048GQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B510F2048GQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B510F2048GQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ64_PRS + * @{ + * @addtogroup EFM32GG11B510F2048GQ64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ64_WTIMER + * @{ + * @defgroup EFM32GG11B510F2048GQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ64_MSC + * @{ + * @defgroup EFM32GG11B510F2048GQ64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ64_EMU + * @{ + * @defgroup EFM32GG11B510F2048GQ64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ64_CMU + * @{ + * @defgroup EFM32GG11B510F2048GQ64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ64_PRS + * @{ + * @defgroup EFM32GG11B510F2048GQ64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ64_SMU + * @{ + * @defgroup EFM32GG11B510F2048GQ64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048GQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B510F2048GQ64_UNLOCK */ + +/** @} End of group EFM32GG11B510F2048GQ64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048GQ64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048GQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048GQ64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048GQ64_AF_Pins */ + +/** @} End of group EFM32GG11B510F2048GQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B510F2048GQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048il120.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048il120.h new file mode 100644 index 0000000000000..b62bb08f9f3bf --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048il120.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B510F2048IL120 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B510F2048IL120_H +#define EFM32GG11B510F2048IL120_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120 EFM32GG11B510F2048IL120 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B510F2048IL120_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B510F2048IL120) +#define EFM32GG11B510F2048IL120 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B510F2048IL120" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B510F2048IL120 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B510F2048IL120_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_MSC MSC + * @{ + * @brief EFM32GG11B510F2048IL120_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_EMU EMU + * @{ + * @brief EFM32GG11B510F2048IL120_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_CMU CMU + * @{ + * @brief EFM32GG11B510F2048IL120_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_PRS PRS + * @{ + * @brief EFM32GG11B510F2048IL120_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_SMU SMU + * @{ + * @brief EFM32GG11B510F2048IL120_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B510F2048IL120_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B510F2048IL120_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B510F2048IL120_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B510F2048IL120_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IL120_PRS + * @{ + * @addtogroup EFM32GG11B510F2048IL120_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IL120_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IL120_WTIMER + * @{ + * @defgroup EFM32GG11B510F2048IL120_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IL120_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IL120_MSC + * @{ + * @defgroup EFM32GG11B510F2048IL120_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IL120_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IL120_EMU + * @{ + * @defgroup EFM32GG11B510F2048IL120_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IL120_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IL120_CMU + * @{ + * @defgroup EFM32GG11B510F2048IL120_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IL120_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IL120_PRS + * @{ + * @defgroup EFM32GG11B510F2048IL120_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IL120_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IL120_SMU + * @{ + * @defgroup EFM32GG11B510F2048IL120_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IL120_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IL120_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B510F2048IL120_UNLOCK */ + +/** @} End of group EFM32GG11B510F2048IL120_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IL120_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048IL120_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IL120_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IL120_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048IL120_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IL120_AF_Pins */ + +/** @} End of group EFM32GG11B510F2048IL120 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B510F2048IL120_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048im64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048im64.h new file mode 100644 index 0000000000000..fbd0b402e24ac --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048im64.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B510F2048IM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B510F2048IM64_H +#define EFM32GG11B510F2048IM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64 EFM32GG11B510F2048IM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B510F2048IM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B510F2048IM64) +#define EFM32GG11B510F2048IM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B510F2048IM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B510F2048IM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B510F2048IM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_MSC MSC + * @{ + * @brief EFM32GG11B510F2048IM64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_EMU EMU + * @{ + * @brief EFM32GG11B510F2048IM64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_CMU CMU + * @{ + * @brief EFM32GG11B510F2048IM64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_PRS PRS + * @{ + * @brief EFM32GG11B510F2048IM64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_SMU SMU + * @{ + * @brief EFM32GG11B510F2048IM64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B510F2048IM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B510F2048IM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B510F2048IM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B510F2048IM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IM64_PRS + * @{ + * @addtogroup EFM32GG11B510F2048IM64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IM64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IM64_WTIMER + * @{ + * @defgroup EFM32GG11B510F2048IM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IM64_MSC + * @{ + * @defgroup EFM32GG11B510F2048IM64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IM64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IM64_EMU + * @{ + * @defgroup EFM32GG11B510F2048IM64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IM64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IM64_CMU + * @{ + * @defgroup EFM32GG11B510F2048IM64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IM64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IM64_PRS + * @{ + * @defgroup EFM32GG11B510F2048IM64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IM64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IM64_SMU + * @{ + * @defgroup EFM32GG11B510F2048IM64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IM64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B510F2048IM64_UNLOCK */ + +/** @} End of group EFM32GG11B510F2048IM64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048IM64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IM64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048IM64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IM64_AF_Pins */ + +/** @} End of group EFM32GG11B510F2048IM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B510F2048IM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq100.h new file mode 100644 index 0000000000000..8eb93c4dae6d8 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq100.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B510F2048IQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B510F2048IQ100_H +#define EFM32GG11B510F2048IQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100 EFM32GG11B510F2048IQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B510F2048IQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B510F2048IQ100) +#define EFM32GG11B510F2048IQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B510F2048IQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B510F2048IQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B510F2048IQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_MSC MSC + * @{ + * @brief EFM32GG11B510F2048IQ100_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_EMU EMU + * @{ + * @brief EFM32GG11B510F2048IQ100_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_CMU CMU + * @{ + * @brief EFM32GG11B510F2048IQ100_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_PRS PRS + * @{ + * @brief EFM32GG11B510F2048IQ100_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_SMU SMU + * @{ + * @brief EFM32GG11B510F2048IQ100_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B510F2048IQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B510F2048IQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B510F2048IQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B510F2048IQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ100_PRS + * @{ + * @addtogroup EFM32GG11B510F2048IQ100_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ100_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ100_WTIMER + * @{ + * @defgroup EFM32GG11B510F2048IQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ100_MSC + * @{ + * @defgroup EFM32GG11B510F2048IQ100_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ100_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ100_EMU + * @{ + * @defgroup EFM32GG11B510F2048IQ100_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ100_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ100_CMU + * @{ + * @defgroup EFM32GG11B510F2048IQ100_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ100_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ100_PRS + * @{ + * @defgroup EFM32GG11B510F2048IQ100_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ100_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ100_SMU + * @{ + * @defgroup EFM32GG11B510F2048IQ100_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ100_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B510F2048IQ100_UNLOCK */ + +/** @} End of group EFM32GG11B510F2048IQ100_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048IQ100_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ100_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048IQ100_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ100_AF_Pins */ + +/** @} End of group EFM32GG11B510F2048IQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B510F2048IQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq64.h new file mode 100644 index 0000000000000..9edd5d17d245c --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq64.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B510F2048IQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B510F2048IQ64_H +#define EFM32GG11B510F2048IQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64 EFM32GG11B510F2048IQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B510F2048IQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B510F2048IQ64) +#define EFM32GG11B510F2048IQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B510F2048IQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B510F2048IQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00060000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B510F2048IQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_MSC MSC + * @{ + * @brief EFM32GG11B510F2048IQ64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_EMU EMU + * @{ + * @brief EFM32GG11B510F2048IQ64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_CMU CMU + * @{ + * @brief EFM32GG11B510F2048IQ64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_PRS PRS + * @{ + * @brief EFM32GG11B510F2048IQ64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_SMU SMU + * @{ + * @brief EFM32GG11B510F2048IQ64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B510F2048IQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B510F2048IQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B510F2048IQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B510F2048IQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ64_PRS + * @{ + * @addtogroup EFM32GG11B510F2048IQ64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ64_WTIMER + * @{ + * @defgroup EFM32GG11B510F2048IQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ64_MSC + * @{ + * @defgroup EFM32GG11B510F2048IQ64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ64_EMU + * @{ + * @defgroup EFM32GG11B510F2048IQ64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ64_CMU + * @{ + * @defgroup EFM32GG11B510F2048IQ64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ64_PRS + * @{ + * @defgroup EFM32GG11B510F2048IQ64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ64_SMU + * @{ + * @defgroup EFM32GG11B510F2048IQ64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B510F2048IQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B510F2048IQ64_UNLOCK */ + +/** @} End of group EFM32GG11B510F2048IQ64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048IQ64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B510F2048IQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B510F2048IQ64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B510F2048IQ64_AF_Pins */ + +/** @} End of group EFM32GG11B510F2048IQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B510F2048IQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gl120.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gl120.h new file mode 100644 index 0000000000000..b35f69924e773 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gl120.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B520F2048GL120 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B520F2048GL120_H +#define EFM32GG11B520F2048GL120_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120 EFM32GG11B520F2048GL120 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B520F2048GL120_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B520F2048GL120) +#define EFM32GG11B520F2048GL120 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B520F2048GL120" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B520F2048GL120 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B520F2048GL120_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_MSC MSC + * @{ + * @brief EFM32GG11B520F2048GL120_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_EMU EMU + * @{ + * @brief EFM32GG11B520F2048GL120_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_CMU CMU + * @{ + * @brief EFM32GG11B520F2048GL120_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_PRS PRS + * @{ + * @brief EFM32GG11B520F2048GL120_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_SMU SMU + * @{ + * @brief EFM32GG11B520F2048GL120_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B520F2048GL120_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B520F2048GL120_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B520F2048GL120_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B520F2048GL120_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GL120_PRS + * @{ + * @addtogroup EFM32GG11B520F2048GL120_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GL120_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GL120_WTIMER + * @{ + * @defgroup EFM32GG11B520F2048GL120_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GL120_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GL120_MSC + * @{ + * @defgroup EFM32GG11B520F2048GL120_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GL120_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GL120_EMU + * @{ + * @defgroup EFM32GG11B520F2048GL120_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GL120_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GL120_CMU + * @{ + * @defgroup EFM32GG11B520F2048GL120_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GL120_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GL120_PRS + * @{ + * @defgroup EFM32GG11B520F2048GL120_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GL120_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GL120_SMU + * @{ + * @defgroup EFM32GG11B520F2048GL120_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GL120_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GL120_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B520F2048GL120_UNLOCK */ + +/** @} End of group EFM32GG11B520F2048GL120_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GL120_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048GL120_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GL120_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GL120_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048GL120_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GL120_AF_Pins */ + +/** @} End of group EFM32GG11B520F2048GL120 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B520F2048GL120_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gm64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gm64.h new file mode 100644 index 0000000000000..f3a0152573ebe --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gm64.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B520F2048GM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B520F2048GM64_H +#define EFM32GG11B520F2048GM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64 EFM32GG11B520F2048GM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B520F2048GM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B520F2048GM64) +#define EFM32GG11B520F2048GM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B520F2048GM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B520F2048GM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B520F2048GM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_MSC MSC + * @{ + * @brief EFM32GG11B520F2048GM64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_EMU EMU + * @{ + * @brief EFM32GG11B520F2048GM64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_CMU CMU + * @{ + * @brief EFM32GG11B520F2048GM64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_PRS PRS + * @{ + * @brief EFM32GG11B520F2048GM64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_SMU SMU + * @{ + * @brief EFM32GG11B520F2048GM64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B520F2048GM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B520F2048GM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B520F2048GM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B520F2048GM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GM64_PRS + * @{ + * @addtogroup EFM32GG11B520F2048GM64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GM64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GM64_WTIMER + * @{ + * @defgroup EFM32GG11B520F2048GM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GM64_MSC + * @{ + * @defgroup EFM32GG11B520F2048GM64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GM64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GM64_EMU + * @{ + * @defgroup EFM32GG11B520F2048GM64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GM64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GM64_CMU + * @{ + * @defgroup EFM32GG11B520F2048GM64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GM64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GM64_PRS + * @{ + * @defgroup EFM32GG11B520F2048GM64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GM64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GM64_SMU + * @{ + * @defgroup EFM32GG11B520F2048GM64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GM64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B520F2048GM64_UNLOCK */ + +/** @} End of group EFM32GG11B520F2048GM64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048GM64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GM64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048GM64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GM64_AF_Pins */ + +/** @} End of group EFM32GG11B520F2048GM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B520F2048GM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq100.h new file mode 100644 index 0000000000000..6f493dc7a0a1a --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq100.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B520F2048GQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B520F2048GQ100_H +#define EFM32GG11B520F2048GQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100 EFM32GG11B520F2048GQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B520F2048GQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B520F2048GQ100) +#define EFM32GG11B520F2048GQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B520F2048GQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B520F2048GQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B520F2048GQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_MSC MSC + * @{ + * @brief EFM32GG11B520F2048GQ100_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_EMU EMU + * @{ + * @brief EFM32GG11B520F2048GQ100_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_CMU CMU + * @{ + * @brief EFM32GG11B520F2048GQ100_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_PRS PRS + * @{ + * @brief EFM32GG11B520F2048GQ100_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_SMU SMU + * @{ + * @brief EFM32GG11B520F2048GQ100_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B520F2048GQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B520F2048GQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B520F2048GQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B520F2048GQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ100_PRS + * @{ + * @addtogroup EFM32GG11B520F2048GQ100_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ100_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ100_WTIMER + * @{ + * @defgroup EFM32GG11B520F2048GQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ100_MSC + * @{ + * @defgroup EFM32GG11B520F2048GQ100_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ100_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ100_EMU + * @{ + * @defgroup EFM32GG11B520F2048GQ100_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ100_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ100_CMU + * @{ + * @defgroup EFM32GG11B520F2048GQ100_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ100_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ100_PRS + * @{ + * @defgroup EFM32GG11B520F2048GQ100_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ100_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ100_SMU + * @{ + * @defgroup EFM32GG11B520F2048GQ100_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ100_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B520F2048GQ100_UNLOCK */ + +/** @} End of group EFM32GG11B520F2048GQ100_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048GQ100_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ100_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048GQ100_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ100_AF_Pins */ + +/** @} End of group EFM32GG11B520F2048GQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B520F2048GQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq64.h new file mode 100644 index 0000000000000..44e05ea164163 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq64.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B520F2048GQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B520F2048GQ64_H +#define EFM32GG11B520F2048GQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64 EFM32GG11B520F2048GQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B520F2048GQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B520F2048GQ64) +#define EFM32GG11B520F2048GQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B520F2048GQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B520F2048GQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B520F2048GQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_MSC MSC + * @{ + * @brief EFM32GG11B520F2048GQ64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_EMU EMU + * @{ + * @brief EFM32GG11B520F2048GQ64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_CMU CMU + * @{ + * @brief EFM32GG11B520F2048GQ64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_PRS PRS + * @{ + * @brief EFM32GG11B520F2048GQ64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_SMU SMU + * @{ + * @brief EFM32GG11B520F2048GQ64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B520F2048GQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B520F2048GQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B520F2048GQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B520F2048GQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ64_PRS + * @{ + * @addtogroup EFM32GG11B520F2048GQ64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ64_WTIMER + * @{ + * @defgroup EFM32GG11B520F2048GQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ64_MSC + * @{ + * @defgroup EFM32GG11B520F2048GQ64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ64_EMU + * @{ + * @defgroup EFM32GG11B520F2048GQ64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ64_CMU + * @{ + * @defgroup EFM32GG11B520F2048GQ64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ64_PRS + * @{ + * @defgroup EFM32GG11B520F2048GQ64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ64_SMU + * @{ + * @defgroup EFM32GG11B520F2048GQ64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048GQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B520F2048GQ64_UNLOCK */ + +/** @} End of group EFM32GG11B520F2048GQ64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048GQ64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048GQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048GQ64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048GQ64_AF_Pins */ + +/** @} End of group EFM32GG11B520F2048GQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B520F2048GQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048il120.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048il120.h new file mode 100644 index 0000000000000..e5304d0ce1f19 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048il120.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B520F2048IL120 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B520F2048IL120_H +#define EFM32GG11B520F2048IL120_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120 EFM32GG11B520F2048IL120 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B520F2048IL120_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B520F2048IL120) +#define EFM32GG11B520F2048IL120 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B520F2048IL120" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B520F2048IL120 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B520F2048IL120_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_MSC MSC + * @{ + * @brief EFM32GG11B520F2048IL120_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_EMU EMU + * @{ + * @brief EFM32GG11B520F2048IL120_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_CMU CMU + * @{ + * @brief EFM32GG11B520F2048IL120_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_PRS PRS + * @{ + * @brief EFM32GG11B520F2048IL120_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_SMU SMU + * @{ + * @brief EFM32GG11B520F2048IL120_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B520F2048IL120_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B520F2048IL120_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B520F2048IL120_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B520F2048IL120_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IL120_PRS + * @{ + * @addtogroup EFM32GG11B520F2048IL120_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IL120_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IL120_WTIMER + * @{ + * @defgroup EFM32GG11B520F2048IL120_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IL120_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IL120_MSC + * @{ + * @defgroup EFM32GG11B520F2048IL120_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IL120_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IL120_EMU + * @{ + * @defgroup EFM32GG11B520F2048IL120_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IL120_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IL120_CMU + * @{ + * @defgroup EFM32GG11B520F2048IL120_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IL120_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IL120_PRS + * @{ + * @defgroup EFM32GG11B520F2048IL120_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IL120_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IL120_SMU + * @{ + * @defgroup EFM32GG11B520F2048IL120_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IL120_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IL120_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B520F2048IL120_UNLOCK */ + +/** @} End of group EFM32GG11B520F2048IL120_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IL120_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048IL120_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IL120_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IL120_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048IL120_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IL120_AF_Pins */ + +/** @} End of group EFM32GG11B520F2048IL120 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B520F2048IL120_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048im64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048im64.h new file mode 100644 index 0000000000000..a7afdf5617b2a --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048im64.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B520F2048IM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B520F2048IM64_H +#define EFM32GG11B520F2048IM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64 EFM32GG11B520F2048IM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B520F2048IM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B520F2048IM64) +#define EFM32GG11B520F2048IM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B520F2048IM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B520F2048IM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B520F2048IM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_MSC MSC + * @{ + * @brief EFM32GG11B520F2048IM64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_EMU EMU + * @{ + * @brief EFM32GG11B520F2048IM64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_CMU CMU + * @{ + * @brief EFM32GG11B520F2048IM64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_PRS PRS + * @{ + * @brief EFM32GG11B520F2048IM64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_SMU SMU + * @{ + * @brief EFM32GG11B520F2048IM64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B520F2048IM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B520F2048IM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B520F2048IM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B520F2048IM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IM64_PRS + * @{ + * @addtogroup EFM32GG11B520F2048IM64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IM64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IM64_WTIMER + * @{ + * @defgroup EFM32GG11B520F2048IM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IM64_MSC + * @{ + * @defgroup EFM32GG11B520F2048IM64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IM64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IM64_EMU + * @{ + * @defgroup EFM32GG11B520F2048IM64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IM64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IM64_CMU + * @{ + * @defgroup EFM32GG11B520F2048IM64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IM64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IM64_PRS + * @{ + * @defgroup EFM32GG11B520F2048IM64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IM64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IM64_SMU + * @{ + * @defgroup EFM32GG11B520F2048IM64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IM64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B520F2048IM64_UNLOCK */ + +/** @} End of group EFM32GG11B520F2048IM64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048IM64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IM64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IM64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048IM64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IM64_AF_Pins */ + +/** @} End of group EFM32GG11B520F2048IM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B520F2048IM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq100.h new file mode 100644 index 0000000000000..fcf174257f014 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq100.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B520F2048IQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B520F2048IQ100_H +#define EFM32GG11B520F2048IQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100 EFM32GG11B520F2048IQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B520F2048IQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B520F2048IQ100) +#define EFM32GG11B520F2048IQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B520F2048IQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B520F2048IQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B520F2048IQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_MSC MSC + * @{ + * @brief EFM32GG11B520F2048IQ100_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_EMU EMU + * @{ + * @brief EFM32GG11B520F2048IQ100_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_CMU CMU + * @{ + * @brief EFM32GG11B520F2048IQ100_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_PRS PRS + * @{ + * @brief EFM32GG11B520F2048IQ100_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_SMU SMU + * @{ + * @brief EFM32GG11B520F2048IQ100_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B520F2048IQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B520F2048IQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B520F2048IQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B520F2048IQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ100_PRS + * @{ + * @addtogroup EFM32GG11B520F2048IQ100_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ100_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ100_WTIMER + * @{ + * @defgroup EFM32GG11B520F2048IQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ100_MSC + * @{ + * @defgroup EFM32GG11B520F2048IQ100_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ100_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ100_EMU + * @{ + * @defgroup EFM32GG11B520F2048IQ100_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ100_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ100_CMU + * @{ + * @defgroup EFM32GG11B520F2048IQ100_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ100_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ100_PRS + * @{ + * @defgroup EFM32GG11B520F2048IQ100_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ100_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ100_SMU + * @{ + * @defgroup EFM32GG11B520F2048IQ100_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ100_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B520F2048IQ100_UNLOCK */ + +/** @} End of group EFM32GG11B520F2048IQ100_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048IQ100_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ100_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ100_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048IQ100_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ100_AF_Pins */ + +/** @} End of group EFM32GG11B520F2048IQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B520F2048IQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq64.h new file mode 100644 index 0000000000000..d030153def5a1 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq64.h @@ -0,0 +1,9978 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B520F2048IQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B520F2048IQ64_H +#define EFM32GG11B520F2048IQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64 EFM32GG11B520F2048IQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B520F2048IQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B520F2048IQ64) +#define EFM32GG11B520F2048IQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B520F2048IQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B520F2048IQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B520F2048IQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_MSC MSC + * @{ + * @brief EFM32GG11B520F2048IQ64_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_EMU EMU + * @{ + * @brief EFM32GG11B520F2048IQ64_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +#include "efm32gg11b_rmu.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_CMU CMU + * @{ + * @brief EFM32GG11B520F2048IQ64_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED20[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_PRS PRS + * @{ + * @brief EFM32GG11B520F2048IQ64_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_SMU SMU + * @{ + * @brief EFM32GG11B520F2048IQ64_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B520F2048IQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B520F2048IQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B520F2048IQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B520F2048IQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ64_PRS + * @{ + * @addtogroup EFM32GG11B520F2048IQ64_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ64_PRS */ + +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ64_WTIMER + * @{ + * @defgroup EFM32GG11B520F2048IQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ64_MSC + * @{ + * @defgroup EFM32GG11B520F2048IQ64_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ64_MSC */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ64_EMU + * @{ + * @defgroup EFM32GG11B520F2048IQ64_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ64_EMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ64_CMU + * @{ + * @defgroup EFM32GG11B520F2048IQ64_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ64_CMU */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ64_PRS + * @{ + * @defgroup EFM32GG11B520F2048IQ64_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ64_PRS */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ64_SMU + * @{ + * @defgroup EFM32GG11B520F2048IQ64_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ64_SMU */ + +/***************************************************************************//** + * @defgroup EFM32GG11B520F2048IQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B520F2048IQ64_UNLOCK */ + +/** @} End of group EFM32GG11B520F2048IQ64_BitFields */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048IQ64_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ64_AF_Ports */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B520F2048IQ64_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B520F2048IQ64_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B520F2048IQ64_AF_Pins */ + +/** @} End of group EFM32GG11B520F2048IQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B520F2048IQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl120.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl120.h new file mode 100644 index 0000000000000..69dea4140b480 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl120.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B820F2048GL120 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B820F2048GL120_H +#define EFM32GG11B820F2048GL120_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL120 EFM32GG11B820F2048GL120 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL120_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B820F2048GL120_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL120_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B820F2048GL120) +#define EFM32GG11B820F2048GL120 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B820F2048GL120" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B820F2048GL120 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B820F2048GL120_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL120_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B820F2048GL120_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL120_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B820F2048GL120_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL120_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B820F2048GL120_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL120_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B820F2048GL120_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL120_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B820F2048GL120_WTIMER + * @{ + * @defgroup EFM32GG11B820F2048GL120_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B820F2048GL120_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL120_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B820F2048GL120_UNLOCK */ + +/** @} End of group EFM32GG11B820F2048GL120_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B820F2048GL120 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B820F2048GL120_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl152.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl152.h new file mode 100644 index 0000000000000..524627f71d439 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl152.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B820F2048GL152 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B820F2048GL152_H +#define EFM32GG11B820F2048GL152_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL152 EFM32GG11B820F2048GL152 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL152_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B820F2048GL152_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL152_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B820F2048GL152) +#define EFM32GG11B820F2048GL152 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B820F2048GL152" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B820F2048GL152 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B820F2048GL152_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL152_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B820F2048GL152_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL152_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B820F2048GL152_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL152_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B820F2048GL152_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL152_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B820F2048GL152_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL152_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B820F2048GL152_WTIMER + * @{ + * @defgroup EFM32GG11B820F2048GL152_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B820F2048GL152_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL152_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B820F2048GL152_UNLOCK */ + +/** @} End of group EFM32GG11B820F2048GL152_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B820F2048GL152 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B820F2048GL152_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl192.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl192.h new file mode 100644 index 0000000000000..baf606d75f6df --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl192.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B820F2048GL192 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B820F2048GL192_H +#define EFM32GG11B820F2048GL192_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL192 EFM32GG11B820F2048GL192 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL192_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B820F2048GL192_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL192_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B820F2048GL192) +#define EFM32GG11B820F2048GL192 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B820F2048GL192" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B820F2048GL192 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B820F2048GL192_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL192_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B820F2048GL192_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL192_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B820F2048GL192_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL192_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B820F2048GL192_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL192_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B820F2048GL192_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL192_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B820F2048GL192_WTIMER + * @{ + * @defgroup EFM32GG11B820F2048GL192_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B820F2048GL192_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GL192_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B820F2048GL192_UNLOCK */ + +/** @} End of group EFM32GG11B820F2048GL192_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B820F2048GL192 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B820F2048GL192_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gm64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gm64.h new file mode 100644 index 0000000000000..f449a84047b33 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gm64.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B820F2048GM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B820F2048GM64_H +#define EFM32GG11B820F2048GM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GM64 EFM32GG11B820F2048GM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B820F2048GM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B820F2048GM64) +#define EFM32GG11B820F2048GM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B820F2048GM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B820F2048GM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B820F2048GM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B820F2048GM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B820F2048GM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B820F2048GM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B820F2048GM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B820F2048GM64_WTIMER + * @{ + * @defgroup EFM32GG11B820F2048GM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B820F2048GM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B820F2048GM64_UNLOCK */ + +/** @} End of group EFM32GG11B820F2048GM64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B820F2048GM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B820F2048GM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq100.h new file mode 100644 index 0000000000000..b992ee4a70751 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq100.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B820F2048GQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B820F2048GQ100_H +#define EFM32GG11B820F2048GQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ100 EFM32GG11B820F2048GQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B820F2048GQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B820F2048GQ100) +#define EFM32GG11B820F2048GQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B820F2048GQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B820F2048GQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B820F2048GQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B820F2048GQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B820F2048GQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B820F2048GQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B820F2048GQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B820F2048GQ100_WTIMER + * @{ + * @defgroup EFM32GG11B820F2048GQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B820F2048GQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B820F2048GQ100_UNLOCK */ + +/** @} End of group EFM32GG11B820F2048GQ100_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B820F2048GQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B820F2048GQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq64.h new file mode 100644 index 0000000000000..2eb18abf34348 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq64.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B820F2048GQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B820F2048GQ64_H +#define EFM32GG11B820F2048GQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ64 EFM32GG11B820F2048GQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B820F2048GQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B820F2048GQ64) +#define EFM32GG11B820F2048GQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B820F2048GQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B820F2048GQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B820F2048GQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B820F2048GQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B820F2048GQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B820F2048GQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B820F2048GQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B820F2048GQ64_WTIMER + * @{ + * @defgroup EFM32GG11B820F2048GQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B820F2048GQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048GQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B820F2048GQ64_UNLOCK */ + +/** @} End of group EFM32GG11B820F2048GQ64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B820F2048GQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B820F2048GQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il120.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il120.h new file mode 100644 index 0000000000000..78def01f2c820 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il120.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B820F2048IL120 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B820F2048IL120_H +#define EFM32GG11B820F2048IL120_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL120 EFM32GG11B820F2048IL120 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL120_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B820F2048IL120_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL120_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B820F2048IL120) +#define EFM32GG11B820F2048IL120 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B820F2048IL120" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B820F2048IL120 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B820F2048IL120_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL120_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B820F2048IL120_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL120_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B820F2048IL120_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL120_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B820F2048IL120_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL120_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B820F2048IL120_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL120_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B820F2048IL120_WTIMER + * @{ + * @defgroup EFM32GG11B820F2048IL120_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B820F2048IL120_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL120_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B820F2048IL120_UNLOCK */ + +/** @} End of group EFM32GG11B820F2048IL120_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B820F2048IL120 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B820F2048IL120_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il152.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il152.h new file mode 100644 index 0000000000000..e9579b1e6cbfb --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il152.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B820F2048IL152 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B820F2048IL152_H +#define EFM32GG11B820F2048IL152_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL152 EFM32GG11B820F2048IL152 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL152_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B820F2048IL152_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL152_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B820F2048IL152) +#define EFM32GG11B820F2048IL152 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B820F2048IL152" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B820F2048IL152 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B820F2048IL152_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL152_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B820F2048IL152_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL152_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B820F2048IL152_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL152_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B820F2048IL152_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL152_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B820F2048IL152_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL152_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B820F2048IL152_WTIMER + * @{ + * @defgroup EFM32GG11B820F2048IL152_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B820F2048IL152_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IL152_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B820F2048IL152_UNLOCK */ + +/** @} End of group EFM32GG11B820F2048IL152_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B820F2048IL152 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B820F2048IL152_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048im64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048im64.h new file mode 100644 index 0000000000000..02ace7a13bd0b --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048im64.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B820F2048IM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B820F2048IM64_H +#define EFM32GG11B820F2048IM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IM64 EFM32GG11B820F2048IM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B820F2048IM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B820F2048IM64) +#define EFM32GG11B820F2048IM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B820F2048IM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B820F2048IM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B820F2048IM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B820F2048IM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B820F2048IM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B820F2048IM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B820F2048IM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B820F2048IM64_WTIMER + * @{ + * @defgroup EFM32GG11B820F2048IM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B820F2048IM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B820F2048IM64_UNLOCK */ + +/** @} End of group EFM32GG11B820F2048IM64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B820F2048IM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B820F2048IM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq100.h new file mode 100644 index 0000000000000..ca5cdb2ce51a3 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq100.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B820F2048IQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B820F2048IQ100_H +#define EFM32GG11B820F2048IQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ100 EFM32GG11B820F2048IQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B820F2048IQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B820F2048IQ100) +#define EFM32GG11B820F2048IQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B820F2048IQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B820F2048IQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B820F2048IQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B820F2048IQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B820F2048IQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B820F2048IQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B820F2048IQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B820F2048IQ100_WTIMER + * @{ + * @defgroup EFM32GG11B820F2048IQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B820F2048IQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B820F2048IQ100_UNLOCK */ + +/** @} End of group EFM32GG11B820F2048IQ100_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B820F2048IQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B820F2048IQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq64.h new file mode 100644 index 0000000000000..eadd7c696b223 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq64.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B820F2048IQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B820F2048IQ64_H +#define EFM32GG11B820F2048IQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ64 EFM32GG11B820F2048IQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B820F2048IQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B820F2048IQ64) +#define EFM32GG11B820F2048IQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B820F2048IQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B820F2048IQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B820F2048IQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B820F2048IQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B820F2048IQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B820F2048IQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B820F2048IQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B820F2048IQ64_WTIMER + * @{ + * @defgroup EFM32GG11B820F2048IQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B820F2048IQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B820F2048IQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B820F2048IQ64_UNLOCK */ + +/** @} End of group EFM32GG11B820F2048IQ64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B820F2048IQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B820F2048IQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl120.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl120.h new file mode 100644 index 0000000000000..3ce4eae991e10 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl120.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B840F1024GL120 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B840F1024GL120_H +#define EFM32GG11B840F1024GL120_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL120 EFM32GG11B840F1024GL120 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL120_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B840F1024GL120_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL120_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B840F1024GL120) +#define EFM32GG11B840F1024GL120 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B840F1024GL120" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B840F1024GL120 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B840F1024GL120_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL120_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B840F1024GL120_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL120_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B840F1024GL120_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL120_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B840F1024GL120_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL120_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B840F1024GL120_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL120_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B840F1024GL120_WTIMER + * @{ + * @defgroup EFM32GG11B840F1024GL120_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B840F1024GL120_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL120_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B840F1024GL120_UNLOCK */ + +/** @} End of group EFM32GG11B840F1024GL120_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B840F1024GL120 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B840F1024GL120_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl152.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl152.h new file mode 100644 index 0000000000000..f479818d7d78b --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl152.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B840F1024GL152 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B840F1024GL152_H +#define EFM32GG11B840F1024GL152_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL152 EFM32GG11B840F1024GL152 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL152_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B840F1024GL152_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL152_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B840F1024GL152) +#define EFM32GG11B840F1024GL152 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B840F1024GL152" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B840F1024GL152 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B840F1024GL152_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL152_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B840F1024GL152_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL152_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B840F1024GL152_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL152_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B840F1024GL152_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL152_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B840F1024GL152_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL152_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B840F1024GL152_WTIMER + * @{ + * @defgroup EFM32GG11B840F1024GL152_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B840F1024GL152_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL152_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B840F1024GL152_UNLOCK */ + +/** @} End of group EFM32GG11B840F1024GL152_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B840F1024GL152 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B840F1024GL152_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl192.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl192.h new file mode 100644 index 0000000000000..f64e83541ce5b --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl192.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B840F1024GL192 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B840F1024GL192_H +#define EFM32GG11B840F1024GL192_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL192 EFM32GG11B840F1024GL192 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL192_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B840F1024GL192_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL192_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B840F1024GL192) +#define EFM32GG11B840F1024GL192 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B840F1024GL192" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B840F1024GL192 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B840F1024GL192_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL192_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B840F1024GL192_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL192_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B840F1024GL192_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL192_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B840F1024GL192_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL192_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B840F1024GL192_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL192_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B840F1024GL192_WTIMER + * @{ + * @defgroup EFM32GG11B840F1024GL192_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B840F1024GL192_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GL192_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B840F1024GL192_UNLOCK */ + +/** @} End of group EFM32GG11B840F1024GL192_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B840F1024GL192 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B840F1024GL192_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gm64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gm64.h new file mode 100644 index 0000000000000..368b4ebd6c721 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gm64.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B840F1024GM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B840F1024GM64_H +#define EFM32GG11B840F1024GM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GM64 EFM32GG11B840F1024GM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B840F1024GM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B840F1024GM64) +#define EFM32GG11B840F1024GM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B840F1024GM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B840F1024GM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B840F1024GM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B840F1024GM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B840F1024GM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B840F1024GM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B840F1024GM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B840F1024GM64_WTIMER + * @{ + * @defgroup EFM32GG11B840F1024GM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B840F1024GM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B840F1024GM64_UNLOCK */ + +/** @} End of group EFM32GG11B840F1024GM64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B840F1024GM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B840F1024GM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq100.h new file mode 100644 index 0000000000000..36faf381fb430 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq100.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B840F1024GQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B840F1024GQ100_H +#define EFM32GG11B840F1024GQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ100 EFM32GG11B840F1024GQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B840F1024GQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B840F1024GQ100) +#define EFM32GG11B840F1024GQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B840F1024GQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B840F1024GQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B840F1024GQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B840F1024GQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B840F1024GQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B840F1024GQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B840F1024GQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B840F1024GQ100_WTIMER + * @{ + * @defgroup EFM32GG11B840F1024GQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B840F1024GQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B840F1024GQ100_UNLOCK */ + +/** @} End of group EFM32GG11B840F1024GQ100_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B840F1024GQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B840F1024GQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq64.h new file mode 100644 index 0000000000000..91d868d31c41a --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq64.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B840F1024GQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B840F1024GQ64_H +#define EFM32GG11B840F1024GQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ64 EFM32GG11B840F1024GQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B840F1024GQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B840F1024GQ64) +#define EFM32GG11B840F1024GQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B840F1024GQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B840F1024GQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B840F1024GQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B840F1024GQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B840F1024GQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B840F1024GQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B840F1024GQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B840F1024GQ64_WTIMER + * @{ + * @defgroup EFM32GG11B840F1024GQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B840F1024GQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024GQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B840F1024GQ64_UNLOCK */ + +/** @} End of group EFM32GG11B840F1024GQ64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B840F1024GQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B840F1024GQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il120.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il120.h new file mode 100644 index 0000000000000..069325d609fa5 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il120.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B840F1024IL120 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B840F1024IL120_H +#define EFM32GG11B840F1024IL120_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL120 EFM32GG11B840F1024IL120 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL120_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B840F1024IL120_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL120_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B840F1024IL120) +#define EFM32GG11B840F1024IL120 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B840F1024IL120" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B840F1024IL120 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B840F1024IL120_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL120_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B840F1024IL120_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL120_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B840F1024IL120_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL120_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B840F1024IL120_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL120_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B840F1024IL120_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL120_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B840F1024IL120_WTIMER + * @{ + * @defgroup EFM32GG11B840F1024IL120_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B840F1024IL120_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL120_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B840F1024IL120_UNLOCK */ + +/** @} End of group EFM32GG11B840F1024IL120_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B840F1024IL120 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B840F1024IL120_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il152.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il152.h new file mode 100644 index 0000000000000..1e7c1a83f16e8 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il152.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B840F1024IL152 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B840F1024IL152_H +#define EFM32GG11B840F1024IL152_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL152 EFM32GG11B840F1024IL152 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL152_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B840F1024IL152_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL152_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B840F1024IL152) +#define EFM32GG11B840F1024IL152 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B840F1024IL152" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B840F1024IL152 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B840F1024IL152_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL152_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B840F1024IL152_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL152_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B840F1024IL152_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL152_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B840F1024IL152_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL152_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B840F1024IL152_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL152_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B840F1024IL152_WTIMER + * @{ + * @defgroup EFM32GG11B840F1024IL152_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B840F1024IL152_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IL152_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B840F1024IL152_UNLOCK */ + +/** @} End of group EFM32GG11B840F1024IL152_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B840F1024IL152 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B840F1024IL152_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024im64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024im64.h new file mode 100644 index 0000000000000..7b6255f5f7c81 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024im64.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B840F1024IM64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B840F1024IM64_H +#define EFM32GG11B840F1024IM64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IM64 EFM32GG11B840F1024IM64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IM64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B840F1024IM64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IM64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B840F1024IM64) +#define EFM32GG11B840F1024IM64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B840F1024IM64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B840F1024IM64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B840F1024IM64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IM64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B840F1024IM64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IM64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B840F1024IM64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IM64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B840F1024IM64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IM64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B840F1024IM64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IM64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B840F1024IM64_WTIMER + * @{ + * @defgroup EFM32GG11B840F1024IM64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B840F1024IM64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IM64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B840F1024IM64_UNLOCK */ + +/** @} End of group EFM32GG11B840F1024IM64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B840F1024IM64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B840F1024IM64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq100.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq100.h new file mode 100644 index 0000000000000..505fadf4f5aaf --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq100.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B840F1024IQ100 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B840F1024IQ100_H +#define EFM32GG11B840F1024IQ100_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ100 EFM32GG11B840F1024IQ100 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ100_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B840F1024IQ100_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ100_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B840F1024IQ100) +#define EFM32GG11B840F1024IQ100 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B840F1024IQ100" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B840F1024IQ100 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B840F1024IQ100_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ100_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B840F1024IQ100_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ100_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B840F1024IQ100_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ100_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B840F1024IQ100_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ100_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B840F1024IQ100_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ100_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B840F1024IQ100_WTIMER + * @{ + * @defgroup EFM32GG11B840F1024IQ100_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B840F1024IQ100_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ100_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B840F1024IQ100_UNLOCK */ + +/** @} End of group EFM32GG11B840F1024IQ100_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B840F1024IQ100 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B840F1024IQ100_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq64.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq64.h new file mode 100644 index 0000000000000..de53eac8c60b8 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq64.h @@ -0,0 +1,1923 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32GG11B840F1024IQ64 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +#ifndef EFM32GG11B840F1024IQ64_H +#define EFM32GG11B840F1024IQ64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ64 EFM32GG11B840F1024IQ64 + * @{ + ******************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ +/****** Cortex-M4 Processor Exceptions Numbers *******************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ + + EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ + LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ + SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ + TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ + I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ + GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ + TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ + TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ + USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ + USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ + UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ + UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ + UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ + UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ + LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ + LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ + LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ + PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ + PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ + RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ + CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ + MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ + CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ + USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ + USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ + USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ + WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ + WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ + WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ + I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ + VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ + TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ + TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ + TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ + USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ + USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ + CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ + EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ + ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ + ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ + LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ + SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ + ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ + CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ + CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ + USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ + RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ + WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ + LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ + TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ + QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ +} IRQn_Type; + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ64_Core Core + * @{ + * @brief Processor and Core Peripheral Section + ******************************************************************************/ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32GG11B840F1024IQ64_Core */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ64_Part Part + * @{ + ******************************************************************************/ + +/** Part family */ + +#define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32GG11B840F1024IQ64) +#define EFM32GG11B840F1024IQ64 1 /**< GIANT Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32GG11B840F1024IQ64" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ +#define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ +#define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ +#define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ +#define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ +#define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ +#define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ +#define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ +#define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ +#define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ +#define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ +#define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define USB_MEM_BASE (0x40100000UL) /**< USB base address */ +#define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ +#define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ +#define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ +#define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ +#define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ +#define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ +#define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ +#define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ +#define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ +#define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ +#define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ +#define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ +#define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ +#define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ +#define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ +#define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ +#define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ +#define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ +#define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ +#define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ +#define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ +#define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ +#define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ +#define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ + +/** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32GG11B840F1024IQ64 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 355U +/** AF channel maximum location number */ +#define AFCHANLOC_MAX 8U +/** Analog AF channels */ +#define AFACHAN_MAX 184U + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ +#define CAN_PRESENT /**< CAN is available in this part */ +#define CAN_COUNT 2 /**< 2 CANs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 7 /**< 7 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 4 /**< 4 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 6 /**< 6 USARTs available */ +#define UART_PRESENT /**< UART is available in this part */ +#define UART_COUNT 2 /**< 2 UARTs available */ +#define QSPI_PRESENT /**< QSPI is available in this part */ +#define QSPI_COUNT 1 /**< 1 QSPIs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 2 /**< 2 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 2 /**< 2 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 3 /**< 3 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 2 /**< 2 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 4 /**< 4 ACMPs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define MSC_PRESENT /**< MSC is available in this part */ +#define MSC_COUNT 1 /**< 1 MSC available */ +#define EMU_PRESENT /**< EMU is available in this part */ +#define EMU_COUNT 1 /**< 1 EMU available */ +#define RMU_PRESENT /**< RMU is available in this part */ +#define RMU_COUNT 1 /**< 1 RMU available */ +#define CMU_PRESENT /**< CMU is available in this part */ +#define CMU_COUNT 1 /**< 1 CMU available */ +#define LESENSE_PRESENT /**< LESENSE is available in this part */ +#define LESENSE_COUNT 1 /**< 1 LESENSE available */ +#define EBI_PRESENT /**< EBI is available in this part */ +#define EBI_COUNT 1 /**< 1 EBI available */ +#define ETH_PRESENT /**< ETH is available in this part */ +#define ETH_COUNT 1 /**< 1 ETH available */ +#define SDIO_PRESENT /**< SDIO is available in this part */ +#define SDIO_COUNT 1 /**< 1 SDIO available */ +#define GPIO_PRESENT /**< GPIO is available in this part */ +#define GPIO_COUNT 1 /**< 1 GPIO available */ +#define PRS_PRESENT /**< PRS is available in this part */ +#define PRS_COUNT 1 /**< 1 PRS available */ +#define LDMA_PRESENT /**< LDMA is available in this part */ +#define LDMA_COUNT 1 /**< 1 LDMA available */ +#define FPUEH_PRESENT /**< FPUEH is available in this part */ +#define FPUEH_COUNT 1 /**< 1 FPUEH available */ +#define GPCRC_PRESENT /**< GPCRC is available in this part */ +#define GPCRC_COUNT 1 /**< 1 GPCRC available */ +#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ +#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ +#define USB_PRESENT /**< USB is available in this part */ +#define USB_COUNT 1 /**< 1 USB available */ +#define BU_PRESENT /**< BU is available in this part */ +#define BU_COUNT 1 /**< 1 BU available */ +#define CSEN_PRESENT /**< CSEN is available in this part */ +#define CSEN_COUNT 1 /**< 1 CSEN available */ +#define LCD_PRESENT /**< LCD is available in this part */ +#define LCD_COUNT 1 /**< 1 LCD available */ +#define RTC_PRESENT /**< RTC is available in this part */ +#define RTC_COUNT 1 /**< 1 RTC available */ +#define RTCC_PRESENT /**< RTCC is available in this part */ +#define RTCC_COUNT 1 /**< 1 RTCC available */ +#define ETM_PRESENT /**< ETM is available in this part */ +#define ETM_COUNT 1 /**< 1 ETM available */ +#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ +#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ +#define SMU_PRESENT /**< SMU is available in this part */ +#define SMU_COUNT 1 /**< 1 SMU available */ +#define DCDC_PRESENT /**< DCDC is available in this part */ +#define DCDC_COUNT 1 /**< 1 DCDC available */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32gg11b.h" /* System Header File */ + +/** @} End of group EFM32GG11B840F1024IQ64_Part */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ64_Peripheral_TypeDefs Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + ******************************************************************************/ + +#include "efm32gg11b_msc.h" +#include "efm32gg11b_emu.h" +#include "efm32gg11b_rmu.h" +#include "efm32gg11b_cmu.h" +#include "efm32gg11b_crypto.h" +#include "efm32gg11b_lesense_st.h" +#include "efm32gg11b_lesense_buf.h" +#include "efm32gg11b_lesense_ch.h" +#include "efm32gg11b_lesense.h" +#include "efm32gg11b_ebi.h" +#include "efm32gg11b_eth.h" +#include "efm32gg11b_sdio.h" +#include "efm32gg11b_gpio_p.h" +#include "efm32gg11b_gpio.h" +#include "efm32gg11b_prs_ch.h" +#include "efm32gg11b_prs.h" +#include "efm32gg11b_ldma_ch.h" +#include "efm32gg11b_ldma.h" +#include "efm32gg11b_fpueh.h" +#include "efm32gg11b_gpcrc.h" +#include "efm32gg11b_can_mir.h" +#include "efm32gg11b_can.h" +#include "efm32gg11b_timer_cc.h" +#include "efm32gg11b_timer.h" +#include "efm32gg11b_usart.h" +#include "efm32gg11b_qspi.h" +#include "efm32gg11b_leuart.h" +#include "efm32gg11b_letimer.h" +#include "efm32gg11b_cryotimer.h" +#include "efm32gg11b_pcnt.h" +#include "efm32gg11b_i2c.h" +#include "efm32gg11b_adc.h" +#include "efm32gg11b_acmp.h" +#include "efm32gg11b_vdac_opa.h" +#include "efm32gg11b_vdac.h" +#include "efm32gg11b_usb_hc.h" +#include "efm32gg11b_usb_diep.h" +#include "efm32gg11b_usb_doep.h" +#include "efm32gg11b_usb.h" +#include "efm32gg11b_idac.h" +#include "efm32gg11b_csen.h" +#include "efm32gg11b_lcd.h" +#include "efm32gg11b_rtc_comp.h" +#include "efm32gg11b_rtc.h" +#include "efm32gg11b_rtcc_cc.h" +#include "efm32gg11b_rtcc_ret.h" +#include "efm32gg11b_rtcc.h" +#include "efm32gg11b_wdog_pch.h" +#include "efm32gg11b_wdog.h" +#include "efm32gg11b_etm.h" +#include "efm32gg11b_smu.h" +#include "efm32gg11b_trng.h" +#include "efm32gg11b_dma_descriptor.h" +#include "efm32gg11b_devinfo.h" +#include "efm32gg11b_romtable.h" + +/** @} End of group EFM32GG11B840F1024IQ64_Peripheral_TypeDefs */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ64_Peripheral_Base Peripheral Memory Map + * @{ + ******************************************************************************/ + +#define MSC_BASE (0x40000000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define EBI_BASE (0x4000B000UL) /**< EBI base address */ +#define ETH_BASE (0x40024000UL) /**< ETH base address */ +#define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ +#define GPIO_BASE (0x40088000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x40002000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ +#define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ +#define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ +#define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ +#define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ +#define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ +#define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define USART4_BASE (0x40011000UL) /**< USART4 base address */ +#define USART5_BASE (0x40011400UL) /**< USART5 base address */ +#define UART0_BASE (0x40014000UL) /**< UART0 base address */ +#define UART1_BASE (0x40014400UL) /**< UART1 base address */ +#define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ +#define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ +#define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ +#define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ +#define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ +#define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ +#define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ +#define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ +#define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ +#define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ +#define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ +#define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ +#define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ +#define USB_BASE (0x40022000UL) /**< USB base address */ +#define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ +#define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ +#define LCD_BASE (0x40054000UL) /**< LCD base address */ +#define RTC_BASE (0x40060000UL) /**< RTC base address */ +#define RTCC_BASE (0x40062000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40020000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32GG11B840F1024IQ64_Peripheral_Base */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ64_Peripheral_Declaration Peripheral Declarations + * @{ + ******************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ +#define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ +#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ +#define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ +#define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ +#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ +#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ +#define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32GG11B840F1024IQ64_Peripheral_Declaration */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ64_Peripheral_Offsets Peripheral Offsets + * @{ + ******************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ +#define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32GG11B840F1024IQ64_Peripheral_Offsets */ + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ64_BitFields Bit Fields + * @{ + ******************************************************************************/ + +#include "efm32gg11b_prs_signals.h" +#include "efm32gg11b_dmareq.h" + +/***************************************************************************//** + * @addtogroup EFM32GG11B840F1024IQ64_WTIMER + * @{ + * @defgroup EFM32GG11B840F1024IQ64_WTIMER_BitFields WTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B840F1024IQ64_WTIMER */ + +#include "efm32gg11b_uart.h" + +/***************************************************************************//** + * @defgroup EFM32GG11B840F1024IQ64_UNLOCK Unlock Codes + * @{ + ******************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32GG11B840F1024IQ64_UNLOCK */ + +/** @} End of group EFM32GG11B840F1024IQ64_BitFields */ + +#include "efm32gg11b_af_ports.h" +#include "efm32gg11b_af_pins.h" + +/** @} End of group EFM32GG11B840F1024IQ64 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32GG11B840F1024IQ64_H */ diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_acmp.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_acmp.h new file mode 100644 index 0000000000000..d02480522a15d --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_acmp.h @@ -0,0 +1,1390 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_ACMP register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_ACMP ACMP + * @{ + * @brief EFM32GG11B_ACMP Register Declaration + ******************************************************************************/ +/** ACMP Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTSEL; /**< Input Selection Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ + __IOM uint32_t HYSTERESIS0; /**< Hysteresis 0 Register */ + __IOM uint32_t HYSTERESIS1; /**< Hysteresis 1 Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pine Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t EXTIFCTRL; /**< External Override Interface Control */ +} ACMP_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_ACMP + * @{ + * @defgroup EFM32GG11B_ACMP_BitFields ACMP Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x07000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0xBF3CF70DUL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */ +#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */ +#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */ +#define ACMP_CTRL_APORTXMASTERDIS (0x1UL << 8) /**< APORT Bus X Master Disable */ +#define _ACMP_CTRL_APORTXMASTERDIS_SHIFT 8 /**< Shift value for ACMP_APORTXMASTERDIS */ +#define _ACMP_CTRL_APORTXMASTERDIS_MASK 0x100UL /**< Bit mask for ACMP_APORTXMASTERDIS */ +#define _ACMP_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTXMASTERDIS_DEFAULT (_ACMP_CTRL_APORTXMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTYMASTERDIS (0x1UL << 9) /**< APORT Bus Y Master Disable */ +#define _ACMP_CTRL_APORTYMASTERDIS_SHIFT 9 /**< Shift value for ACMP_APORTYMASTERDIS */ +#define _ACMP_CTRL_APORTYMASTERDIS_MASK 0x200UL /**< Bit mask for ACMP_APORTYMASTERDIS */ +#define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTYMASTERDIS_DEFAULT (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus Selected By VASEL */ +#define _ACMP_CTRL_APORTVMASTERDIS_SHIFT 10 /**< Shift value for ACMP_APORTVMASTERDIS */ +#define _ACMP_CTRL_APORTVMASTERDIS_MASK 0x400UL /**< Bit mask for ACMP_APORTVMASTERDIS */ +#define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTVMASTERDIS_DEFAULT (_ACMP_CTRL_APORTVMASTERDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_SHIFT 12 /**< Shift value for ACMP_PWRSEL */ +#define _ACMP_CTRL_PWRSEL_MASK 0x7000UL /**< Bit mask for ACMP_PWRSEL */ +#define _ACMP_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_AVDD 0x00000000UL /**< Mode AVDD for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_DVDD 0x00000001UL /**< Mode DVDD for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_IOVDD0 0x00000002UL /**< Mode IOVDD0 for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_IOVDD1 0x00000004UL /**< Mode IOVDD1 for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_DEFAULT (_ACMP_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_AVDD (_ACMP_CTRL_PWRSEL_AVDD << 12) /**< Shifted mode AVDD for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_DVDD (_ACMP_CTRL_PWRSEL_DVDD << 12) /**< Shifted mode DVDD for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_IOVDD0 (_ACMP_CTRL_PWRSEL_IOVDD0 << 12) /**< Shifted mode IOVDD0 for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_IOVDD1 (_ACMP_CTRL_PWRSEL_IOVDD1 << 12) /**< Shifted mode IOVDD1 for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP Accuracy Mode */ +#define _ACMP_CTRL_ACCURACY_SHIFT 15 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CTRL_ACCURACY_MASK 0x8000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CTRL_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_DEFAULT (_ACMP_CTRL_ACCURACY_DEFAULT << 15) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_LOW (_ACMP_CTRL_ACCURACY_LOW << 15) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_HIGH (_ACMP_CTRL_ACCURACY_HIGH << 15) /**< Shifted mode HIGH for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_SHIFT 18 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CTRL_INPUTRANGE_MASK 0xC0000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CTRL_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_GTVDDDIV2 0x00000001UL /**< Mode GTVDDDIV2 for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 0x00000002UL /**< Mode LTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_DEFAULT (_ACMP_CTRL_INPUTRANGE_DEFAULT << 18) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_FULL (_ACMP_CTRL_INPUTRANGE_FULL << 18) /**< Shifted mode FULL for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_GTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_GTVDDDIV2 << 18) /**< Shifted mode GTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_LTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_LTVDDDIV2 << 18) /**< Shifted mode LTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_IRISE (0x1UL << 20) /**< Rising Edge Interrupt Sense */ +#define _ACMP_CTRL_IRISE_SHIFT 20 /**< Shift value for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_MASK 0x100000UL /**< Bit mask for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 20) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 20) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 20) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL (0x1UL << 21) /**< Falling Edge Interrupt Sense */ +#define _ACMP_CTRL_IFALL_SHIFT 21 /**< Shift value for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_MASK 0x200000UL /**< Bit mask for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 21) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 21) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 21) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_MASK 0x3F000000UL /**< Bit mask for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */ +#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTSEL */ +#define _ACMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_MASK 0x757FFFFFUL /**< Mask for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_R5VOUT 0x000000F4UL /**< Mode R5VOUT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH0 (_ACMP_INPUTSEL_POSSEL_APORT0XCH0 << 0) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH1 (_ACMP_INPUTSEL_POSSEL_APORT0XCH1 << 0) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH2 (_ACMP_INPUTSEL_POSSEL_APORT0XCH2 << 0) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH3 (_ACMP_INPUTSEL_POSSEL_APORT0XCH3 << 0) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH4 (_ACMP_INPUTSEL_POSSEL_APORT0XCH4 << 0) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH5 (_ACMP_INPUTSEL_POSSEL_APORT0XCH5 << 0) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH6 (_ACMP_INPUTSEL_POSSEL_APORT0XCH6 << 0) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH7 (_ACMP_INPUTSEL_POSSEL_APORT0XCH7 << 0) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH8 (_ACMP_INPUTSEL_POSSEL_APORT0XCH8 << 0) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH9 (_ACMP_INPUTSEL_POSSEL_APORT0XCH9 << 0) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH10 (_ACMP_INPUTSEL_POSSEL_APORT0XCH10 << 0) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH11 (_ACMP_INPUTSEL_POSSEL_APORT0XCH11 << 0) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH12 (_ACMP_INPUTSEL_POSSEL_APORT0XCH12 << 0) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH13 (_ACMP_INPUTSEL_POSSEL_APORT0XCH13 << 0) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH14 (_ACMP_INPUTSEL_POSSEL_APORT0XCH14 << 0) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH15 (_ACMP_INPUTSEL_POSSEL_APORT0XCH15 << 0) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH0 (_ACMP_INPUTSEL_POSSEL_APORT0YCH0 << 0) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH1 (_ACMP_INPUTSEL_POSSEL_APORT0YCH1 << 0) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH2 (_ACMP_INPUTSEL_POSSEL_APORT0YCH2 << 0) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH3 (_ACMP_INPUTSEL_POSSEL_APORT0YCH3 << 0) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH4 (_ACMP_INPUTSEL_POSSEL_APORT0YCH4 << 0) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH5 (_ACMP_INPUTSEL_POSSEL_APORT0YCH5 << 0) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH6 (_ACMP_INPUTSEL_POSSEL_APORT0YCH6 << 0) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH7 (_ACMP_INPUTSEL_POSSEL_APORT0YCH7 << 0) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH8 (_ACMP_INPUTSEL_POSSEL_APORT0YCH8 << 0) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH9 (_ACMP_INPUTSEL_POSSEL_APORT0YCH9 << 0) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH10 (_ACMP_INPUTSEL_POSSEL_APORT0YCH10 << 0) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH11 (_ACMP_INPUTSEL_POSSEL_APORT0YCH11 << 0) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH12 (_ACMP_INPUTSEL_POSSEL_APORT0YCH12 << 0) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH13 (_ACMP_INPUTSEL_POSSEL_APORT0YCH13 << 0) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH14 (_ACMP_INPUTSEL_POSSEL_APORT0YCH14 << 0) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH15 (_ACMP_INPUTSEL_POSSEL_APORT0YCH15 << 0) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH0 (_ACMP_INPUTSEL_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH1 (_ACMP_INPUTSEL_POSSEL_APORT1YCH1 << 0) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH2 (_ACMP_INPUTSEL_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH3 (_ACMP_INPUTSEL_POSSEL_APORT1YCH3 << 0) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH4 (_ACMP_INPUTSEL_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH5 (_ACMP_INPUTSEL_POSSEL_APORT1YCH5 << 0) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH6 (_ACMP_INPUTSEL_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH7 (_ACMP_INPUTSEL_POSSEL_APORT1YCH7 << 0) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH8 (_ACMP_INPUTSEL_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH9 (_ACMP_INPUTSEL_POSSEL_APORT1YCH9 << 0) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH10 (_ACMP_INPUTSEL_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH11 (_ACMP_INPUTSEL_POSSEL_APORT1YCH11 << 0) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH12 (_ACMP_INPUTSEL_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH13 (_ACMP_INPUTSEL_POSSEL_APORT1YCH13 << 0) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH14 (_ACMP_INPUTSEL_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH15 (_ACMP_INPUTSEL_POSSEL_APORT1YCH15 << 0) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH16 (_ACMP_INPUTSEL_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH17 (_ACMP_INPUTSEL_POSSEL_APORT1YCH17 << 0) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH18 (_ACMP_INPUTSEL_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH19 (_ACMP_INPUTSEL_POSSEL_APORT1YCH19 << 0) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH20 (_ACMP_INPUTSEL_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH21 (_ACMP_INPUTSEL_POSSEL_APORT1YCH21 << 0) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH22 (_ACMP_INPUTSEL_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH23 (_ACMP_INPUTSEL_POSSEL_APORT1YCH23 << 0) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH24 (_ACMP_INPUTSEL_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH25 (_ACMP_INPUTSEL_POSSEL_APORT1YCH25 << 0) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH26 (_ACMP_INPUTSEL_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH27 (_ACMP_INPUTSEL_POSSEL_APORT1YCH27 << 0) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH28 (_ACMP_INPUTSEL_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH29 (_ACMP_INPUTSEL_POSSEL_APORT1YCH29 << 0) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH30 (_ACMP_INPUTSEL_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH31 (_ACMP_INPUTSEL_POSSEL_APORT1YCH31 << 0) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH0 (_ACMP_INPUTSEL_POSSEL_APORT2YCH0 << 0) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH1 (_ACMP_INPUTSEL_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH2 (_ACMP_INPUTSEL_POSSEL_APORT2YCH2 << 0) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH3 (_ACMP_INPUTSEL_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH4 (_ACMP_INPUTSEL_POSSEL_APORT2YCH4 << 0) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH5 (_ACMP_INPUTSEL_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH6 (_ACMP_INPUTSEL_POSSEL_APORT2YCH6 << 0) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH7 (_ACMP_INPUTSEL_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH8 (_ACMP_INPUTSEL_POSSEL_APORT2YCH8 << 0) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH9 (_ACMP_INPUTSEL_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH10 (_ACMP_INPUTSEL_POSSEL_APORT2YCH10 << 0) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH11 (_ACMP_INPUTSEL_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH12 (_ACMP_INPUTSEL_POSSEL_APORT2YCH12 << 0) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH13 (_ACMP_INPUTSEL_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH14 (_ACMP_INPUTSEL_POSSEL_APORT2YCH14 << 0) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH15 (_ACMP_INPUTSEL_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH16 (_ACMP_INPUTSEL_POSSEL_APORT2YCH16 << 0) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH17 (_ACMP_INPUTSEL_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH18 (_ACMP_INPUTSEL_POSSEL_APORT2YCH18 << 0) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH19 (_ACMP_INPUTSEL_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH20 (_ACMP_INPUTSEL_POSSEL_APORT2YCH20 << 0) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH21 (_ACMP_INPUTSEL_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH22 (_ACMP_INPUTSEL_POSSEL_APORT2YCH22 << 0) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH23 (_ACMP_INPUTSEL_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH24 (_ACMP_INPUTSEL_POSSEL_APORT2YCH24 << 0) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH25 (_ACMP_INPUTSEL_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH26 (_ACMP_INPUTSEL_POSSEL_APORT2YCH26 << 0) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH27 (_ACMP_INPUTSEL_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH28 (_ACMP_INPUTSEL_POSSEL_APORT2YCH28 << 0) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH29 (_ACMP_INPUTSEL_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH30 (_ACMP_INPUTSEL_POSSEL_APORT2YCH30 << 0) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH31 (_ACMP_INPUTSEL_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH0 (_ACMP_INPUTSEL_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH1 (_ACMP_INPUTSEL_POSSEL_APORT3YCH1 << 0) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH2 (_ACMP_INPUTSEL_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH3 (_ACMP_INPUTSEL_POSSEL_APORT3YCH3 << 0) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH4 (_ACMP_INPUTSEL_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH5 (_ACMP_INPUTSEL_POSSEL_APORT3YCH5 << 0) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH6 (_ACMP_INPUTSEL_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH7 (_ACMP_INPUTSEL_POSSEL_APORT3YCH7 << 0) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH8 (_ACMP_INPUTSEL_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH9 (_ACMP_INPUTSEL_POSSEL_APORT3YCH9 << 0) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH10 (_ACMP_INPUTSEL_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH11 (_ACMP_INPUTSEL_POSSEL_APORT3YCH11 << 0) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH12 (_ACMP_INPUTSEL_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH13 (_ACMP_INPUTSEL_POSSEL_APORT3YCH13 << 0) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH14 (_ACMP_INPUTSEL_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH15 (_ACMP_INPUTSEL_POSSEL_APORT3YCH15 << 0) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH16 (_ACMP_INPUTSEL_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH17 (_ACMP_INPUTSEL_POSSEL_APORT3YCH17 << 0) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH18 (_ACMP_INPUTSEL_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH19 (_ACMP_INPUTSEL_POSSEL_APORT3YCH19 << 0) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH20 (_ACMP_INPUTSEL_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH21 (_ACMP_INPUTSEL_POSSEL_APORT3YCH21 << 0) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH22 (_ACMP_INPUTSEL_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH23 (_ACMP_INPUTSEL_POSSEL_APORT3YCH23 << 0) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH24 (_ACMP_INPUTSEL_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH25 (_ACMP_INPUTSEL_POSSEL_APORT3YCH25 << 0) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH26 (_ACMP_INPUTSEL_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH27 (_ACMP_INPUTSEL_POSSEL_APORT3YCH27 << 0) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH28 (_ACMP_INPUTSEL_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH29 (_ACMP_INPUTSEL_POSSEL_APORT3YCH29 << 0) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH30 (_ACMP_INPUTSEL_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH31 (_ACMP_INPUTSEL_POSSEL_APORT3YCH31 << 0) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH0 (_ACMP_INPUTSEL_POSSEL_APORT4YCH0 << 0) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH1 (_ACMP_INPUTSEL_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH2 (_ACMP_INPUTSEL_POSSEL_APORT4YCH2 << 0) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH3 (_ACMP_INPUTSEL_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH4 (_ACMP_INPUTSEL_POSSEL_APORT4YCH4 << 0) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH5 (_ACMP_INPUTSEL_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH6 (_ACMP_INPUTSEL_POSSEL_APORT4YCH6 << 0) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH7 (_ACMP_INPUTSEL_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH8 (_ACMP_INPUTSEL_POSSEL_APORT4YCH8 << 0) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH9 (_ACMP_INPUTSEL_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH10 (_ACMP_INPUTSEL_POSSEL_APORT4YCH10 << 0) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH19 (_ACMP_INPUTSEL_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH20 (_ACMP_INPUTSEL_POSSEL_APORT4YCH20 << 0) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH21 (_ACMP_INPUTSEL_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH22 (_ACMP_INPUTSEL_POSSEL_APORT4YCH22 << 0) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH23 (_ACMP_INPUTSEL_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH24 (_ACMP_INPUTSEL_POSSEL_APORT4YCH24 << 0) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH25 (_ACMP_INPUTSEL_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH26 (_ACMP_INPUTSEL_POSSEL_APORT4YCH26 << 0) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH27 (_ACMP_INPUTSEL_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_R5VOUT (_ACMP_INPUTSEL_POSSEL_R5VOUT << 0) /**< Shifted mode R5VOUT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VDD (_ACMP_INPUTSEL_POSSEL_VDD << 0) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VSS (_ACMP_INPUTSEL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 8) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VSS (_ACMP_INPUTSEL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_SHIFT 16 /**< Shift value for ACMP_VASEL */ +#define _ACMP_INPUTSEL_VASEL_MASK 0x3F0000UL /**< Bit mask for ACMP_VASEL */ +#define _ACMP_INPUTSEL_VASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_VDD 0x00000000UL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH0 0x00000001UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH2 0x00000003UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH4 0x00000005UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH6 0x00000007UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH8 0x00000009UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH10 0x0000000BUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH12 0x0000000DUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH14 0x0000000FUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH16 0x00000011UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH18 0x00000013UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH20 0x00000015UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH22 0x00000017UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH24 0x00000019UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH26 0x0000001BUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH28 0x0000001DUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH30 0x0000001FUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_DEFAULT (_ACMP_INPUTSEL_VASEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_VDD (_ACMP_INPUTSEL_VASEL_VDD << 16) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH0 (_ACMP_INPUTSEL_VASEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH2 (_ACMP_INPUTSEL_VASEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH4 (_ACMP_INPUTSEL_VASEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH6 (_ACMP_INPUTSEL_VASEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH8 (_ACMP_INPUTSEL_VASEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH10 (_ACMP_INPUTSEL_VASEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH12 (_ACMP_INPUTSEL_VASEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH14 (_ACMP_INPUTSEL_VASEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH16 (_ACMP_INPUTSEL_VASEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH18 (_ACMP_INPUTSEL_VASEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH20 (_ACMP_INPUTSEL_VASEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH22 (_ACMP_INPUTSEL_VASEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH24 (_ACMP_INPUTSEL_VASEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH26 (_ACMP_INPUTSEL_VASEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH28 (_ACMP_INPUTSEL_VASEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH30 (_ACMP_INPUTSEL_VASEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH0 (_ACMP_INPUTSEL_VASEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH1 (_ACMP_INPUTSEL_VASEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH2 (_ACMP_INPUTSEL_VASEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH3 (_ACMP_INPUTSEL_VASEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH4 (_ACMP_INPUTSEL_VASEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH5 (_ACMP_INPUTSEL_VASEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH6 (_ACMP_INPUTSEL_VASEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH7 (_ACMP_INPUTSEL_VASEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH8 (_ACMP_INPUTSEL_VASEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH9 (_ACMP_INPUTSEL_VASEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH10 (_ACMP_INPUTSEL_VASEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH11 (_ACMP_INPUTSEL_VASEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH12 (_ACMP_INPUTSEL_VASEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH13 (_ACMP_INPUTSEL_VASEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH14 (_ACMP_INPUTSEL_VASEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH15 (_ACMP_INPUTSEL_VASEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH16 (_ACMP_INPUTSEL_VASEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH17 (_ACMP_INPUTSEL_VASEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH18 (_ACMP_INPUTSEL_VASEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH19 (_ACMP_INPUTSEL_VASEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH20 (_ACMP_INPUTSEL_VASEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH21 (_ACMP_INPUTSEL_VASEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH22 (_ACMP_INPUTSEL_VASEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH23 (_ACMP_INPUTSEL_VASEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH24 (_ACMP_INPUTSEL_VASEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH25 (_ACMP_INPUTSEL_VASEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH26 (_ACMP_INPUTSEL_VASEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH27 (_ACMP_INPUTSEL_VASEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH28 (_ACMP_INPUTSEL_VASEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH29 (_ACMP_INPUTSEL_VASEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH30 (_ACMP_INPUTSEL_VASEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH31 (_ACMP_INPUTSEL_VASEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL (0x1UL << 22) /**< VB Selection */ +#define _ACMP_INPUTSEL_VBSEL_SHIFT 22 /**< Shift value for ACMP_VBSEL */ +#define _ACMP_INPUTSEL_VBSEL_MASK 0x400000UL /**< Bit mask for ACMP_VBSEL */ +#define _ACMP_INPUTSEL_VBSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VBSEL_1V25 0x00000000UL /**< Mode 1V25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VBSEL_2V5 0x00000001UL /**< Mode 2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_DEFAULT (_ACMP_INPUTSEL_VBSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_1V25 (_ACMP_INPUTSEL_VBSEL_1V25 << 22) /**< Shifted mode 1V25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_2V5 (_ACMP_INPUTSEL_VBSEL_2V5 << 22) /**< Shifted mode 2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL (0x1UL << 24) /**< Low-Power Sampled Voltage Selection */ +#define _ACMP_INPUTSEL_VLPSEL_SHIFT 24 /**< Shift value for ACMP_VLPSEL */ +#define _ACMP_INPUTSEL_VLPSEL_MASK 0x1000000UL /**< Bit mask for ACMP_VLPSEL */ +#define _ACMP_INPUTSEL_VLPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VLPSEL_VADIV 0x00000000UL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VLPSEL_VBDIV 0x00000001UL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_DEFAULT (_ACMP_INPUTSEL_VLPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_VADIV (_ACMP_INPUTSEL_VLPSEL_VADIV << 24) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_VBDIV (_ACMP_INPUTSEL_VLPSEL_VBDIV << 24) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN (0x1UL << 26) /**< Capacitive Sense Mode Internal Resistor Enable */ +#define _ACMP_INPUTSEL_CSRESEN_SHIFT 26 /**< Shift value for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_MASK 0x4000000UL /**< Bit mask for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 26) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES7 0x00000007UL /**< Mode RES7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES4 (_ACMP_INPUTSEL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES5 (_ACMP_INPUTSEL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES6 (_ACMP_INPUTSEL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES7 (_ACMP_INPUTSEL_CSRESSEL_RES7 << 28) /**< Shifted mode RES7 for ACMP_INPUTSEL */ + +/* Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000000FUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */ +#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Output */ +#define _ACMP_STATUS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_STATUS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_APORTCONFLICT_DEFAULT (_ACMP_STATUS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_EXTIFACT (0x1UL << 3) /**< External Override Interface Active */ +#define _ACMP_STATUS_EXTIFACT_SHIFT 3 /**< Shift value for ACMP_EXTIFACT */ +#define _ACMP_STATUS_EXTIFACT_MASK 0x8UL /**< Bit mask for ACMP_EXTIFACT */ +#define _ACMP_STATUS_EXTIFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_EXTIFACT_DEFAULT (_ACMP_STATUS_EXTIFACT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x00000007UL /**< Mask for ACMP_IF */ +#define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ +#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */ +#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Interrupt Flag */ +#define _ACMP_IF_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IF_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_APORTCONFLICT_DEFAULT (_ACMP_IF_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IFS */ +#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */ +#define _ACMP_IFS_MASK 0x00000007UL /**< Mask for ACMP_IFS */ +#define ACMP_IFS_EDGE (0x1UL << 0) /**< Set EDGE Interrupt Flag */ +#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP (0x1UL << 1) /**< Set WARMUP Interrupt Flag */ +#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_APORTCONFLICT (0x1UL << 2) /**< Set APORTCONFLICT Interrupt Flag */ +#define _ACMP_IFS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IFS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_APORTCONFLICT_DEFAULT (_ACMP_IFS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFS */ + +/* Bit fields for ACMP IFC */ +#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */ +#define _ACMP_IFC_MASK 0x00000007UL /**< Mask for ACMP_IFC */ +#define ACMP_IFC_EDGE (0x1UL << 0) /**< Clear EDGE Interrupt Flag */ +#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP (0x1UL << 1) /**< Clear WARMUP Interrupt Flag */ +#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_APORTCONFLICT (0x1UL << 2) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _ACMP_IFC_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IFC_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_APORTCONFLICT_DEFAULT (_ACMP_IFC_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFC */ + +/* Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x00000007UL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_EDGE (0x1UL << 0) /**< EDGE Interrupt Enable */ +#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP (0x1UL << 1) /**< WARMUP Interrupt Enable */ +#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_APORTCONFLICT (0x1UL << 2) /**< APORTCONFLICT Interrupt Enable */ +#define _ACMP_IEN_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IEN_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_APORTCONFLICT_DEFAULT (_ACMP_IEN_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP APORTREQ */ +#define _ACMP_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTREQ */ +#define _ACMP_APORTREQ_MASK 0x000003FFUL /**< Mask for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */ +#define _ACMP_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ACMP_APORT0XREQ */ +#define _ACMP_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ACMP_APORT0XREQ */ +#define _ACMP_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0XREQ_DEFAULT (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */ +#define _ACMP_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ACMP_APORT0YREQ */ +#define _ACMP_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ACMP_APORT0YREQ */ +#define _ACMP_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0YREQ_DEFAULT (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */ +#define _ACMP_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ACMP_APORT1XREQ */ +#define _ACMP_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ACMP_APORT1XREQ */ +#define _ACMP_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1XREQ_DEFAULT (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */ +#define _ACMP_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ACMP_APORT1YREQ */ +#define _ACMP_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ACMP_APORT1YREQ */ +#define _ACMP_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1YREQ_DEFAULT (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */ +#define _ACMP_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ACMP_APORT2XREQ */ +#define _ACMP_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ACMP_APORT2XREQ */ +#define _ACMP_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2XREQ_DEFAULT (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */ +#define _ACMP_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ACMP_APORT2YREQ */ +#define _ACMP_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ACMP_APORT2YREQ */ +#define _ACMP_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2YREQ_DEFAULT (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */ +#define _ACMP_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ACMP_APORT3XREQ */ +#define _ACMP_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ACMP_APORT3XREQ */ +#define _ACMP_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3XREQ_DEFAULT (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */ +#define _ACMP_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ACMP_APORT3YREQ */ +#define _ACMP_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ACMP_APORT3YREQ */ +#define _ACMP_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3YREQ_DEFAULT (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */ +#define _ACMP_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ACMP_APORT4XREQ */ +#define _ACMP_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ACMP_APORT4XREQ */ +#define _ACMP_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4XREQ_DEFAULT (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */ +#define _ACMP_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ACMP_APORT4YREQ */ +#define _ACMP_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ACMP_APORT4YREQ */ +#define _ACMP_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4YREQ_DEFAULT (_ACMP_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ + +/* Bit fields for ACMP APORTCONFLICT */ +#define _ACMP_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTCONFLICT */ +#define _ACMP_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ACMP_APORT0XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ACMP_APORT0XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ACMP_APORT0YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ACMP_APORT0YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORT1XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORT1XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ACMP_APORT1YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_APORT1YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ACMP_APORT2XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ACMP_APORT2XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ACMP_APORT2YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ACMP_APORT2YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ACMP_APORT3XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ACMP_APORT3XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ACMP_APORT3YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ACMP_APORT3YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ACMP_APORT4XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ACMP_APORT4XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ACMP_APORT4YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ACMP_APORT4YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ + +/* Bit fields for ACMP HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ +#define _ACMP_HYSTERESIS0_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ +#define _ACMP_HYSTERESIS0_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_DEFAULT (_ACMP_HYSTERESIS0_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST0 (_ACMP_HYSTERESIS0_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST1 (_ACMP_HYSTERESIS0_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST2 (_ACMP_HYSTERESIS0_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST3 (_ACMP_HYSTERESIS0_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST4 (_ACMP_HYSTERESIS0_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST5 (_ACMP_HYSTERESIS0_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST6 (_ACMP_HYSTERESIS0_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST7 (_ACMP_HYSTERESIS0_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST8 (_ACMP_HYSTERESIS0_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST9 (_ACMP_HYSTERESIS0_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST10 (_ACMP_HYSTERESIS0_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST11 (_ACMP_HYSTERESIS0_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST12 (_ACMP_HYSTERESIS0_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST13 (_ACMP_HYSTERESIS0_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST14 (_ACMP_HYSTERESIS0_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST15 (_ACMP_HYSTERESIS0_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS0_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS0_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_DIVVA_DEFAULT (_ACMP_HYSTERESIS0_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS0_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS0_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_DIVVB_DEFAULT (_ACMP_HYSTERESIS0_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ + +/* Bit fields for ACMP HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ +#define _ACMP_HYSTERESIS1_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ +#define _ACMP_HYSTERESIS1_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_DEFAULT (_ACMP_HYSTERESIS1_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST0 (_ACMP_HYSTERESIS1_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST1 (_ACMP_HYSTERESIS1_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST2 (_ACMP_HYSTERESIS1_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST3 (_ACMP_HYSTERESIS1_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST4 (_ACMP_HYSTERESIS1_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST5 (_ACMP_HYSTERESIS1_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST6 (_ACMP_HYSTERESIS1_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST7 (_ACMP_HYSTERESIS1_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST8 (_ACMP_HYSTERESIS1_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST9 (_ACMP_HYSTERESIS1_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST10 (_ACMP_HYSTERESIS1_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST11 (_ACMP_HYSTERESIS1_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST12 (_ACMP_HYSTERESIS1_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST13 (_ACMP_HYSTERESIS1_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST14 (_ACMP_HYSTERESIS1_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST15 (_ACMP_HYSTERESIS1_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS1_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS1_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_DIVVA_DEFAULT (_ACMP_HYSTERESIS1_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS1_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS1_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_DIVVB_DEFAULT (_ACMP_HYSTERESIS1_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ + +/* Bit fields for ACMP ROUTEPEN */ +#define _ACMP_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTEPEN */ +#define _ACMP_ROUTEPEN_MASK 0x00000001UL /**< Mask for ACMP_ROUTEPEN */ +#define ACMP_ROUTEPEN_OUTPEN (0x1UL << 0) /**< ACMP Output Pin Enable */ +#define _ACMP_ROUTEPEN_OUTPEN_SHIFT 0 /**< Shift value for ACMP_OUTPEN */ +#define _ACMP_ROUTEPEN_OUTPEN_MASK 0x1UL /**< Bit mask for ACMP_OUTPEN */ +#define _ACMP_ROUTEPEN_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTEPEN */ +#define ACMP_ROUTEPEN_OUTPEN_DEFAULT (_ACMP_ROUTEPEN_OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTEPEN */ + +/* Bit fields for ACMP ROUTELOC0 */ +#define _ACMP_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_MASK 0x00000007UL /**< Mask for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_SHIFT 0 /**< Shift value for ACMP_OUTLOC */ +#define _ACMP_ROUTELOC0_OUTLOC_MASK 0x7UL /**< Bit mask for ACMP_OUTLOC */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC4 0x00000004UL /**< Mode LOC4 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC5 0x00000005UL /**< Mode LOC5 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC6 0x00000006UL /**< Mode LOC6 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC7 0x00000007UL /**< Mode LOC7 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC0 (_ACMP_ROUTELOC0_OUTLOC_LOC0 << 0) /**< Shifted mode LOC0 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_DEFAULT (_ACMP_ROUTELOC0_OUTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC1 (_ACMP_ROUTELOC0_OUTLOC_LOC1 << 0) /**< Shifted mode LOC1 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC2 (_ACMP_ROUTELOC0_OUTLOC_LOC2 << 0) /**< Shifted mode LOC2 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC3 (_ACMP_ROUTELOC0_OUTLOC_LOC3 << 0) /**< Shifted mode LOC3 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC4 (_ACMP_ROUTELOC0_OUTLOC_LOC4 << 0) /**< Shifted mode LOC4 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC5 (_ACMP_ROUTELOC0_OUTLOC_LOC5 << 0) /**< Shifted mode LOC5 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC6 (_ACMP_ROUTELOC0_OUTLOC_LOC6 << 0) /**< Shifted mode LOC6 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC7 (_ACMP_ROUTELOC0_OUTLOC_LOC7 << 0) /**< Shifted mode LOC7 for ACMP_ROUTELOC0 */ + +/* Bit fields for ACMP EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_MASK 0x000000F1UL /**< Mask for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_EN (0x1UL << 0) /**< Enable External Interface */ +#define _ACMP_EXTIFCTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EXTIFCTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EXTIFCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_EN_DEFAULT (_ACMP_EXTIFCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_SHIFT 4 /**< Shift value for ACMP_APORTSEL */ +#define _ACMP_EXTIFCTRL_APORTSEL_MASK 0xF0UL /**< Bit mask for ACMP_APORTSEL */ +#define _ACMP_EXTIFCTRL_APORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT0X 0x00000000UL /**< Mode APORT0X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT0Y 0x00000001UL /**< Mode APORT0Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1X 0x00000002UL /**< Mode APORT1X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1Y 0x00000003UL /**< Mode APORT1Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1XY 0x00000004UL /**< Mode APORT1XY for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2X 0x00000005UL /**< Mode APORT2X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2Y 0x00000006UL /**< Mode APORT2Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2YX 0x00000007UL /**< Mode APORT2YX for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3X 0x00000008UL /**< Mode APORT3X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3Y 0x00000009UL /**< Mode APORT3Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3XY 0x0000000AUL /**< Mode APORT3XY for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4X 0x0000000BUL /**< Mode APORT4X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4Y 0x0000000CUL /**< Mode APORT4Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4YX 0x0000000DUL /**< Mode APORT4YX for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_DEFAULT (_ACMP_EXTIFCTRL_APORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT0X (_ACMP_EXTIFCTRL_APORTSEL_APORT0X << 4) /**< Shifted mode APORT0X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT0Y (_ACMP_EXTIFCTRL_APORTSEL_APORT0Y << 4) /**< Shifted mode APORT0Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1X (_ACMP_EXTIFCTRL_APORTSEL_APORT1X << 4) /**< Shifted mode APORT1X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1Y (_ACMP_EXTIFCTRL_APORTSEL_APORT1Y << 4) /**< Shifted mode APORT1Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1XY (_ACMP_EXTIFCTRL_APORTSEL_APORT1XY << 4) /**< Shifted mode APORT1XY for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2X (_ACMP_EXTIFCTRL_APORTSEL_APORT2X << 4) /**< Shifted mode APORT2X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2Y (_ACMP_EXTIFCTRL_APORTSEL_APORT2Y << 4) /**< Shifted mode APORT2Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2YX (_ACMP_EXTIFCTRL_APORTSEL_APORT2YX << 4) /**< Shifted mode APORT2YX for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3X (_ACMP_EXTIFCTRL_APORTSEL_APORT3X << 4) /**< Shifted mode APORT3X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3Y (_ACMP_EXTIFCTRL_APORTSEL_APORT3Y << 4) /**< Shifted mode APORT3Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3XY (_ACMP_EXTIFCTRL_APORTSEL_APORT3XY << 4) /**< Shifted mode APORT3XY for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4X (_ACMP_EXTIFCTRL_APORTSEL_APORT4X << 4) /**< Shifted mode APORT4X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4Y (_ACMP_EXTIFCTRL_APORTSEL_APORT4Y << 4) /**< Shifted mode APORT4Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4YX (_ACMP_EXTIFCTRL_APORTSEL_APORT4YX << 4) /**< Shifted mode APORT4YX for ACMP_EXTIFCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B_ACMP */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_adc.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_adc.h new file mode 100644 index 0000000000000..c35a0330d3e67 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_adc.h @@ -0,0 +1,2435 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_ADC register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_ADC ADC + * @{ + * @brief EFM32GG11B_ADC Register Declaration + ******************************************************************************/ +/** ADC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t SINGLECTRL; /**< Single Channel Control Register */ + __IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register Continued */ + __IOM uint32_t SCANCTRL; /**< Scan Control Register */ + __IOM uint32_t SCANCTRLX; /**< Scan Control Register Continued */ + __IOM uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */ + __IOM uint32_t SCANINPUTSEL; /**< Input Selection Register for Scan Mode */ + __IOM uint32_t SCANNEGSEL; /**< Negative Input Select Register for Scan */ + __IOM uint32_t CMPTHR; /**< Compare Threshold Register */ + __IOM uint32_t BIASPROG; /**< Bias Programming Register for Various Analog Blocks Used in ADC Operation */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */ + __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */ + __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */ + __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */ + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */ + __IM uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */ + + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ + __IM uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */ + __IM uint32_t SCANFIFOCOUNT; /**< Scan FIFO Count Register */ + __IOM uint32_t SINGLEFIFOCLEAR; /**< Single FIFO Clear Register */ + __IOM uint32_t SCANFIFOCLEAR; /**< Scan FIFO Clear Register */ + __IOM uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */ +} ADC_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_ADC + * @{ + * @defgroup EFM32GG11B_ADC_BitFields ADC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for ADC CTRL */ +#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */ +#define _ADC_CTRL_MASK 0xFF7F7FDFUL /**< Mask for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC 0x00000002UL /**< Mode KEEPINSLOWACC for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 0) /**< Shifted mode KEEPINSTANDBY for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPINSLOWACC (_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC << 0) /**< Shifted mode KEEPINSLOWACC for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_SINGLEDMAWU (0x1UL << 2) /**< SINGLEFIFO DMA Wakeup */ +#define _ADC_CTRL_SINGLEDMAWU_SHIFT 2 /**< Shift value for ADC_SINGLEDMAWU */ +#define _ADC_CTRL_SINGLEDMAWU_MASK 0x4UL /**< Bit mask for ADC_SINGLEDMAWU */ +#define _ADC_CTRL_SINGLEDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SINGLEDMAWU_DEFAULT (_ADC_CTRL_SINGLEDMAWU_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SCANDMAWU (0x1UL << 3) /**< SCANFIFO DMA Wakeup */ +#define _ADC_CTRL_SCANDMAWU_SHIFT 3 /**< Shift value for ADC_SCANDMAWU */ +#define _ADC_CTRL_SCANDMAWU_MASK 0x8UL /**< Bit mask for ADC_SCANDMAWU */ +#define _ADC_CTRL_SCANDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SCANDMAWU_DEFAULT (_ADC_CTRL_SCANDMAWU_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TAILGATE (0x1UL << 4) /**< Conversion Tailgating */ +#define _ADC_CTRL_TAILGATE_SHIFT 4 /**< Shift value for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK Enable Mode When ADCCLKMODE=1 */ +#define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */ +#define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */ +#define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_ASYNCCLKEN_ASNEEDED 0x00000000UL /**< Mode ASNEEDED for ADC_CTRL */ +#define _ADC_CTRL_ASYNCCLKEN_ALWAYSON 0x00000001UL /**< Mode ALWAYSON for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_DEFAULT (_ADC_CTRL_ASYNCCLKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_ASNEEDED (_ADC_CTRL_ASYNCCLKEN_ASNEEDED << 6) /**< Shifted mode ASNEEDED for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_ALWAYSON (_ADC_CTRL_ASYNCCLKEN_ALWAYSON << 6) /**< Shifted mode ALWAYSON for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE (0x1UL << 7) /**< ADC Clock Mode */ +#define _ADC_CTRL_ADCCLKMODE_SHIFT 7 /**< Shift value for ADC_ADCCLKMODE */ +#define _ADC_CTRL_ADCCLKMODE_MASK 0x80UL /**< Bit mask for ADC_ADCCLKMODE */ +#define _ADC_CTRL_ADCCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_ADCCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for ADC_CTRL */ +#define _ADC_CTRL_ADCCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_DEFAULT (_ADC_CTRL_ADCCLKMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_SYNC (_ADC_CTRL_ADCCLKMODE_SYNC << 7) /**< Shifted mode SYNC for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_ASYNC (_ADC_CTRL_ADCCLKMODE_ASYNC << 7) /**< Shifted mode ASYNC for ADC_CTRL */ +#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */ +#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */ +#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */ +#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */ +#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */ +#define ADC_CTRL_DBGHALT (0x1UL << 28) /**< Debug Mode Halt Enable */ +#define _ADC_CTRL_DBGHALT_SHIFT 28 /**< Shift value for ADC_DBGHALT */ +#define _ADC_CTRL_DBGHALT_MASK 0x10000000UL /**< Bit mask for ADC_DBGHALT */ +#define _ADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_DBGHALT_DEFAULT (_ADC_CTRL_DBGHALT_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE (0x1UL << 29) /**< Channel Connect */ +#define _ADC_CTRL_CHCONMODE_SHIFT 29 /**< Shift value for ADC_CHCONMODE */ +#define _ADC_CTRL_CHCONMODE_MASK 0x20000000UL /**< Bit mask for ADC_CHCONMODE */ +#define _ADC_CTRL_CHCONMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_CHCONMODE_MAXSETTLE 0x00000000UL /**< Mode MAXSETTLE for ADC_CTRL */ +#define _ADC_CTRL_CHCONMODE_MAXRESP 0x00000001UL /**< Mode MAXRESP for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_DEFAULT (_ADC_CTRL_CHCONMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_MAXSETTLE (_ADC_CTRL_CHCONMODE_MAXSETTLE << 29) /**< Shifted mode MAXSETTLE for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_MAXRESP (_ADC_CTRL_CHCONMODE_MAXRESP << 29) /**< Shifted mode MAXRESP for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_SHIFT 30 /**< Shift value for ADC_CHCONREFWARMIDLE */ +#define _ADC_CTRL_CHCONREFWARMIDLE_MASK 0xC0000000UL /**< Bit mask for ADC_CHCONREFWARMIDLE */ +#define _ADC_CTRL_CHCONREFWARMIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN 0x00000000UL /**< Mode PREFSCAN for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE 0x00000001UL /**< Mode PREFSINGLE for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV 0x00000002UL /**< Mode KEEPPREV for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_DEFAULT (_ADC_CTRL_CHCONREFWARMIDLE_DEFAULT << 30) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN (_ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN << 30) /**< Shifted mode PREFSCAN for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE (_ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE << 30) /**< Shifted mode PREFSINGLE for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV (_ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV << 30) /**< Shifted mode KEEPPREV for ADC_CTRL */ + +/* Bit fields for ADC CMD */ +#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */ +#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */ +#define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Channel Conversion Start */ +#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Channel Conversion Stop */ +#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */ +#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */ +#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */ + +/* Bit fields for ADC STATUS */ +#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */ +#define _ADC_STATUS_MASK 0x00031F07UL /**< Mask for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Channel Conversion Active */ +#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */ +#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANPENDING (0x1UL << 2) /**< Scan Conversion Pending */ +#define _ADC_STATUS_SCANPENDING_SHIFT 2 /**< Shift value for ADC_SCANPENDING */ +#define _ADC_STATUS_SCANPENDING_MASK 0x4UL /**< Bit mask for ADC_SCANPENDING */ +#define _ADC_STATUS_SCANPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANPENDING_DEFAULT (_ADC_STATUS_SCANPENDING_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Channel Reference Warmed Up */ +#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */ +#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_SHIFT 10 /**< Shift value for ADC_PROGERR */ +#define _ADC_STATUS_PROGERR_MASK 0xC00UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_STATUS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_BUSCONF 0x00000001UL /**< Mode BUSCONF for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_NEGSELCONF 0x00000002UL /**< Mode NEGSELCONF for ADC_STATUS */ +#define ADC_STATUS_PROGERR_DEFAULT (_ADC_STATUS_PROGERR_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_PROGERR_BUSCONF (_ADC_STATUS_PROGERR_BUSCONF << 10) /**< Shifted mode BUSCONF for ADC_STATUS */ +#define ADC_STATUS_PROGERR_NEGSELCONF (_ADC_STATUS_PROGERR_NEGSELCONF << 10) /**< Shifted mode NEGSELCONF for ADC_STATUS */ +#define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */ +#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */ +#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */ +#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Channel Data Valid */ +#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */ +#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */ + +/* Bit fields for ADC SINGLECTRL */ +#define _ADC_SINGLECTRL_RESETVALUE 0x00FFFF00UL /**< Default value for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_MASK 0xAFFFFFFFUL /**< Mask for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Channel Repetitive Mode */ +#define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ +#define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ +#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Channel Differential Mode */ +#define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Channel Result Adjustment */ +#define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ +#define _ADC_SINGLECTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ +#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ +#define _ADC_SINGLECTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ +#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_5V (_ADC_SINGLECTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_CONF (_ADC_SINGLECTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SHIFT 8 /**< Shift value for ADC_POSSEL */ +#define _ADC_SINGLECTRL_POSSEL_MASK 0xFF00UL /**< Bit mask for ADC_POSSEL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_BUVDD 0x000000E1UL /**< Mode BUVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DVDD 0x000000E2UL /**< Mode DVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_PAVDD 0x000000E3UL /**< Mode PAVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DECOUPLE 0x000000E4UL /**< Mode DECOUPLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_IOVDD 0x000000E5UL /**< Mode IOVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_IOVDD1 0x000000E6UL /**< Mode IOVDD1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_OPA2 0x000000F2UL /**< Mode OPA2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_R5VOUT 0x000000F5UL /**< Mode R5VOUT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SUBLSB 0x000000F9UL /**< Mode SUBLSB for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_OPA3 0x000000FAUL /**< Mode OPA3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH0 (_ADC_SINGLECTRL_POSSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH1 (_ADC_SINGLECTRL_POSSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH2 (_ADC_SINGLECTRL_POSSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH3 (_ADC_SINGLECTRL_POSSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH4 (_ADC_SINGLECTRL_POSSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH5 (_ADC_SINGLECTRL_POSSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH6 (_ADC_SINGLECTRL_POSSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH7 (_ADC_SINGLECTRL_POSSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH8 (_ADC_SINGLECTRL_POSSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH9 (_ADC_SINGLECTRL_POSSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH10 (_ADC_SINGLECTRL_POSSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH11 (_ADC_SINGLECTRL_POSSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH12 (_ADC_SINGLECTRL_POSSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH13 (_ADC_SINGLECTRL_POSSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH14 (_ADC_SINGLECTRL_POSSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH15 (_ADC_SINGLECTRL_POSSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH0 (_ADC_SINGLECTRL_POSSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH1 (_ADC_SINGLECTRL_POSSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH2 (_ADC_SINGLECTRL_POSSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH3 (_ADC_SINGLECTRL_POSSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH4 (_ADC_SINGLECTRL_POSSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH5 (_ADC_SINGLECTRL_POSSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH6 (_ADC_SINGLECTRL_POSSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH7 (_ADC_SINGLECTRL_POSSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH8 (_ADC_SINGLECTRL_POSSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH9 (_ADC_SINGLECTRL_POSSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH10 (_ADC_SINGLECTRL_POSSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH11 (_ADC_SINGLECTRL_POSSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH12 (_ADC_SINGLECTRL_POSSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH13 (_ADC_SINGLECTRL_POSSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH14 (_ADC_SINGLECTRL_POSSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH15 (_ADC_SINGLECTRL_POSSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH0 (_ADC_SINGLECTRL_POSSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH1 (_ADC_SINGLECTRL_POSSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH2 (_ADC_SINGLECTRL_POSSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH3 (_ADC_SINGLECTRL_POSSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH4 (_ADC_SINGLECTRL_POSSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH5 (_ADC_SINGLECTRL_POSSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH6 (_ADC_SINGLECTRL_POSSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH7 (_ADC_SINGLECTRL_POSSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH8 (_ADC_SINGLECTRL_POSSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH9 (_ADC_SINGLECTRL_POSSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH10 (_ADC_SINGLECTRL_POSSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH11 (_ADC_SINGLECTRL_POSSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH12 (_ADC_SINGLECTRL_POSSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH13 (_ADC_SINGLECTRL_POSSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH14 (_ADC_SINGLECTRL_POSSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH15 (_ADC_SINGLECTRL_POSSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH16 (_ADC_SINGLECTRL_POSSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH17 (_ADC_SINGLECTRL_POSSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH18 (_ADC_SINGLECTRL_POSSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH19 (_ADC_SINGLECTRL_POSSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH20 (_ADC_SINGLECTRL_POSSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH21 (_ADC_SINGLECTRL_POSSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH22 (_ADC_SINGLECTRL_POSSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH23 (_ADC_SINGLECTRL_POSSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH24 (_ADC_SINGLECTRL_POSSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH25 (_ADC_SINGLECTRL_POSSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH26 (_ADC_SINGLECTRL_POSSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH27 (_ADC_SINGLECTRL_POSSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH28 (_ADC_SINGLECTRL_POSSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH29 (_ADC_SINGLECTRL_POSSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH30 (_ADC_SINGLECTRL_POSSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH31 (_ADC_SINGLECTRL_POSSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH0 (_ADC_SINGLECTRL_POSSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH1 (_ADC_SINGLECTRL_POSSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH2 (_ADC_SINGLECTRL_POSSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH3 (_ADC_SINGLECTRL_POSSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH4 (_ADC_SINGLECTRL_POSSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH5 (_ADC_SINGLECTRL_POSSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH6 (_ADC_SINGLECTRL_POSSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH7 (_ADC_SINGLECTRL_POSSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH8 (_ADC_SINGLECTRL_POSSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH9 (_ADC_SINGLECTRL_POSSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH10 (_ADC_SINGLECTRL_POSSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH11 (_ADC_SINGLECTRL_POSSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH12 (_ADC_SINGLECTRL_POSSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH13 (_ADC_SINGLECTRL_POSSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH14 (_ADC_SINGLECTRL_POSSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH15 (_ADC_SINGLECTRL_POSSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH16 (_ADC_SINGLECTRL_POSSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH17 (_ADC_SINGLECTRL_POSSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH18 (_ADC_SINGLECTRL_POSSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH19 (_ADC_SINGLECTRL_POSSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH20 (_ADC_SINGLECTRL_POSSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH21 (_ADC_SINGLECTRL_POSSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH22 (_ADC_SINGLECTRL_POSSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH23 (_ADC_SINGLECTRL_POSSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH24 (_ADC_SINGLECTRL_POSSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH25 (_ADC_SINGLECTRL_POSSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH26 (_ADC_SINGLECTRL_POSSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH27 (_ADC_SINGLECTRL_POSSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH28 (_ADC_SINGLECTRL_POSSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH29 (_ADC_SINGLECTRL_POSSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH30 (_ADC_SINGLECTRL_POSSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH31 (_ADC_SINGLECTRL_POSSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH0 (_ADC_SINGLECTRL_POSSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH1 (_ADC_SINGLECTRL_POSSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH2 (_ADC_SINGLECTRL_POSSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH3 (_ADC_SINGLECTRL_POSSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH4 (_ADC_SINGLECTRL_POSSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH5 (_ADC_SINGLECTRL_POSSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH6 (_ADC_SINGLECTRL_POSSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH7 (_ADC_SINGLECTRL_POSSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH8 (_ADC_SINGLECTRL_POSSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH9 (_ADC_SINGLECTRL_POSSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH10 (_ADC_SINGLECTRL_POSSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH11 (_ADC_SINGLECTRL_POSSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH12 (_ADC_SINGLECTRL_POSSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH13 (_ADC_SINGLECTRL_POSSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH14 (_ADC_SINGLECTRL_POSSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH15 (_ADC_SINGLECTRL_POSSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH16 (_ADC_SINGLECTRL_POSSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH17 (_ADC_SINGLECTRL_POSSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH18 (_ADC_SINGLECTRL_POSSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH19 (_ADC_SINGLECTRL_POSSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH20 (_ADC_SINGLECTRL_POSSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH21 (_ADC_SINGLECTRL_POSSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH22 (_ADC_SINGLECTRL_POSSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH23 (_ADC_SINGLECTRL_POSSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH24 (_ADC_SINGLECTRL_POSSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH25 (_ADC_SINGLECTRL_POSSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH26 (_ADC_SINGLECTRL_POSSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH27 (_ADC_SINGLECTRL_POSSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH28 (_ADC_SINGLECTRL_POSSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH29 (_ADC_SINGLECTRL_POSSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH30 (_ADC_SINGLECTRL_POSSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH31 (_ADC_SINGLECTRL_POSSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH0 (_ADC_SINGLECTRL_POSSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH1 (_ADC_SINGLECTRL_POSSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH2 (_ADC_SINGLECTRL_POSSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH3 (_ADC_SINGLECTRL_POSSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH4 (_ADC_SINGLECTRL_POSSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH5 (_ADC_SINGLECTRL_POSSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH6 (_ADC_SINGLECTRL_POSSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH7 (_ADC_SINGLECTRL_POSSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH8 (_ADC_SINGLECTRL_POSSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH9 (_ADC_SINGLECTRL_POSSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH10 (_ADC_SINGLECTRL_POSSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH11 (_ADC_SINGLECTRL_POSSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH12 (_ADC_SINGLECTRL_POSSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH13 (_ADC_SINGLECTRL_POSSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH14 (_ADC_SINGLECTRL_POSSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH15 (_ADC_SINGLECTRL_POSSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH16 (_ADC_SINGLECTRL_POSSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH17 (_ADC_SINGLECTRL_POSSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH18 (_ADC_SINGLECTRL_POSSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH19 (_ADC_SINGLECTRL_POSSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH20 (_ADC_SINGLECTRL_POSSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH21 (_ADC_SINGLECTRL_POSSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH22 (_ADC_SINGLECTRL_POSSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH23 (_ADC_SINGLECTRL_POSSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH24 (_ADC_SINGLECTRL_POSSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH25 (_ADC_SINGLECTRL_POSSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH26 (_ADC_SINGLECTRL_POSSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH27 (_ADC_SINGLECTRL_POSSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH28 (_ADC_SINGLECTRL_POSSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH29 (_ADC_SINGLECTRL_POSSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_BUVDD (_ADC_SINGLECTRL_POSSEL_BUVDD << 8) /**< Shifted mode BUVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DVDD (_ADC_SINGLECTRL_POSSEL_DVDD << 8) /**< Shifted mode DVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_PAVDD (_ADC_SINGLECTRL_POSSEL_PAVDD << 8) /**< Shifted mode PAVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DECOUPLE (_ADC_SINGLECTRL_POSSEL_DECOUPLE << 8) /**< Shifted mode DECOUPLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_IOVDD (_ADC_SINGLECTRL_POSSEL_IOVDD << 8) /**< Shifted mode IOVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_IOVDD1 (_ADC_SINGLECTRL_POSSEL_IOVDD1 << 8) /**< Shifted mode IOVDD1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_OPA2 (_ADC_SINGLECTRL_POSSEL_OPA2 << 8) /**< Shifted mode OPA2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_R5VOUT (_ADC_SINGLECTRL_POSSEL_R5VOUT << 8) /**< Shifted mode R5VOUT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SUBLSB (_ADC_SINGLECTRL_POSSEL_SUBLSB << 8) /**< Shifted mode SUBLSB for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_OPA3 (_ADC_SINGLECTRL_POSSEL_OPA3 << 8) /**< Shifted mode OPA3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DEFAULT (_ADC_SINGLECTRL_POSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VSS (_ADC_SINGLECTRL_POSSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_SHIFT 16 /**< Shift value for ADC_NEGSEL */ +#define _ADC_SINGLECTRL_NEGSEL_MASK 0xFF0000UL /**< Bit mask for ADC_NEGSEL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_TESTN 0x000000F5UL /**< Mode TESTN for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH0 << 16) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH1 << 16) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH2 << 16) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH3 << 16) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH4 << 16) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH5 << 16) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH6 << 16) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH7 << 16) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH8 << 16) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH9 << 16) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH10 << 16) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH11 << 16) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH12 << 16) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH13 << 16) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH14 << 16) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH15 << 16) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH0 << 16) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH1 << 16) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH2 << 16) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH3 << 16) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH4 << 16) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH5 << 16) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH6 << 16) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH7 << 16) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH8 << 16) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH9 << 16) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH10 << 16) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH11 << 16) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH12 << 16) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH13 << 16) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH14 << 16) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH15 << 16) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH1 << 16) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH3 << 16) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH5 << 16) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH7 << 16) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH9 << 16) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH11 << 16) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH13 << 16) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH15 << 16) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH17 << 16) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH19 << 16) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH21 << 16) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH23 << 16) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH25 << 16) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH27 << 16) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH29 << 16) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH31 << 16) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH0 << 16) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH2 << 16) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH4 << 16) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH6 << 16) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH8 << 16) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH10 << 16) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH12 << 16) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH14 << 16) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH16 << 16) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH18 << 16) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH20 << 16) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH22 << 16) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH24 << 16) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH26 << 16) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH28 << 16) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH30 << 16) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH1 << 16) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH3 << 16) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH5 << 16) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH7 << 16) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH9 << 16) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH11 << 16) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH13 << 16) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH15 << 16) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH17 << 16) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH19 << 16) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH21 << 16) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH23 << 16) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH25 << 16) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH27 << 16) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH29 << 16) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH31 << 16) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_TESTN (_ADC_SINGLECTRL_NEGSEL_TESTN << 16) /**< Shifted mode TESTN for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_DEFAULT (_ADC_SINGLECTRL_NEGSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_VSS (_ADC_SINGLECTRL_NEGSEL_VSS << 16) /**< Shifted mode VSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ +#define _ADC_SINGLECTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ +#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_3CYCLES (_ADC_SINGLECTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN (0x1UL << 29) /**< Single Channel PRS Trigger Enable */ +#define _ADC_SINGLECTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Single Channel */ +#define _ADC_SINGLECTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ +#define _ADC_SINGLECTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ +#define _ADC_SINGLECTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_CMPEN_DEFAULT (_ADC_SINGLECTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ + +/* Bit fields for ADC SINGLECTRLX */ +#define _ADC_SINGLECTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_MASK 0xEFFF7FFFUL /**< Mask for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ +#define _ADC_SINGLECTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ +#define _ADC_SINGLECTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_DEFAULT (_ADC_SINGLECTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VBGR (_ADC_SINGLECTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VDDXWATT (_ADC_SINGLECTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFP (_ADC_SINGLECTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VENTROPY (_ADC_SINGLECTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */ +#define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ +#define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ +#define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATTFIX_DEFAULT (_ADC_SINGLECTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ +#define _ADC_SINGLECTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ +#define _ADC_SINGLECTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATT_DEFAULT (_ADC_SINGLECTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ +#define _ADC_SINGLECTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ +#define _ADC_SINGLECTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VINATT_DEFAULT (_ADC_SINGLECTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ +#define _ADC_SINGLECTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ +#define _ADC_SINGLECTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_DVL_DEFAULT (_ADC_SINGLECTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT (0x1UL << 14) /**< Single Channel FIFO Overflow Action */ +#define _ADC_SINGLECTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ +#define _ADC_SINGLECTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ +#define _ADC_SINGLECTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_DEFAULT (_ADC_SINGLECTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_DISCARD (_ADC_SINGLECTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE (_ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE (0x1UL << 16) /**< Single Channel PRS Trigger Mode */ +#define _ADC_SINGLECTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ +#define _ADC_SINGLECTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ +#define _ADC_SINGLECTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_DEFAULT (_ADC_SINGLECTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_PULSED (_ADC_SINGLECTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_TIMED (_ADC_SINGLECTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ +#define _ADC_SINGLECTRLX_PRSSEL_MASK 0x3E0000UL /**< Bit mask for ADC_PRSSEL */ +#define _ADC_SINGLECTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_DEFAULT (_ADC_SINGLECTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH0 (_ADC_SINGLECTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH1 (_ADC_SINGLECTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH2 (_ADC_SINGLECTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH3 (_ADC_SINGLECTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH4 (_ADC_SINGLECTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH5 (_ADC_SINGLECTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH6 (_ADC_SINGLECTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH7 (_ADC_SINGLECTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH8 (_ADC_SINGLECTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH9 (_ADC_SINGLECTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH10 (_ADC_SINGLECTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH11 (_ADC_SINGLECTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH12 (_ADC_SINGLECTRLX_PRSSEL_PRSCH12 << 17) /**< Shifted mode PRSCH12 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH13 (_ADC_SINGLECTRLX_PRSSEL_PRSCH13 << 17) /**< Shifted mode PRSCH13 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH14 (_ADC_SINGLECTRLX_PRSSEL_PRSCH14 << 17) /**< Shifted mode PRSCH14 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH15 (_ADC_SINGLECTRLX_PRSSEL_PRSCH15 << 17) /**< Shifted mode PRSCH15 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH16 (_ADC_SINGLECTRLX_PRSSEL_PRSCH16 << 17) /**< Shifted mode PRSCH16 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH17 (_ADC_SINGLECTRLX_PRSSEL_PRSCH17 << 17) /**< Shifted mode PRSCH17 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH18 (_ADC_SINGLECTRLX_PRSSEL_PRSCH18 << 17) /**< Shifted mode PRSCH18 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH19 (_ADC_SINGLECTRLX_PRSSEL_PRSCH19 << 17) /**< Shifted mode PRSCH19 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH20 (_ADC_SINGLECTRLX_PRSSEL_PRSCH20 << 17) /**< Shifted mode PRSCH20 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH21 (_ADC_SINGLECTRLX_PRSSEL_PRSCH21 << 17) /**< Shifted mode PRSCH21 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH22 (_ADC_SINGLECTRLX_PRSSEL_PRSCH22 << 17) /**< Shifted mode PRSCH22 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH23 (_ADC_SINGLECTRLX_PRSSEL_PRSCH23 << 17) /**< Shifted mode PRSCH23 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ +#define _ADC_SINGLECTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ +#define _ADC_SINGLECTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_DEFAULT (_ADC_SINGLECTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_NODELAY (_ADC_SINGLECTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_4CYCLES (_ADC_SINGLECTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_8CYCLES (_ADC_SINGLECTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_16CYCLES (_ADC_SINGLECTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_32CYCLES (_ADC_SINGLECTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_64CYCLES (_ADC_SINGLECTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_128CYCLES (_ADC_SINGLECTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_256CYCLES (_ADC_SINGLECTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SINGLECTRLX */ + +/* Bit fields for ADC SCANCTRL */ +#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_MASK 0xAF0000FFUL /**< Mask for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */ +#define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ +#define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ +#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */ +#define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */ +#define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ +#define _ADC_SCANCTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ +#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ +#define _ADC_SCANCTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ +#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_5V (_ADC_SCANCTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_CONF (_ADC_SCANCTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ +#define _ADC_SCANCTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ +#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_3CYCLES (_ADC_SCANCTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN (0x1UL << 29) /**< Scan Sequence PRS Trigger Enable */ +#define _ADC_SCANCTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Scan */ +#define _ADC_SCANCTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ +#define _ADC_SCANCTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ +#define _ADC_SCANCTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_CMPEN_DEFAULT (_ADC_SCANCTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ + +/* Bit fields for ADC SCANCTRLX */ +#define _ADC_SCANCTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_MASK 0xEFFF7FFFUL /**< Mask for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ +#define _ADC_SCANCTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ +#define _ADC_SCANCTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_DEFAULT (_ADC_SCANCTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VBGR (_ADC_SCANCTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VDDXWATT (_ADC_SCANCTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPWATT (_ADC_SCANCTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFP (_ADC_SCANCTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */ +#define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ +#define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ +#define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATTFIX_DEFAULT (_ADC_SCANCTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ +#define _ADC_SCANCTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ +#define _ADC_SCANCTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATT_DEFAULT (_ADC_SCANCTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ +#define _ADC_SCANCTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ +#define _ADC_SCANCTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VINATT_DEFAULT (_ADC_SCANCTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ +#define _ADC_SCANCTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ +#define _ADC_SCANCTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_DVL_DEFAULT (_ADC_SCANCTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT (0x1UL << 14) /**< Scan FIFO Overflow Action */ +#define _ADC_SCANCTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ +#define _ADC_SCANCTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ +#define _ADC_SCANCTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_DEFAULT (_ADC_SCANCTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_DISCARD (_ADC_SCANCTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_OVERWRITE (_ADC_SCANCTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE (0x1UL << 16) /**< Scan PRS Trigger Mode */ +#define _ADC_SCANCTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ +#define _ADC_SCANCTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ +#define _ADC_SCANCTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_DEFAULT (_ADC_SCANCTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_PULSED (_ADC_SCANCTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_TIMED (_ADC_SCANCTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ +#define _ADC_SCANCTRLX_PRSSEL_MASK 0x3E0000UL /**< Bit mask for ADC_PRSSEL */ +#define _ADC_SCANCTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_DEFAULT (_ADC_SCANCTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH0 (_ADC_SCANCTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH1 (_ADC_SCANCTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH2 (_ADC_SCANCTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH3 (_ADC_SCANCTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH4 (_ADC_SCANCTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH5 (_ADC_SCANCTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH6 (_ADC_SCANCTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH7 (_ADC_SCANCTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH8 (_ADC_SCANCTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH9 (_ADC_SCANCTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH10 (_ADC_SCANCTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH11 (_ADC_SCANCTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH12 (_ADC_SCANCTRLX_PRSSEL_PRSCH12 << 17) /**< Shifted mode PRSCH12 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH13 (_ADC_SCANCTRLX_PRSSEL_PRSCH13 << 17) /**< Shifted mode PRSCH13 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH14 (_ADC_SCANCTRLX_PRSSEL_PRSCH14 << 17) /**< Shifted mode PRSCH14 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH15 (_ADC_SCANCTRLX_PRSSEL_PRSCH15 << 17) /**< Shifted mode PRSCH15 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH16 (_ADC_SCANCTRLX_PRSSEL_PRSCH16 << 17) /**< Shifted mode PRSCH16 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH17 (_ADC_SCANCTRLX_PRSSEL_PRSCH17 << 17) /**< Shifted mode PRSCH17 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH18 (_ADC_SCANCTRLX_PRSSEL_PRSCH18 << 17) /**< Shifted mode PRSCH18 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH19 (_ADC_SCANCTRLX_PRSSEL_PRSCH19 << 17) /**< Shifted mode PRSCH19 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH20 (_ADC_SCANCTRLX_PRSSEL_PRSCH20 << 17) /**< Shifted mode PRSCH20 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH21 (_ADC_SCANCTRLX_PRSSEL_PRSCH21 << 17) /**< Shifted mode PRSCH21 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH22 (_ADC_SCANCTRLX_PRSSEL_PRSCH22 << 17) /**< Shifted mode PRSCH22 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH23 (_ADC_SCANCTRLX_PRSSEL_PRSCH23 << 17) /**< Shifted mode PRSCH23 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ +#define _ADC_SCANCTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ +#define _ADC_SCANCTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_DEFAULT (_ADC_SCANCTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_NODELAY (_ADC_SCANCTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_4CYCLES (_ADC_SCANCTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_8CYCLES (_ADC_SCANCTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_16CYCLES (_ADC_SCANCTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_32CYCLES (_ADC_SCANCTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_64CYCLES (_ADC_SCANCTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_128CYCLES (_ADC_SCANCTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_256CYCLES (_ADC_SCANCTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SCANCTRLX */ + +/* Bit fields for ADC SCANMASK */ +#define _ADC_SCANMASK_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANMASK */ +#define _ADC_SCANMASK_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */ +#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */ +#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */ + +/* Bit fields for ADC SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_MASK 0x1F1F1F1FUL /**< Mask for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT 0 /**< Shift value for ADC_INPUT0TO7SEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_MASK 0x1FUL /**< Bit mask for ADC_INPUT0TO7SEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 << 0) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 << 0) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 << 0) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 << 0) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 << 0) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 << 0) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 << 0) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 << 0) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 << 0) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 << 0) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT 8 /**< Shift value for ADC_INPUT8TO15SEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_MASK 0x1F00UL /**< Bit mask for ADC_INPUT8TO15SEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 << 8) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 << 8) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 << 8) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 << 8) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 << 8) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 << 8) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 << 8) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 << 8) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 << 8) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 << 8) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT 16 /**< Shift value for ADC_INPUT16TO23SEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_MASK 0x1F0000UL /**< Bit mask for ADC_INPUT16TO23SEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 << 16) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 << 16) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 << 16) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 << 16) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 << 16) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 << 16) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 << 16) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 << 16) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 << 16) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 << 16) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT 24 /**< Shift value for ADC_INPUT24TO31SEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_MASK 0x1F000000UL /**< Bit mask for ADC_INPUT24TO31SEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 << 24) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 << 24) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 << 24) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 << 24) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 << 24) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 << 24) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 << 24) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 << 24) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 << 24) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 << 24) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ + +/* Bit fields for ADC SCANNEGSEL */ +#define _ADC_SCANNEGSEL_RESETVALUE 0x000039E4UL /**< Default value for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_MASK 0x0000FFFFUL /**< Mask for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT 0 /**< Shift value for ADC_INPUT0NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK 0x3UL /**< Bit mask for ADC_INPUT0NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT 2 /**< Shift value for ADC_INPUT2NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK 0xCUL /**< Bit mask for ADC_INPUT2NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 << 2) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 << 2) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 << 2) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 << 2) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT 4 /**< Shift value for ADC_INPUT4NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK 0x30UL /**< Bit mask for ADC_INPUT4NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 << 4) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 << 4) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 << 4) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 << 4) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT 6 /**< Shift value for ADC_INPUT6NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK 0xC0UL /**< Bit mask for ADC_INPUT6NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 << 6) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 << 6) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 << 6) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 << 6) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT 8 /**< Shift value for ADC_INPUT9NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK 0x300UL /**< Bit mask for ADC_INPUT9NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 << 8) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 << 8) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 << 8) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 << 8) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT 10 /**< Shift value for ADC_INPUT11NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK 0xC00UL /**< Bit mask for ADC_INPUT11NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 << 10) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 << 10) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 << 10) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 << 10) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT 12 /**< Shift value for ADC_INPUT13NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK 0x3000UL /**< Bit mask for ADC_INPUT13NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 << 12) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 << 12) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 << 12) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 << 12) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT 14 /**< Shift value for ADC_INPUT15NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK 0xC000UL /**< Bit mask for ADC_INPUT15NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 << 14) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 << 14) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 << 14) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 << 14) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ + +/* Bit fields for ADC CMPTHR */ +#define _ADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for ADC_CMPTHR */ +#define _ADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for ADC_CMPTHR */ +#define _ADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for ADC_ADLT */ +#define _ADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for ADC_ADLT */ +#define _ADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ +#define ADC_CMPTHR_ADLT_DEFAULT (_ADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMPTHR */ +#define _ADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for ADC_ADGT */ +#define _ADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for ADC_ADGT */ +#define _ADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ +#define ADC_CMPTHR_ADGT_DEFAULT (_ADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CMPTHR */ + +/* Bit fields for ADC BIASPROG */ +#define _ADC_BIASPROG_RESETVALUE 0x00000000UL /**< Default value for ADC_BIASPROG */ +#define _ADC_BIASPROG_MASK 0x0001100FUL /**< Mask for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SHIFT 0 /**< Shift value for ADC_ADCBIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_MASK 0xFUL /**< Bit mask for ADC_ADCBIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE2 0x00000004UL /**< Mode SCALE2 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE4 0x00000008UL /**< Mode SCALE4 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE8 0x0000000CUL /**< Mode SCALE8 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE16 0x0000000EUL /**< Mode SCALE16 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE32 0x0000000FUL /**< Mode SCALE32 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_DEFAULT (_ADC_BIASPROG_ADCBIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_NORMAL (_ADC_BIASPROG_ADCBIASPROG_NORMAL << 0) /**< Shifted mode NORMAL for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE2 (_ADC_BIASPROG_ADCBIASPROG_SCALE2 << 0) /**< Shifted mode SCALE2 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE4 (_ADC_BIASPROG_ADCBIASPROG_SCALE4 << 0) /**< Shifted mode SCALE4 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */ +#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF Flag */ +#define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */ +#define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */ +#define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy Setting for the System Bias During ADC Operation */ +#define _ADC_BIASPROG_GPBIASACC_SHIFT 16 /**< Shift value for ADC_GPBIASACC */ +#define _ADC_BIASPROG_GPBIASACC_MASK 0x10000UL /**< Bit mask for ADC_GPBIASACC */ +#define _ADC_BIASPROG_GPBIASACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_GPBIASACC_HIGHACC 0x00000000UL /**< Mode HIGHACC for ADC_BIASPROG */ +#define _ADC_BIASPROG_GPBIASACC_LOWACC 0x00000001UL /**< Mode LOWACC for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_DEFAULT (_ADC_BIASPROG_GPBIASACC_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_HIGHACC (_ADC_BIASPROG_GPBIASACC_HIGHACC << 16) /**< Shifted mode HIGHACC for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_LOWACC (_ADC_BIASPROG_GPBIASACC_LOWACC << 16) /**< Shifted mode LOWACC for ADC_BIASPROG */ + +/* Bit fields for ADC CAL */ +#define _ADC_CAL_RESETVALUE 0x40784078UL /**< Default value for ADC_CAL */ +#define _ADC_CAL_MASK 0xFFFFFFFFUL /**< Mask for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_MASK 0xFUL /**< Bit mask for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSETINV_SHIFT 4 /**< Shift value for ADC_SINGLEOFFSETINV */ +#define _ADC_CAL_SINGLEOFFSETINV_MASK 0xF0UL /**< Bit mask for ADC_SINGLEOFFSETINV */ +#define _ADC_CAL_SINGLEOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEOFFSETINV_DEFAULT (_ADC_CAL_SINGLEOFFSETINV_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */ +#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative Single-ended Offset Calibration is Enabled */ +#define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */ +#define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */ +#define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_OFFSETINVMODE_DEFAULT (_ADC_CAL_OFFSETINVMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_MASK 0xF0000UL /**< Bit mask for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSETINV_SHIFT 20 /**< Shift value for ADC_SCANOFFSETINV */ +#define _ADC_CAL_SCANOFFSETINV_MASK 0xF00000UL /**< Bit mask for ADC_SCANOFFSETINV */ +#define _ADC_CAL_SCANOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANOFFSETINV_DEFAULT (_ADC_CAL_SCANOFFSETINV_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */ +#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration Mode is Enabled */ +#define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */ +#define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */ +#define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_CALEN_DEFAULT (_ADC_CAL_CALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_CAL */ + +/* Bit fields for ADC IF */ +#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */ +#define _ADC_IF_MASK 0x3F030F03UL /**< Mask for ADC_IF */ +#define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */ +#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */ +#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single FIFO Overflow Interrupt Flag */ +#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF (0x1UL << 9) /**< Scan FIFO Overflow Interrupt Flag */ +#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEUF (0x1UL << 10) /**< Single FIFO Underflow Interrupt Flag */ +#define _ADC_IF_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IF_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IF_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEUF_DEFAULT (_ADC_IF_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANUF (0x1UL << 11) /**< Scan FIFO Underflow Interrupt Flag */ +#define _ADC_IF_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IF_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IF_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANUF_DEFAULT (_ADC_IF_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLECMP (0x1UL << 16) /**< Single Result Compare Match Interrupt Flag */ +#define _ADC_IF_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IF_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLECMP_DEFAULT (_ADC_IF_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANCMP (0x1UL << 17) /**< Scan Result Compare Match Interrupt Flag */ +#define _ADC_IF_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IF_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANCMP_DEFAULT (_ADC_IF_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_VREFOV (0x1UL << 24) /**< VREF Over Voltage Interrupt Flag */ +#define _ADC_IF_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IF_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IF_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_VREFOV_DEFAULT (_ADC_IF_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_PROGERR (0x1UL << 25) /**< Programming Error Interrupt Flag */ +#define _ADC_IF_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IF_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IF_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_PROGERR_DEFAULT (_ADC_IF_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANEXTPEND (0x1UL << 26) /**< External Scan Trigger Pending Flag */ +#define _ADC_IF_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IF_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IF_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANEXTPEND_DEFAULT (_ADC_IF_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANPEND (0x1UL << 27) /**< Scan Trigger Pending Flag */ +#define _ADC_IF_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IF_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IF_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANPEND_DEFAULT (_ADC_IF_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_PRSTIMEDERR (0x1UL << 28) /**< PRS Timed Mode Error Flag */ +#define _ADC_IF_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IF_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IF_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_PRSTIMEDERR_DEFAULT (_ADC_IF_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_EM23ERR (0x1UL << 29) /**< EM23 Entry Error Flag */ +#define _ADC_IF_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IF_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_EM23ERR_DEFAULT (_ADC_IF_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IF */ + +/* Bit fields for ADC IFS */ +#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */ +#define _ADC_IFS_MASK 0x3F030F00UL /**< Mask for ADC_IFS */ +#define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Set SINGLEOF Interrupt Flag */ +#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF (0x1UL << 9) /**< Set SCANOF Interrupt Flag */ +#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEUF (0x1UL << 10) /**< Set SINGLEUF Interrupt Flag */ +#define _ADC_IFS_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IFS_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IFS_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEUF_DEFAULT (_ADC_IFS_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANUF (0x1UL << 11) /**< Set SCANUF Interrupt Flag */ +#define _ADC_IFS_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IFS_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IFS_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANUF_DEFAULT (_ADC_IFS_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLECMP (0x1UL << 16) /**< Set SINGLECMP Interrupt Flag */ +#define _ADC_IFS_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IFS_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IFS_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLECMP_DEFAULT (_ADC_IFS_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANCMP (0x1UL << 17) /**< Set SCANCMP Interrupt Flag */ +#define _ADC_IFS_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IFS_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IFS_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANCMP_DEFAULT (_ADC_IFS_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_VREFOV (0x1UL << 24) /**< Set VREFOV Interrupt Flag */ +#define _ADC_IFS_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IFS_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IFS_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_VREFOV_DEFAULT (_ADC_IFS_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PROGERR (0x1UL << 25) /**< Set PROGERR Interrupt Flag */ +#define _ADC_IFS_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IFS_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IFS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PROGERR_DEFAULT (_ADC_IFS_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANEXTPEND (0x1UL << 26) /**< Set SCANEXTPEND Interrupt Flag */ +#define _ADC_IFS_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IFS_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IFS_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANEXTPEND_DEFAULT (_ADC_IFS_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANPEND (0x1UL << 27) /**< Set SCANPEND Interrupt Flag */ +#define _ADC_IFS_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IFS_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IFS_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANPEND_DEFAULT (_ADC_IFS_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PRSTIMEDERR (0x1UL << 28) /**< Set PRSTIMEDERR Interrupt Flag */ +#define _ADC_IFS_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IFS_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IFS_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PRSTIMEDERR_DEFAULT (_ADC_IFS_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_EM23ERR (0x1UL << 29) /**< Set EM23ERR Interrupt Flag */ +#define _ADC_IFS_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IFS_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_EM23ERR_DEFAULT (_ADC_IFS_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFS */ + +/* Bit fields for ADC IFC */ +#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */ +#define _ADC_IFC_MASK 0x3F030F00UL /**< Mask for ADC_IFC */ +#define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Clear SINGLEOF Interrupt Flag */ +#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF (0x1UL << 9) /**< Clear SCANOF Interrupt Flag */ +#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEUF (0x1UL << 10) /**< Clear SINGLEUF Interrupt Flag */ +#define _ADC_IFC_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IFC_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IFC_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEUF_DEFAULT (_ADC_IFC_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANUF (0x1UL << 11) /**< Clear SCANUF Interrupt Flag */ +#define _ADC_IFC_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IFC_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IFC_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANUF_DEFAULT (_ADC_IFC_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLECMP (0x1UL << 16) /**< Clear SINGLECMP Interrupt Flag */ +#define _ADC_IFC_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IFC_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IFC_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLECMP_DEFAULT (_ADC_IFC_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANCMP (0x1UL << 17) /**< Clear SCANCMP Interrupt Flag */ +#define _ADC_IFC_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IFC_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IFC_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANCMP_DEFAULT (_ADC_IFC_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_VREFOV (0x1UL << 24) /**< Clear VREFOV Interrupt Flag */ +#define _ADC_IFC_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IFC_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IFC_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_VREFOV_DEFAULT (_ADC_IFC_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PROGERR (0x1UL << 25) /**< Clear PROGERR Interrupt Flag */ +#define _ADC_IFC_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IFC_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IFC_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PROGERR_DEFAULT (_ADC_IFC_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANEXTPEND (0x1UL << 26) /**< Clear SCANEXTPEND Interrupt Flag */ +#define _ADC_IFC_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IFC_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IFC_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANEXTPEND_DEFAULT (_ADC_IFC_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANPEND (0x1UL << 27) /**< Clear SCANPEND Interrupt Flag */ +#define _ADC_IFC_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IFC_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IFC_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANPEND_DEFAULT (_ADC_IFC_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PRSTIMEDERR (0x1UL << 28) /**< Clear PRSTIMEDERR Interrupt Flag */ +#define _ADC_IFC_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IFC_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IFC_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PRSTIMEDERR_DEFAULT (_ADC_IFC_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_EM23ERR (0x1UL << 29) /**< Clear EM23ERR Interrupt Flag */ +#define _ADC_IFC_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IFC_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_EM23ERR_DEFAULT (_ADC_IFC_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFC */ + +/* Bit fields for ADC IEN */ +#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */ +#define _ADC_IEN_MASK 0x3F030F03UL /**< Mask for ADC_IEN */ +#define ADC_IEN_SINGLE (0x1UL << 0) /**< SINGLE Interrupt Enable */ +#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN (0x1UL << 1) /**< SCAN Interrupt Enable */ +#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF (0x1UL << 8) /**< SINGLEOF Interrupt Enable */ +#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF (0x1UL << 9) /**< SCANOF Interrupt Enable */ +#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEUF (0x1UL << 10) /**< SINGLEUF Interrupt Enable */ +#define _ADC_IEN_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IEN_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IEN_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEUF_DEFAULT (_ADC_IEN_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANUF (0x1UL << 11) /**< SCANUF Interrupt Enable */ +#define _ADC_IEN_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IEN_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IEN_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANUF_DEFAULT (_ADC_IEN_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLECMP (0x1UL << 16) /**< SINGLECMP Interrupt Enable */ +#define _ADC_IEN_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IEN_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLECMP_DEFAULT (_ADC_IEN_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANCMP (0x1UL << 17) /**< SCANCMP Interrupt Enable */ +#define _ADC_IEN_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IEN_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANCMP_DEFAULT (_ADC_IEN_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_VREFOV (0x1UL << 24) /**< VREFOV Interrupt Enable */ +#define _ADC_IEN_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IEN_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IEN_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_VREFOV_DEFAULT (_ADC_IEN_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PROGERR (0x1UL << 25) /**< PROGERR Interrupt Enable */ +#define _ADC_IEN_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IEN_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IEN_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PROGERR_DEFAULT (_ADC_IEN_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANEXTPEND (0x1UL << 26) /**< SCANEXTPEND Interrupt Enable */ +#define _ADC_IEN_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IEN_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IEN_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANEXTPEND_DEFAULT (_ADC_IEN_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANPEND (0x1UL << 27) /**< SCANPEND Interrupt Enable */ +#define _ADC_IEN_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IEN_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IEN_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANPEND_DEFAULT (_ADC_IEN_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PRSTIMEDERR (0x1UL << 28) /**< PRSTIMEDERR Interrupt Enable */ +#define _ADC_IEN_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IEN_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IEN_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PRSTIMEDERR_DEFAULT (_ADC_IEN_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_EM23ERR (0x1UL << 29) /**< EM23ERR Interrupt Enable */ +#define _ADC_IEN_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IEN_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_EM23ERR_DEFAULT (_ADC_IEN_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IEN */ + +/* Bit fields for ADC SINGLEDATA */ +#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */ +#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */ + +/* Bit fields for ADC SCANDATA */ +#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */ +#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */ +#define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */ +#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */ + +/* Bit fields for ADC SINGLEDATAP */ +#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */ +#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */ + +/* Bit fields for ADC SCANDATAP */ +#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */ +#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */ + +/* Bit fields for ADC SCANDATAX */ +#define _ADC_SCANDATAX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SCANDATAX_DATA_MASK 0xFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SCANDATAX_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ +#define ADC_SCANDATAX_DATA_DEFAULT (_ADC_SCANDATAX_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_SCANINPUTID_SHIFT 16 /**< Shift value for ADC_SCANINPUTID */ +#define _ADC_SCANDATAX_SCANINPUTID_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTID */ +#define _ADC_SCANDATAX_SCANINPUTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ +#define ADC_SCANDATAX_SCANINPUTID_DEFAULT (_ADC_SCANDATAX_SCANINPUTID_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ + +/* Bit fields for ADC SCANDATAXP */ +#define _ADC_SCANDATAXP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SCANDATAXP_DATAP_MASK 0xFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SCANDATAXP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ +#define ADC_SCANDATAXP_DATAP_DEFAULT (_ADC_SCANDATAXP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_SHIFT 16 /**< Shift value for ADC_SCANINPUTIDPEEK */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTIDPEEK */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ +#define ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT (_ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ + +/* Bit fields for ADC APORTREQ */ +#define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */ +#define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */ +#define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */ +#define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */ +#define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */ +#define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */ +#define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */ +#define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is Requested */ +#define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */ +#define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */ +#define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */ +#define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */ +#define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */ +#define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */ +#define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */ +#define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */ +#define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */ +#define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */ +#define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */ +#define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */ +#define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */ +#define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */ +#define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */ +#define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */ +#define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */ +#define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */ +#define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */ +#define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */ +#define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */ +#define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */ +#define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */ +#define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4YREQ_DEFAULT (_ADC_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTREQ */ + +/* Bit fields for ADC APORTCONFLICT */ +#define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */ +#define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ + +/* Bit fields for ADC SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_SHIFT 0 /**< Shift value for ADC_SINGLEDC */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_MASK 0x7UL /**< Bit mask for ADC_SINGLEDC */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCOUNT */ +#define ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT (_ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCOUNT */ + +/* Bit fields for ADC SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_SCANDC_SHIFT 0 /**< Shift value for ADC_SCANDC */ +#define _ADC_SCANFIFOCOUNT_SCANDC_MASK 0x7UL /**< Bit mask for ADC_SCANDC */ +#define _ADC_SCANFIFOCOUNT_SCANDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCOUNT */ +#define ADC_SCANFIFOCOUNT_SCANDC_DEFAULT (_ADC_SCANFIFOCOUNT_SCANDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCOUNT */ + +/* Bit fields for ADC SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */ +#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO Content */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */ +#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT (_ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCLEAR */ + +/* Bit fields for ADC SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */ +#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO Content */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */ +#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT (_ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCLEAR */ + +/* Bit fields for ADC APORTMASTERDIS */ +#define _ADC_APORTMASTERDIS_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTMASTERDIS */ +#define _ADC_APORTMASTERDIS_MASK 0x000003FCUL /**< Mask for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1XMASTERDIS (0x1UL << 2) /**< APORT1X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_SHIFT 2 /**< Shift value for ADC_APORT1XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_MASK 0x4UL /**< Bit mask for ADC_APORT1XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1YMASTERDIS (0x1UL << 3) /**< APORT1Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_SHIFT 3 /**< Shift value for ADC_APORT1YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_MASK 0x8UL /**< Bit mask for ADC_APORT1YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2XMASTERDIS (0x1UL << 4) /**< APORT2X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_SHIFT 4 /**< Shift value for ADC_APORT2XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_MASK 0x10UL /**< Bit mask for ADC_APORT2XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2YMASTERDIS (0x1UL << 5) /**< APORT2Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_SHIFT 5 /**< Shift value for ADC_APORT2YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_MASK 0x20UL /**< Bit mask for ADC_APORT2YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3XMASTERDIS (0x1UL << 6) /**< APORT3X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_SHIFT 6 /**< Shift value for ADC_APORT3XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_MASK 0x40UL /**< Bit mask for ADC_APORT3XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3YMASTERDIS (0x1UL << 7) /**< APORT3Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_SHIFT 7 /**< Shift value for ADC_APORT3YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_MASK 0x80UL /**< Bit mask for ADC_APORT3YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4XMASTERDIS (0x1UL << 8) /**< APORT4X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_SHIFT 8 /**< Shift value for ADC_APORT4XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_MASK 0x100UL /**< Bit mask for ADC_APORT4XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4YMASTERDIS (0x1UL << 9) /**< APORT4Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_SHIFT 9 /**< Shift value for ADC_APORT4YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_MASK 0x200UL /**< Bit mask for ADC_APORT4YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ + +/** @} */ +/** @} End of group EFM32GG11B_ADC */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_pins.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_pins.h new file mode 100644 index 0000000000000..1ce8d6edb8f71 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_pins.h @@ -0,0 +1,403 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_AF_PINS register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup EFM32GG11B_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B_AF_Pins Alternate Function Pins + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ +#define AF_ETH_MIITXCLK_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : -1) /**< Pin number for AF_ETH_MIITXCLK location number i */ +#define AF_ETH_MIITXD3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : -1) /**< Pin number for AF_ETH_MIITXD3 location number i */ +#define AF_ETH_MIITXD2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : -1) /**< Pin number for AF_ETH_MIITXD2 location number i */ +#define AF_ETH_MIITXD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : -1) /**< Pin number for AF_ETH_MIITXD1 location number i */ +#define AF_ETH_MIITXD0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1) /**< Pin number for AF_ETH_MIITXD0 location number i */ +#define AF_ETH_MIITXEN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : -1) /**< Pin number for AF_ETH_MIITXEN location number i */ +#define AF_ETH_MIITXER_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : -1) /**< Pin number for AF_ETH_MIITXER location number i */ +#define AF_ETH_MIIRXCLK_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 12 : -1) /**< Pin number for AF_ETH_MIIRXCLK location number i */ +#define AF_ETH_MIIRXD3_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 11 : -1) /**< Pin number for AF_ETH_MIIRXD3 location number i */ +#define AF_ETH_MIIRXD2_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 10 : -1) /**< Pin number for AF_ETH_MIIRXD2 location number i */ +#define AF_ETH_MIIRXD1_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 9 : -1) /**< Pin number for AF_ETH_MIIRXD1 location number i */ +#define AF_ETH_MIIRXD0_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 11 : (i) == 2 ? 9 : -1) /**< Pin number for AF_ETH_MIIRXD0 location number i */ +#define AF_ETH_MIIRXDV_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 8 : -1) /**< Pin number for AF_ETH_MIIRXDV location number i */ +#define AF_ETH_MIIRXER_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 7 : -1) /**< Pin number for AF_ETH_MIIRXER location number i */ +#define AF_ETH_MIICRS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 3 : -1) /**< Pin number for AF_ETH_MIICRS location number i */ +#define AF_ETH_MIICOL_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 4 : -1) /**< Pin number for AF_ETH_MIICOL location number i */ +#define AF_ETH_MDIO_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 0 : (i) == 3 ? 15 : -1) /**< Pin number for AF_ETH_MDIO location number i */ +#define AF_ETH_MDC_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 1 : (i) == 3 ? 6 : -1) /**< Pin number for AF_ETH_MDC location number i */ +#define AF_ETH_TSUEXTCLK_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 2 : (i) == 3 ? 8 : -1) /**< Pin number for AF_ETH_TSUEXTCLK location number i */ +#define AF_ETH_TSUTMRTOG_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 9 : -1) /**< Pin number for AF_ETH_TSUTMRTOG location number i */ +#define AF_ETH_RMIITXD1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : -1) /**< Pin number for AF_ETH_RMIITXD1 location number i */ +#define AF_ETH_RMIITXD0_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : -1) /**< Pin number for AF_ETH_RMIITXD0 location number i */ +#define AF_ETH_RMIITXEN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : -1) /**< Pin number for AF_ETH_RMIITXEN location number i */ +#define AF_ETH_RMIIRXD1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : -1) /**< Pin number for AF_ETH_RMIIRXD1 location number i */ +#define AF_ETH_RMIIRXD0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 9 : -1) /**< Pin number for AF_ETH_RMIIRXD0 location number i */ +#define AF_ETH_RMIIREFCLK_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 10 : -1) /**< Pin number for AF_ETH_RMIIREFCLK location number i */ +#define AF_ETH_RMIICRSDV_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : -1) /**< Pin number for AF_ETH_RMIICRSDV location number i */ +#define AF_ETH_RMIIRXER_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : -1) /**< Pin number for AF_ETH_RMIIRXER location number i */ +#define AF_SDIO_CLK_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : -1) /**< Pin number for AF_SDIO_CLK location number i */ +#define AF_SDIO_CMD_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : -1) /**< Pin number for AF_SDIO_CMD location number i */ +#define AF_SDIO_DAT0_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : -1) /**< Pin number for AF_SDIO_DAT0 location number i */ +#define AF_SDIO_DAT1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 1 : -1) /**< Pin number for AF_SDIO_DAT1 location number i */ +#define AF_SDIO_DAT2_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 2 : -1) /**< Pin number for AF_SDIO_DAT2 location number i */ +#define AF_SDIO_DAT3_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : -1) /**< Pin number for AF_SDIO_DAT3 location number i */ +#define AF_SDIO_DAT4_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : -1) /**< Pin number for AF_SDIO_DAT4 location number i */ +#define AF_SDIO_DAT5_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 5 : -1) /**< Pin number for AF_SDIO_DAT5 location number i */ +#define AF_SDIO_DAT6_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 3 : -1) /**< Pin number for AF_SDIO_DAT6 location number i */ +#define AF_SDIO_DAT7_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : -1) /**< Pin number for AF_SDIO_DAT7 location number i */ +#define AF_SDIO_CD_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 4 : (i) == 2 ? 6 : (i) == 3 ? 10 : -1) /**< Pin number for AF_SDIO_CD location number i */ +#define AF_SDIO_WP_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_SDIO_WP location number i */ +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ +#define AF_QSPI0_SCLK_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 0 : -1) /**< Pin number for AF_QSPI0_SCLK location number i */ +#define AF_QSPI0_DQ0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Pin number for AF_QSPI0_DQ0 location number i */ +#define AF_QSPI0_DQ1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 3 : (i) == 2 ? 2 : -1) /**< Pin number for AF_QSPI0_DQ1 location number i */ +#define AF_QSPI0_DQ2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 4 : (i) == 2 ? 3 : -1) /**< Pin number for AF_QSPI0_DQ2 location number i */ +#define AF_QSPI0_DQ3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 4 : -1) /**< Pin number for AF_QSPI0_DQ3 location number i */ +#define AF_QSPI0_DQ4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_QSPI0_DQ4 location number i */ +#define AF_QSPI0_DQ5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 6 : -1) /**< Pin number for AF_QSPI0_DQ5 location number i */ +#define AF_QSPI0_DQ6_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 7 : -1) /**< Pin number for AF_QSPI0_DQ6 location number i */ +#define AF_QSPI0_DQ7_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_QSPI0_DQ7 location number i */ +#define AF_QSPI0_CS0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 9 : -1) /**< Pin number for AF_QSPI0_CS0 location number i */ +#define AF_QSPI0_CS1_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 10 : -1) /**< Pin number for AF_QSPI0_CS1 location number i */ +#define AF_QSPI0_DQS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 15 : (i) == 2 ? 11 : -1) /**< Pin number for AF_QSPI0_DQS location number i */ +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ +#define AF_USB_VBUSEN_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_USB_VBUSEN location number i */ +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B_AF_Pins */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_ports.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_ports.h new file mode 100644 index 0000000000000..f2a631306bcb1 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_ports.h @@ -0,0 +1,403 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_AF_PORTS register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup EFM32GG11B_Alternate_Function Alternate Function + * @{ + * @defgroup EFM32GG11B_AF_Ports Alternate Function Ports + * @{ + ******************************************************************************/ + +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ +#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ +#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ +#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ +#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ +#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ +#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ +#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ +#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ +#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ +#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ +#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ +#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ +#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ +#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ +#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ +#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ +#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ +#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ +#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ +#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ +#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ +#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ +#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ +#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ +#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ +#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ +#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ +#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ +#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ +#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ +#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ +#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ +#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ +#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ +#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ +#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ +#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ +#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ +#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ +#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ +#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ +#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ +#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ +#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ +#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ +#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ +#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ +#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ +#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ +#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ +#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ +#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ +#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ +#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ +#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ +#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ +#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ +#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ +#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ +#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ +#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ +#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ +#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ +#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ +#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ +#define AF_ETH_MIITXCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXCLK location number i */ +#define AF_ETH_MIITXD3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD3 location number i */ +#define AF_ETH_MIITXD2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD2 location number i */ +#define AF_ETH_MIITXD1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD1 location number i */ +#define AF_ETH_MIITXD0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD0 location number i */ +#define AF_ETH_MIITXEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXEN location number i */ +#define AF_ETH_MIITXER_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXER location number i */ +#define AF_ETH_MIIRXCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXCLK location number i */ +#define AF_ETH_MIIRXD3_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXD3 location number i */ +#define AF_ETH_MIIRXD2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXD2 location number i */ +#define AF_ETH_MIIRXD1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXD1 location number i */ +#define AF_ETH_MIIRXD0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 5 : -1) /**< Port number for AF_ETH_MIIRXD0 location number i */ +#define AF_ETH_MIIRXDV_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 5 : -1) /**< Port number for AF_ETH_MIIRXDV location number i */ +#define AF_ETH_MIIRXER_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 5 : -1) /**< Port number for AF_ETH_MIIRXER location number i */ +#define AF_ETH_MIICRS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 6 : (i) == 2 ? 1 : -1) /**< Port number for AF_ETH_MIICRS location number i */ +#define AF_ETH_MIICOL_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 6 : (i) == 2 ? 1 : -1) /**< Port number for AF_ETH_MIICOL location number i */ +#define AF_ETH_MDIO_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_ETH_MDIO location number i */ +#define AF_ETH_MDC_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_ETH_MDC location number i */ +#define AF_ETH_TSUEXTCLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_ETH_TSUEXTCLK location number i */ +#define AF_ETH_TSUTMRTOG_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_ETH_TSUTMRTOG location number i */ +#define AF_ETH_RMIITXD1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIITXD1 location number i */ +#define AF_ETH_RMIITXD0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIITXD0 location number i */ +#define AF_ETH_RMIITXEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIITXEN location number i */ +#define AF_ETH_RMIIRXD1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIIRXD1 location number i */ +#define AF_ETH_RMIIRXD0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIIRXD0 location number i */ +#define AF_ETH_RMIIREFCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIIREFCLK location number i */ +#define AF_ETH_RMIICRSDV_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIICRSDV location number i */ +#define AF_ETH_RMIIRXER_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIIRXER location number i */ +#define AF_SDIO_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1) /**< Port number for AF_SDIO_CLK location number i */ +#define AF_SDIO_CMD_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1) /**< Port number for AF_SDIO_CMD location number i */ +#define AF_SDIO_DAT0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT0 location number i */ +#define AF_SDIO_DAT1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT1 location number i */ +#define AF_SDIO_DAT2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT2 location number i */ +#define AF_SDIO_DAT3_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT3 location number i */ +#define AF_SDIO_DAT4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT4 location number i */ +#define AF_SDIO_DAT5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT5 location number i */ +#define AF_SDIO_DAT6_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : -1) /**< Port number for AF_SDIO_DAT6 location number i */ +#define AF_SDIO_DAT7_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : -1) /**< Port number for AF_SDIO_DAT7 location number i */ +#define AF_SDIO_CD_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Port number for AF_SDIO_CD location number i */ +#define AF_SDIO_WP_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 1 : -1) /**< Port number for AF_SDIO_WP location number i */ +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ +#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ +#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ +#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ +#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ +#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ +#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ +#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ +#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ +#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ +#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ +#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ +#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ +#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ +#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ +#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ +#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ +#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ +#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ +#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ +#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ +#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ +#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ +#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ +#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ +#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ +#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ +#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ +#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ +#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ +#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ +#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ +#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ +#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ +#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ +#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ +#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ +#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ +#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ +#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ +#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ +#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ +#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ +#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ +#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ +#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ +#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ +#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ +#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ +#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ +#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ +#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ +#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ +#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ +#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ +#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ +#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ +#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ +#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ +#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ +#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ +#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ +#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ +#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ +#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ +#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ +#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ +#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ +#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ +#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ +#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ +#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ +#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ +#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ +#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ +#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ +#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ +#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ +#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ +#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ +#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ +#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ +#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ +#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ +#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ +#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ +#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ +#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ +#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ +#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ +#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ +#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ +#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ +#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ +#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ +#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ +#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ +#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ +#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ +#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ +#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ +#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ +#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ +#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ +#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ +#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ +#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ +#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ +#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ +#define AF_QSPI0_SCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_SCLK location number i */ +#define AF_QSPI0_DQ0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ0 location number i */ +#define AF_QSPI0_DQ1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ1 location number i */ +#define AF_QSPI0_DQ2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ2 location number i */ +#define AF_QSPI0_DQ3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ3 location number i */ +#define AF_QSPI0_DQ4_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ4 location number i */ +#define AF_QSPI0_DQ5_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ5 location number i */ +#define AF_QSPI0_DQ6_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ6 location number i */ +#define AF_QSPI0_DQ7_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ7 location number i */ +#define AF_QSPI0_CS0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_CS0 location number i */ +#define AF_QSPI0_CS1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_CS1 location number i */ +#define AF_QSPI0_DQS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQS location number i */ +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ +#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ +#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ +#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ +#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ +#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ +#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ +#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ +#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ +#define AF_USB_VBUSEN_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_USB_VBUSEN location number i */ +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ + +/** @} */ +/** @} End of group EFM32GG11B_AF_Ports */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can.h new file mode 100644 index 0000000000000..fb56cb5a4715c --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can.h @@ -0,0 +1,652 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_CAN register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_CAN CAN + * @{ + * @brief EFM32GG11B_CAN Register Declaration + ******************************************************************************/ +/** CAN Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t STATUS; /**< Status Register */ + __IM uint32_t ERRCNT; /**< Error Count Register */ + __IOM uint32_t BITTIMING; /**< Bit Timing Register */ + __IM uint32_t INTID; /**< Interrupt Identification Register */ + __IOM uint32_t TEST; /**< Test Register */ + __IOM uint32_t BRPE; /**< BRP Extension Register */ + __IM uint32_t TRANSREQ; /**< Transmission Request Register */ + __IM uint32_t MESSAGEDATA; /**< New Data Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IM uint32_t MESSAGESTATE; /**< Message Valid Register */ + __IOM uint32_t CONFIG; /**< Configuration Register */ + __IM uint32_t IF0IF; /**< Message Object Interrupt Flag Register */ + __IOM uint32_t IF0IFS; /**< Message Object Interrupt Flag Set Register */ + __IOM uint32_t IF0IFC; /**< Message Object Interrupt Flag Clear Register */ + __IOM uint32_t IF0IEN; /**< Message Object Interrupt Enable Register */ + __IM uint32_t IF1IF; /**< Status Interrupt Flag Register */ + __IOM uint32_t IF1IFS; /**< Message Object Interrupt Flag Set Register */ + __IOM uint32_t IF1IFC; /**< Message Object Interrupt Flag Clear Register */ + __IOM uint32_t IF1IEN; /**< Status Interrupt Enable Register */ + __IOM uint32_t ROUTE; /**< I/O Routing Register */ + + uint32_t RESERVED1[3U]; /**< Reserved registers */ + CAN_MIR_TypeDef MIR[2U]; /**< Interface Registers */ +} CAN_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_CAN + * @{ + * @defgroup EFM32GG11B_CAN_BitFields CAN Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CAN CTRL */ +#define _CAN_CTRL_RESETVALUE 0x00000001UL /**< Default value for CAN_CTRL */ +#define _CAN_CTRL_MASK 0x000000EFUL /**< Mask for CAN_CTRL */ +#define CAN_CTRL_INIT (0x1UL << 0) /**< Initialize */ +#define _CAN_CTRL_INIT_SHIFT 0 /**< Shift value for CAN_INIT */ +#define _CAN_CTRL_INIT_MASK 0x1UL /**< Bit mask for CAN_INIT */ +#define _CAN_CTRL_INIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_INIT_DEFAULT (_CAN_CTRL_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_IE (0x1UL << 1) /**< Module Interrupt Enable */ +#define _CAN_CTRL_IE_SHIFT 1 /**< Shift value for CAN_IE */ +#define _CAN_CTRL_IE_MASK 0x2UL /**< Bit mask for CAN_IE */ +#define _CAN_CTRL_IE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_IE_DEFAULT (_CAN_CTRL_IE_DEFAULT << 1) /**< Shifted mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_SIE (0x1UL << 2) /**< Status Change Interrupt Enable */ +#define _CAN_CTRL_SIE_SHIFT 2 /**< Shift value for CAN_SIE */ +#define _CAN_CTRL_SIE_MASK 0x4UL /**< Bit mask for CAN_SIE */ +#define _CAN_CTRL_SIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_SIE_DEFAULT (_CAN_CTRL_SIE_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_EIE (0x1UL << 3) /**< Error Interrupt Enable */ +#define _CAN_CTRL_EIE_SHIFT 3 /**< Shift value for CAN_EIE */ +#define _CAN_CTRL_EIE_MASK 0x8UL /**< Bit mask for CAN_EIE */ +#define _CAN_CTRL_EIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_EIE_DEFAULT (_CAN_CTRL_EIE_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_DAR (0x1UL << 5) /**< Disable Automatic Retransmission */ +#define _CAN_CTRL_DAR_SHIFT 5 /**< Shift value for CAN_DAR */ +#define _CAN_CTRL_DAR_MASK 0x20UL /**< Bit mask for CAN_DAR */ +#define _CAN_CTRL_DAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_DAR_DEFAULT (_CAN_CTRL_DAR_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_CCE (0x1UL << 6) /**< Configuration Change Enable */ +#define _CAN_CTRL_CCE_SHIFT 6 /**< Shift value for CAN_CCE */ +#define _CAN_CTRL_CCE_MASK 0x40UL /**< Bit mask for CAN_CCE */ +#define _CAN_CTRL_CCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_CCE_DEFAULT (_CAN_CTRL_CCE_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_TEST (0x1UL << 7) /**< Test Mode Enable Write */ +#define _CAN_CTRL_TEST_SHIFT 7 /**< Shift value for CAN_TEST */ +#define _CAN_CTRL_TEST_MASK 0x80UL /**< Bit mask for CAN_TEST */ +#define _CAN_CTRL_TEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */ +#define CAN_CTRL_TEST_DEFAULT (_CAN_CTRL_TEST_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_CTRL */ + +/* Bit fields for CAN STATUS */ +#define _CAN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CAN_STATUS */ +#define _CAN_STATUS_MASK 0x000000FFUL /**< Mask for CAN_STATUS */ +#define _CAN_STATUS_LEC_SHIFT 0 /**< Shift value for CAN_LEC */ +#define _CAN_STATUS_LEC_MASK 0x7UL /**< Bit mask for CAN_LEC */ +#define _CAN_STATUS_LEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ +#define _CAN_STATUS_LEC_NONE 0x00000000UL /**< Mode NONE for CAN_STATUS */ +#define _CAN_STATUS_LEC_STUFF 0x00000001UL /**< Mode STUFF for CAN_STATUS */ +#define _CAN_STATUS_LEC_FORM 0x00000002UL /**< Mode FORM for CAN_STATUS */ +#define _CAN_STATUS_LEC_ACK 0x00000003UL /**< Mode ACK for CAN_STATUS */ +#define _CAN_STATUS_LEC_BIT1 0x00000004UL /**< Mode BIT1 for CAN_STATUS */ +#define _CAN_STATUS_LEC_BIT0 0x00000005UL /**< Mode BIT0 for CAN_STATUS */ +#define _CAN_STATUS_LEC_CRC 0x00000006UL /**< Mode CRC for CAN_STATUS */ +#define _CAN_STATUS_LEC_UNUSED 0x00000007UL /**< Mode UNUSED for CAN_STATUS */ +#define CAN_STATUS_LEC_DEFAULT (_CAN_STATUS_LEC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_STATUS */ +#define CAN_STATUS_LEC_NONE (_CAN_STATUS_LEC_NONE << 0) /**< Shifted mode NONE for CAN_STATUS */ +#define CAN_STATUS_LEC_STUFF (_CAN_STATUS_LEC_STUFF << 0) /**< Shifted mode STUFF for CAN_STATUS */ +#define CAN_STATUS_LEC_FORM (_CAN_STATUS_LEC_FORM << 0) /**< Shifted mode FORM for CAN_STATUS */ +#define CAN_STATUS_LEC_ACK (_CAN_STATUS_LEC_ACK << 0) /**< Shifted mode ACK for CAN_STATUS */ +#define CAN_STATUS_LEC_BIT1 (_CAN_STATUS_LEC_BIT1 << 0) /**< Shifted mode BIT1 for CAN_STATUS */ +#define CAN_STATUS_LEC_BIT0 (_CAN_STATUS_LEC_BIT0 << 0) /**< Shifted mode BIT0 for CAN_STATUS */ +#define CAN_STATUS_LEC_CRC (_CAN_STATUS_LEC_CRC << 0) /**< Shifted mode CRC for CAN_STATUS */ +#define CAN_STATUS_LEC_UNUSED (_CAN_STATUS_LEC_UNUSED << 0) /**< Shifted mode UNUSED for CAN_STATUS */ +#define CAN_STATUS_TXOK (0x1UL << 3) /**< Transmitted a Message Successfully */ +#define _CAN_STATUS_TXOK_SHIFT 3 /**< Shift value for CAN_TXOK */ +#define _CAN_STATUS_TXOK_MASK 0x8UL /**< Bit mask for CAN_TXOK */ +#define _CAN_STATUS_TXOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ +#define CAN_STATUS_TXOK_DEFAULT (_CAN_STATUS_TXOK_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_STATUS */ +#define CAN_STATUS_RXOK (0x1UL << 4) /**< Received a Message Successfully */ +#define _CAN_STATUS_RXOK_SHIFT 4 /**< Shift value for CAN_RXOK */ +#define _CAN_STATUS_RXOK_MASK 0x10UL /**< Bit mask for CAN_RXOK */ +#define _CAN_STATUS_RXOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ +#define CAN_STATUS_RXOK_DEFAULT (_CAN_STATUS_RXOK_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_STATUS */ +#define CAN_STATUS_EPASS (0x1UL << 5) /**< Error Passive */ +#define _CAN_STATUS_EPASS_SHIFT 5 /**< Shift value for CAN_EPASS */ +#define _CAN_STATUS_EPASS_MASK 0x20UL /**< Bit mask for CAN_EPASS */ +#define _CAN_STATUS_EPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ +#define CAN_STATUS_EPASS_DEFAULT (_CAN_STATUS_EPASS_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_STATUS */ +#define CAN_STATUS_EWARN (0x1UL << 6) /**< Warning Status */ +#define _CAN_STATUS_EWARN_SHIFT 6 /**< Shift value for CAN_EWARN */ +#define _CAN_STATUS_EWARN_MASK 0x40UL /**< Bit mask for CAN_EWARN */ +#define _CAN_STATUS_EWARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ +#define CAN_STATUS_EWARN_DEFAULT (_CAN_STATUS_EWARN_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_STATUS */ +#define CAN_STATUS_BOFF (0x1UL << 7) /**< Bus Off Status */ +#define _CAN_STATUS_BOFF_SHIFT 7 /**< Shift value for CAN_BOFF */ +#define _CAN_STATUS_BOFF_MASK 0x80UL /**< Bit mask for CAN_BOFF */ +#define _CAN_STATUS_BOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */ +#define CAN_STATUS_BOFF_DEFAULT (_CAN_STATUS_BOFF_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_STATUS */ + +/* Bit fields for CAN ERRCNT */ +#define _CAN_ERRCNT_RESETVALUE 0x00000000UL /**< Default value for CAN_ERRCNT */ +#define _CAN_ERRCNT_MASK 0x0000FFFFUL /**< Mask for CAN_ERRCNT */ +#define _CAN_ERRCNT_TEC_SHIFT 0 /**< Shift value for CAN_TEC */ +#define _CAN_ERRCNT_TEC_MASK 0xFFUL /**< Bit mask for CAN_TEC */ +#define _CAN_ERRCNT_TEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */ +#define CAN_ERRCNT_TEC_DEFAULT (_CAN_ERRCNT_TEC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ERRCNT */ +#define _CAN_ERRCNT_REC_SHIFT 8 /**< Shift value for CAN_REC */ +#define _CAN_ERRCNT_REC_MASK 0x7F00UL /**< Bit mask for CAN_REC */ +#define _CAN_ERRCNT_REC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */ +#define CAN_ERRCNT_REC_DEFAULT (_CAN_ERRCNT_REC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ERRCNT */ +#define CAN_ERRCNT_RECERRP (0x1UL << 15) /**< Receive Error Passive */ +#define _CAN_ERRCNT_RECERRP_SHIFT 15 /**< Shift value for CAN_RECERRP */ +#define _CAN_ERRCNT_RECERRP_MASK 0x8000UL /**< Bit mask for CAN_RECERRP */ +#define _CAN_ERRCNT_RECERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */ +#define _CAN_ERRCNT_RECERRP_FALSE 0x00000000UL /**< Mode FALSE for CAN_ERRCNT */ +#define _CAN_ERRCNT_RECERRP_TRUE 0x00000001UL /**< Mode TRUE for CAN_ERRCNT */ +#define CAN_ERRCNT_RECERRP_DEFAULT (_CAN_ERRCNT_RECERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_ERRCNT */ +#define CAN_ERRCNT_RECERRP_FALSE (_CAN_ERRCNT_RECERRP_FALSE << 15) /**< Shifted mode FALSE for CAN_ERRCNT */ +#define CAN_ERRCNT_RECERRP_TRUE (_CAN_ERRCNT_RECERRP_TRUE << 15) /**< Shifted mode TRUE for CAN_ERRCNT */ + +/* Bit fields for CAN BITTIMING */ +#define _CAN_BITTIMING_RESETVALUE 0x00002301UL /**< Default value for CAN_BITTIMING */ +#define _CAN_BITTIMING_MASK 0x00007FFFUL /**< Mask for CAN_BITTIMING */ +#define _CAN_BITTIMING_BRP_SHIFT 0 /**< Shift value for CAN_BRP */ +#define _CAN_BITTIMING_BRP_MASK 0x3FUL /**< Bit mask for CAN_BRP */ +#define _CAN_BITTIMING_BRP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_BITTIMING */ +#define CAN_BITTIMING_BRP_DEFAULT (_CAN_BITTIMING_BRP_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BITTIMING */ +#define _CAN_BITTIMING_SJW_SHIFT 6 /**< Shift value for CAN_SJW */ +#define _CAN_BITTIMING_SJW_MASK 0xC0UL /**< Bit mask for CAN_SJW */ +#define _CAN_BITTIMING_SJW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_BITTIMING */ +#define CAN_BITTIMING_SJW_DEFAULT (_CAN_BITTIMING_SJW_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_BITTIMING */ +#define _CAN_BITTIMING_TSEG1_SHIFT 8 /**< Shift value for CAN_TSEG1 */ +#define _CAN_BITTIMING_TSEG1_MASK 0xF00UL /**< Bit mask for CAN_TSEG1 */ +#define _CAN_BITTIMING_TSEG1_DEFAULT 0x00000003UL /**< Mode DEFAULT for CAN_BITTIMING */ +#define CAN_BITTIMING_TSEG1_DEFAULT (_CAN_BITTIMING_TSEG1_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_BITTIMING */ +#define _CAN_BITTIMING_TSEG2_SHIFT 12 /**< Shift value for CAN_TSEG2 */ +#define _CAN_BITTIMING_TSEG2_MASK 0x7000UL /**< Bit mask for CAN_TSEG2 */ +#define _CAN_BITTIMING_TSEG2_DEFAULT 0x00000002UL /**< Mode DEFAULT for CAN_BITTIMING */ +#define CAN_BITTIMING_TSEG2_DEFAULT (_CAN_BITTIMING_TSEG2_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_BITTIMING */ + +/* Bit fields for CAN INTID */ +#define _CAN_INTID_RESETVALUE 0x00000000UL /**< Default value for CAN_INTID */ +#define _CAN_INTID_MASK 0x0000803FUL /**< Mask for CAN_INTID */ +#define _CAN_INTID_INTID_SHIFT 0 /**< Shift value for CAN_INTID */ +#define _CAN_INTID_INTID_MASK 0x3FUL /**< Bit mask for CAN_INTID */ +#define _CAN_INTID_INTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_INTID */ +#define CAN_INTID_INTID_DEFAULT (_CAN_INTID_INTID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_INTID */ +#define CAN_INTID_INTSTAT (0x1UL << 15) /**< Status Interupt */ +#define _CAN_INTID_INTSTAT_SHIFT 15 /**< Shift value for CAN_INTSTAT */ +#define _CAN_INTID_INTSTAT_MASK 0x8000UL /**< Bit mask for CAN_INTSTAT */ +#define _CAN_INTID_INTSTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_INTID */ +#define _CAN_INTID_INTSTAT_FALSE 0x00000000UL /**< Mode FALSE for CAN_INTID */ +#define _CAN_INTID_INTSTAT_TRUE 0x00000001UL /**< Mode TRUE for CAN_INTID */ +#define CAN_INTID_INTSTAT_DEFAULT (_CAN_INTID_INTSTAT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_INTID */ +#define CAN_INTID_INTSTAT_FALSE (_CAN_INTID_INTSTAT_FALSE << 15) /**< Shifted mode FALSE for CAN_INTID */ +#define CAN_INTID_INTSTAT_TRUE (_CAN_INTID_INTSTAT_TRUE << 15) /**< Shifted mode TRUE for CAN_INTID */ + +/* Bit fields for CAN TEST */ +#define _CAN_TEST_RESETVALUE 0x00000000UL /**< Default value for CAN_TEST */ +#define _CAN_TEST_MASK 0x000000FCUL /**< Mask for CAN_TEST */ +#define CAN_TEST_BASIC (0x1UL << 2) /**< Basic Mode */ +#define _CAN_TEST_BASIC_SHIFT 2 /**< Shift value for CAN_BASIC */ +#define _CAN_TEST_BASIC_MASK 0x4UL /**< Bit mask for CAN_BASIC */ +#define _CAN_TEST_BASIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */ +#define CAN_TEST_BASIC_DEFAULT (_CAN_TEST_BASIC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_TEST */ +#define CAN_TEST_SILENT (0x1UL << 3) /**< Silent Mode */ +#define _CAN_TEST_SILENT_SHIFT 3 /**< Shift value for CAN_SILENT */ +#define _CAN_TEST_SILENT_MASK 0x8UL /**< Bit mask for CAN_SILENT */ +#define _CAN_TEST_SILENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */ +#define CAN_TEST_SILENT_DEFAULT (_CAN_TEST_SILENT_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_TEST */ +#define CAN_TEST_LBACK (0x1UL << 4) /**< Loopback Mode */ +#define _CAN_TEST_LBACK_SHIFT 4 /**< Shift value for CAN_LBACK */ +#define _CAN_TEST_LBACK_MASK 0x10UL /**< Bit mask for CAN_LBACK */ +#define _CAN_TEST_LBACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */ +#define CAN_TEST_LBACK_DEFAULT (_CAN_TEST_LBACK_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_TEST */ +#define _CAN_TEST_TX_SHIFT 5 /**< Shift value for CAN_TX */ +#define _CAN_TEST_TX_MASK 0x60UL /**< Bit mask for CAN_TX */ +#define _CAN_TEST_TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */ +#define _CAN_TEST_TX_CORE 0x00000000UL /**< Mode CORE for CAN_TEST */ +#define _CAN_TEST_TX_SAMPT 0x00000001UL /**< Mode SAMPT for CAN_TEST */ +#define _CAN_TEST_TX_LOW 0x00000002UL /**< Mode LOW for CAN_TEST */ +#define _CAN_TEST_TX_HIGH 0x00000003UL /**< Mode HIGH for CAN_TEST */ +#define CAN_TEST_TX_DEFAULT (_CAN_TEST_TX_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_TEST */ +#define CAN_TEST_TX_CORE (_CAN_TEST_TX_CORE << 5) /**< Shifted mode CORE for CAN_TEST */ +#define CAN_TEST_TX_SAMPT (_CAN_TEST_TX_SAMPT << 5) /**< Shifted mode SAMPT for CAN_TEST */ +#define CAN_TEST_TX_LOW (_CAN_TEST_TX_LOW << 5) /**< Shifted mode LOW for CAN_TEST */ +#define CAN_TEST_TX_HIGH (_CAN_TEST_TX_HIGH << 5) /**< Shifted mode HIGH for CAN_TEST */ +#define CAN_TEST_RX (0x1UL << 7) /**< Monitors the Actual Value of CAN_RX Pin */ +#define _CAN_TEST_RX_SHIFT 7 /**< Shift value for CAN_RX */ +#define _CAN_TEST_RX_MASK 0x80UL /**< Bit mask for CAN_RX */ +#define _CAN_TEST_RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */ +#define _CAN_TEST_RX_LOW 0x00000000UL /**< Mode LOW for CAN_TEST */ +#define _CAN_TEST_RX_HIGH 0x00000001UL /**< Mode HIGH for CAN_TEST */ +#define CAN_TEST_RX_DEFAULT (_CAN_TEST_RX_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_TEST */ +#define CAN_TEST_RX_LOW (_CAN_TEST_RX_LOW << 7) /**< Shifted mode LOW for CAN_TEST */ +#define CAN_TEST_RX_HIGH (_CAN_TEST_RX_HIGH << 7) /**< Shifted mode HIGH for CAN_TEST */ + +/* Bit fields for CAN BRPE */ +#define _CAN_BRPE_RESETVALUE 0x00000000UL /**< Default value for CAN_BRPE */ +#define _CAN_BRPE_MASK 0x0000000FUL /**< Mask for CAN_BRPE */ +#define _CAN_BRPE_BRPE_SHIFT 0 /**< Shift value for CAN_BRPE */ +#define _CAN_BRPE_BRPE_MASK 0xFUL /**< Bit mask for CAN_BRPE */ +#define _CAN_BRPE_BRPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_BRPE */ +#define CAN_BRPE_BRPE_DEFAULT (_CAN_BRPE_BRPE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BRPE */ + +/* Bit fields for CAN TRANSREQ */ +#define _CAN_TRANSREQ_RESETVALUE 0x00000000UL /**< Default value for CAN_TRANSREQ */ +#define _CAN_TRANSREQ_MASK 0xFFFFFFFFUL /**< Mask for CAN_TRANSREQ */ +#define _CAN_TRANSREQ_TXRQSTOUT_SHIFT 0 /**< Shift value for CAN_TXRQSTOUT */ +#define _CAN_TRANSREQ_TXRQSTOUT_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_TXRQSTOUT */ +#define _CAN_TRANSREQ_TXRQSTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TRANSREQ */ +#define _CAN_TRANSREQ_TXRQSTOUT_FALSE 0x00000000UL /**< Mode FALSE for CAN_TRANSREQ */ +#define _CAN_TRANSREQ_TXRQSTOUT_TRUE 0x00000001UL /**< Mode TRUE for CAN_TRANSREQ */ +#define CAN_TRANSREQ_TXRQSTOUT_DEFAULT (_CAN_TRANSREQ_TXRQSTOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_TRANSREQ */ +#define CAN_TRANSREQ_TXRQSTOUT_FALSE (_CAN_TRANSREQ_TXRQSTOUT_FALSE << 0) /**< Shifted mode FALSE for CAN_TRANSREQ */ +#define CAN_TRANSREQ_TXRQSTOUT_TRUE (_CAN_TRANSREQ_TXRQSTOUT_TRUE << 0) /**< Shifted mode TRUE for CAN_TRANSREQ */ + +/* Bit fields for CAN MESSAGEDATA */ +#define _CAN_MESSAGEDATA_RESETVALUE 0x00000000UL /**< Default value for CAN_MESSAGEDATA */ +#define _CAN_MESSAGEDATA_MASK 0xFFFFFFFFUL /**< Mask for CAN_MESSAGEDATA */ +#define _CAN_MESSAGEDATA_VALID_SHIFT 0 /**< Shift value for CAN_VALID */ +#define _CAN_MESSAGEDATA_VALID_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_VALID */ +#define _CAN_MESSAGEDATA_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MESSAGEDATA */ +#define CAN_MESSAGEDATA_VALID_DEFAULT (_CAN_MESSAGEDATA_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGEDATA */ + +/* Bit fields for CAN MESSAGESTATE */ +#define _CAN_MESSAGESTATE_RESETVALUE 0x00000000UL /**< Default value for CAN_MESSAGESTATE */ +#define _CAN_MESSAGESTATE_MASK 0xFFFFFFFFUL /**< Mask for CAN_MESSAGESTATE */ +#define _CAN_MESSAGESTATE_VALID_SHIFT 0 /**< Shift value for CAN_VALID */ +#define _CAN_MESSAGESTATE_VALID_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_VALID */ +#define _CAN_MESSAGESTATE_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MESSAGESTATE */ +#define CAN_MESSAGESTATE_VALID_DEFAULT (_CAN_MESSAGESTATE_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGESTATE */ + +/* Bit fields for CAN CONFIG */ +#define _CAN_CONFIG_RESETVALUE 0x00000000UL /**< Default value for CAN_CONFIG */ +#define _CAN_CONFIG_MASK 0x00008000UL /**< Mask for CAN_CONFIG */ +#define CAN_CONFIG_DBGHALT (0x1UL << 15) /**< Debug Halt */ +#define _CAN_CONFIG_DBGHALT_SHIFT 15 /**< Shift value for CAN_DBGHALT */ +#define _CAN_CONFIG_DBGHALT_MASK 0x8000UL /**< Bit mask for CAN_DBGHALT */ +#define _CAN_CONFIG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CONFIG */ +#define _CAN_CONFIG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for CAN_CONFIG */ +#define _CAN_CONFIG_DBGHALT_STALL 0x00000001UL /**< Mode STALL for CAN_CONFIG */ +#define CAN_CONFIG_DBGHALT_DEFAULT (_CAN_CONFIG_DBGHALT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_CONFIG */ +#define CAN_CONFIG_DBGHALT_NORMAL (_CAN_CONFIG_DBGHALT_NORMAL << 15) /**< Shifted mode NORMAL for CAN_CONFIG */ +#define CAN_CONFIG_DBGHALT_STALL (_CAN_CONFIG_DBGHALT_STALL << 15) /**< Shifted mode STALL for CAN_CONFIG */ + +/* Bit fields for CAN IF0IF */ +#define _CAN_IF0IF_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IF */ +#define _CAN_IF0IF_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IF */ +#define _CAN_IF0IF_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */ +#define _CAN_IF0IF_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */ +#define _CAN_IF0IF_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IF */ +#define CAN_IF0IF_MESSAGE_DEFAULT (_CAN_IF0IF_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IF */ + +/* Bit fields for CAN IF0IFS */ +#define _CAN_IF0IFS_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IFS */ +#define _CAN_IF0IFS_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IFS */ +#define _CAN_IF0IFS_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */ +#define _CAN_IF0IFS_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */ +#define _CAN_IF0IFS_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IFS */ +#define CAN_IF0IFS_MESSAGE_DEFAULT (_CAN_IF0IFS_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFS */ + +/* Bit fields for CAN IF0IFC */ +#define _CAN_IF0IFC_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IFC */ +#define _CAN_IF0IFC_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IFC */ +#define _CAN_IF0IFC_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */ +#define _CAN_IF0IFC_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */ +#define _CAN_IF0IFC_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IFC */ +#define CAN_IF0IFC_MESSAGE_DEFAULT (_CAN_IF0IFC_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFC */ + +/* Bit fields for CAN IF0IEN */ +#define _CAN_IF0IEN_RESETVALUE 0xFFFFFFFFUL /**< Default value for CAN_IF0IEN */ +#define _CAN_IF0IEN_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IEN */ +#define _CAN_IF0IEN_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */ +#define _CAN_IF0IEN_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */ +#define _CAN_IF0IEN_MESSAGE_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for CAN_IF0IEN */ +#define CAN_IF0IEN_MESSAGE_DEFAULT (_CAN_IF0IEN_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IEN */ + +/* Bit fields for CAN IF1IF */ +#define _CAN_IF1IF_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IF */ +#define _CAN_IF1IF_MASK 0x00000001UL /**< Mask for CAN_IF1IF */ +#define CAN_IF1IF_STATUS (0x1UL << 0) /**< Status Interrupt Flag */ +#define _CAN_IF1IF_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */ +#define _CAN_IF1IF_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */ +#define _CAN_IF1IF_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IF */ +#define CAN_IF1IF_STATUS_DEFAULT (_CAN_IF1IF_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IF */ + +/* Bit fields for CAN IF1IFS */ +#define _CAN_IF1IFS_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IFS */ +#define _CAN_IF1IFS_MASK 0x00000001UL /**< Mask for CAN_IF1IFS */ +#define CAN_IF1IFS_STATUS (0x1UL << 0) /**< Set STATUS Interrupt Flag */ +#define _CAN_IF1IFS_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */ +#define _CAN_IF1IFS_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */ +#define _CAN_IF1IFS_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IFS */ +#define CAN_IF1IFS_STATUS_DEFAULT (_CAN_IF1IFS_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFS */ + +/* Bit fields for CAN IF1IFC */ +#define _CAN_IF1IFC_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IFC */ +#define _CAN_IF1IFC_MASK 0x00000001UL /**< Mask for CAN_IF1IFC */ +#define CAN_IF1IFC_STATUS (0x1UL << 0) /**< Clear STATUS Interrupt Flag */ +#define _CAN_IF1IFC_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */ +#define _CAN_IF1IFC_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */ +#define _CAN_IF1IFC_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IFC */ +#define CAN_IF1IFC_STATUS_DEFAULT (_CAN_IF1IFC_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFC */ + +/* Bit fields for CAN IF1IEN */ +#define _CAN_IF1IEN_RESETVALUE 0x00000001UL /**< Default value for CAN_IF1IEN */ +#define _CAN_IF1IEN_MASK 0x00000001UL /**< Mask for CAN_IF1IEN */ +#define CAN_IF1IEN_STATUS (0x1UL << 0) /**< STATUS Interrupt Enable */ +#define _CAN_IF1IEN_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */ +#define _CAN_IF1IEN_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */ +#define _CAN_IF1IEN_STATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_IF1IEN */ +#define CAN_IF1IEN_STATUS_DEFAULT (_CAN_IF1IEN_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IEN */ + +/* Bit fields for CAN ROUTE */ +#define _CAN_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CAN_ROUTE */ +#define _CAN_ROUTE_MASK 0x0000071DUL /**< Mask for CAN_ROUTE */ +#define CAN_ROUTE_TXPEN (0x1UL << 0) /**< TX Pin Enable */ +#define _CAN_ROUTE_TXPEN_SHIFT 0 /**< Shift value for CAN_TXPEN */ +#define _CAN_ROUTE_TXPEN_MASK 0x1UL /**< Bit mask for CAN_TXPEN */ +#define _CAN_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */ +#define CAN_ROUTE_TXPEN_DEFAULT (_CAN_ROUTE_TXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ROUTE */ +#define _CAN_ROUTE_RXLOC_SHIFT 2 /**< Shift value for CAN_RXLOC */ +#define _CAN_ROUTE_RXLOC_MASK 0x1CUL /**< Bit mask for CAN_RXLOC */ +#define _CAN_ROUTE_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for CAN_ROUTE */ +#define _CAN_ROUTE_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */ +#define _CAN_ROUTE_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for CAN_ROUTE */ +#define _CAN_ROUTE_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for CAN_ROUTE */ +#define _CAN_ROUTE_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for CAN_ROUTE */ +#define _CAN_ROUTE_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for CAN_ROUTE */ +#define _CAN_ROUTE_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for CAN_ROUTE */ +#define _CAN_ROUTE_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for CAN_ROUTE */ +#define _CAN_ROUTE_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for CAN_ROUTE */ +#define CAN_ROUTE_RXLOC_LOC0 (_CAN_ROUTE_RXLOC_LOC0 << 2) /**< Shifted mode LOC0 for CAN_ROUTE */ +#define CAN_ROUTE_RXLOC_DEFAULT (_CAN_ROUTE_RXLOC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_ROUTE */ +#define CAN_ROUTE_RXLOC_LOC1 (_CAN_ROUTE_RXLOC_LOC1 << 2) /**< Shifted mode LOC1 for CAN_ROUTE */ +#define CAN_ROUTE_RXLOC_LOC2 (_CAN_ROUTE_RXLOC_LOC2 << 2) /**< Shifted mode LOC2 for CAN_ROUTE */ +#define CAN_ROUTE_RXLOC_LOC3 (_CAN_ROUTE_RXLOC_LOC3 << 2) /**< Shifted mode LOC3 for CAN_ROUTE */ +#define CAN_ROUTE_RXLOC_LOC4 (_CAN_ROUTE_RXLOC_LOC4 << 2) /**< Shifted mode LOC4 for CAN_ROUTE */ +#define CAN_ROUTE_RXLOC_LOC5 (_CAN_ROUTE_RXLOC_LOC5 << 2) /**< Shifted mode LOC5 for CAN_ROUTE */ +#define CAN_ROUTE_RXLOC_LOC6 (_CAN_ROUTE_RXLOC_LOC6 << 2) /**< Shifted mode LOC6 for CAN_ROUTE */ +#define CAN_ROUTE_RXLOC_LOC7 (_CAN_ROUTE_RXLOC_LOC7 << 2) /**< Shifted mode LOC7 for CAN_ROUTE */ +#define _CAN_ROUTE_TXLOC_SHIFT 8 /**< Shift value for CAN_TXLOC */ +#define _CAN_ROUTE_TXLOC_MASK 0x700UL /**< Bit mask for CAN_TXLOC */ +#define _CAN_ROUTE_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for CAN_ROUTE */ +#define _CAN_ROUTE_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */ +#define _CAN_ROUTE_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for CAN_ROUTE */ +#define _CAN_ROUTE_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for CAN_ROUTE */ +#define _CAN_ROUTE_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for CAN_ROUTE */ +#define _CAN_ROUTE_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for CAN_ROUTE */ +#define _CAN_ROUTE_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for CAN_ROUTE */ +#define _CAN_ROUTE_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for CAN_ROUTE */ +#define _CAN_ROUTE_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for CAN_ROUTE */ +#define CAN_ROUTE_TXLOC_LOC0 (_CAN_ROUTE_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for CAN_ROUTE */ +#define CAN_ROUTE_TXLOC_DEFAULT (_CAN_ROUTE_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ROUTE */ +#define CAN_ROUTE_TXLOC_LOC1 (_CAN_ROUTE_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for CAN_ROUTE */ +#define CAN_ROUTE_TXLOC_LOC2 (_CAN_ROUTE_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for CAN_ROUTE */ +#define CAN_ROUTE_TXLOC_LOC3 (_CAN_ROUTE_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for CAN_ROUTE */ +#define CAN_ROUTE_TXLOC_LOC4 (_CAN_ROUTE_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for CAN_ROUTE */ +#define CAN_ROUTE_TXLOC_LOC5 (_CAN_ROUTE_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for CAN_ROUTE */ +#define CAN_ROUTE_TXLOC_LOC6 (_CAN_ROUTE_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for CAN_ROUTE */ +#define CAN_ROUTE_TXLOC_LOC7 (_CAN_ROUTE_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for CAN_ROUTE */ + +/* Bit fields for CAN MIR_CMDMASK */ +#define _CAN_MIR_CMDMASK_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_CMDMASK */ +#define _CAN_MIR_CMDMASK_MASK 0x000000FFUL /**< Mask for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_DATAB (0x1UL << 0) /**< CC Channel Mode */ +#define _CAN_MIR_CMDMASK_DATAB_SHIFT 0 /**< Shift value for CAN_DATAB */ +#define _CAN_MIR_CMDMASK_DATAB_MASK 0x1UL /**< Bit mask for CAN_DATAB */ +#define _CAN_MIR_CMDMASK_DATAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_DATAB_DEFAULT (_CAN_MIR_CMDMASK_DATAB_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_DATAA (0x1UL << 1) /**< Access Data Bytes 0-3 */ +#define _CAN_MIR_CMDMASK_DATAA_SHIFT 1 /**< Shift value for CAN_DATAA */ +#define _CAN_MIR_CMDMASK_DATAA_MASK 0x2UL /**< Bit mask for CAN_DATAA */ +#define _CAN_MIR_CMDMASK_DATAA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_DATAA_DEFAULT (_CAN_MIR_CMDMASK_DATAA_DEFAULT << 1) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_TXRQSTNEWDAT (0x1UL << 2) /**< Transmission Request Bit/ New Data Bit */ +#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_SHIFT 2 /**< Shift value for CAN_TXRQSTNEWDAT */ +#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_MASK 0x4UL /**< Bit mask for CAN_TXRQSTNEWDAT */ +#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT (_CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_CLRINTPND (0x1UL << 3) /**< Clear Interrupt Pending Bit */ +#define _CAN_MIR_CMDMASK_CLRINTPND_SHIFT 3 /**< Shift value for CAN_CLRINTPND */ +#define _CAN_MIR_CMDMASK_CLRINTPND_MASK 0x8UL /**< Bit mask for CAN_CLRINTPND */ +#define _CAN_MIR_CMDMASK_CLRINTPND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_CLRINTPND_DEFAULT (_CAN_MIR_CMDMASK_CLRINTPND_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_CONTROL (0x1UL << 4) /**< Access Control Bits */ +#define _CAN_MIR_CMDMASK_CONTROL_SHIFT 4 /**< Shift value for CAN_CONTROL */ +#define _CAN_MIR_CMDMASK_CONTROL_MASK 0x10UL /**< Bit mask for CAN_CONTROL */ +#define _CAN_MIR_CMDMASK_CONTROL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_CONTROL_DEFAULT (_CAN_MIR_CMDMASK_CONTROL_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_ARBACC (0x1UL << 5) /**< Access Arbitration Bits */ +#define _CAN_MIR_CMDMASK_ARBACC_SHIFT 5 /**< Shift value for CAN_ARBACC */ +#define _CAN_MIR_CMDMASK_ARBACC_MASK 0x20UL /**< Bit mask for CAN_ARBACC */ +#define _CAN_MIR_CMDMASK_ARBACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_ARBACC_DEFAULT (_CAN_MIR_CMDMASK_ARBACC_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_MASKACC (0x1UL << 6) /**< Access Mask Bits */ +#define _CAN_MIR_CMDMASK_MASKACC_SHIFT 6 /**< Shift value for CAN_MASKACC */ +#define _CAN_MIR_CMDMASK_MASKACC_MASK 0x40UL /**< Bit mask for CAN_MASKACC */ +#define _CAN_MIR_CMDMASK_MASKACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_MASKACC_DEFAULT (_CAN_MIR_CMDMASK_MASKACC_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_WRRD (0x1UL << 7) /**< Write/Read RAM */ +#define _CAN_MIR_CMDMASK_WRRD_SHIFT 7 /**< Shift value for CAN_WRRD */ +#define _CAN_MIR_CMDMASK_WRRD_MASK 0x80UL /**< Bit mask for CAN_WRRD */ +#define _CAN_MIR_CMDMASK_WRRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */ +#define _CAN_MIR_CMDMASK_WRRD_READ 0x00000000UL /**< Mode READ for CAN_MIR_CMDMASK */ +#define _CAN_MIR_CMDMASK_WRRD_WRITE 0x00000001UL /**< Mode WRITE for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_WRRD_DEFAULT (_CAN_MIR_CMDMASK_WRRD_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_WRRD_READ (_CAN_MIR_CMDMASK_WRRD_READ << 7) /**< Shifted mode READ for CAN_MIR_CMDMASK */ +#define CAN_MIR_CMDMASK_WRRD_WRITE (_CAN_MIR_CMDMASK_WRRD_WRITE << 7) /**< Shifted mode WRITE for CAN_MIR_CMDMASK */ + +/* Bit fields for CAN MIR_MASK */ +#define _CAN_MIR_MASK_RESETVALUE 0xDFFFFFFFUL /**< Default value for CAN_MIR_MASK */ +#define _CAN_MIR_MASK_MASK 0xDFFFFFFFUL /**< Mask for CAN_MIR_MASK */ +#define _CAN_MIR_MASK_MASK_SHIFT 0 /**< Shift value for CAN_MASK */ +#define _CAN_MIR_MASK_MASK_MASK 0x1FFFFFFFUL /**< Bit mask for CAN_MASK */ +#define _CAN_MIR_MASK_MASK_DEFAULT 0x1FFFFFFFUL /**< Mode DEFAULT for CAN_MIR_MASK */ +#define CAN_MIR_MASK_MASK_DEFAULT (_CAN_MIR_MASK_MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_MASK */ +#define CAN_MIR_MASK_MDIR (0x1UL << 30) /**< Mask Message Direction */ +#define _CAN_MIR_MASK_MDIR_SHIFT 30 /**< Shift value for CAN_MDIR */ +#define _CAN_MIR_MASK_MDIR_MASK 0x40000000UL /**< Bit mask for CAN_MDIR */ +#define _CAN_MIR_MASK_MDIR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_MASK */ +#define CAN_MIR_MASK_MDIR_DEFAULT (_CAN_MIR_MASK_MDIR_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_MASK */ +#define CAN_MIR_MASK_MXTD (0x1UL << 31) /**< Mask Extended Identifier */ +#define _CAN_MIR_MASK_MXTD_SHIFT 31 /**< Shift value for CAN_MXTD */ +#define _CAN_MIR_MASK_MXTD_MASK 0x80000000UL /**< Bit mask for CAN_MXTD */ +#define _CAN_MIR_MASK_MXTD_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_MASK */ +#define CAN_MIR_MASK_MXTD_DEFAULT (_CAN_MIR_MASK_MXTD_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_MASK */ + +/* Bit fields for CAN MIR_ARB */ +#define _CAN_MIR_ARB_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_ARB */ +#define _CAN_MIR_ARB_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_ARB */ +#define _CAN_MIR_ARB_ID_SHIFT 0 /**< Shift value for CAN_ID */ +#define _CAN_MIR_ARB_ID_MASK 0x1FFFFFFFUL /**< Bit mask for CAN_ID */ +#define _CAN_MIR_ARB_ID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */ +#define CAN_MIR_ARB_ID_DEFAULT (_CAN_MIR_ARB_ID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_ARB */ +#define CAN_MIR_ARB_DIR (0x1UL << 29) /**< Message Direction */ +#define _CAN_MIR_ARB_DIR_SHIFT 29 /**< Shift value for CAN_DIR */ +#define _CAN_MIR_ARB_DIR_MASK 0x20000000UL /**< Bit mask for CAN_DIR */ +#define _CAN_MIR_ARB_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */ +#define _CAN_MIR_ARB_DIR_RX 0x00000000UL /**< Mode RX for CAN_MIR_ARB */ +#define _CAN_MIR_ARB_DIR_TX 0x00000001UL /**< Mode TX for CAN_MIR_ARB */ +#define CAN_MIR_ARB_DIR_DEFAULT (_CAN_MIR_ARB_DIR_DEFAULT << 29) /**< Shifted mode DEFAULT for CAN_MIR_ARB */ +#define CAN_MIR_ARB_DIR_RX (_CAN_MIR_ARB_DIR_RX << 29) /**< Shifted mode RX for CAN_MIR_ARB */ +#define CAN_MIR_ARB_DIR_TX (_CAN_MIR_ARB_DIR_TX << 29) /**< Shifted mode TX for CAN_MIR_ARB */ +#define CAN_MIR_ARB_XTD (0x1UL << 30) /**< Extended Identifier */ +#define _CAN_MIR_ARB_XTD_SHIFT 30 /**< Shift value for CAN_XTD */ +#define _CAN_MIR_ARB_XTD_MASK 0x40000000UL /**< Bit mask for CAN_XTD */ +#define _CAN_MIR_ARB_XTD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */ +#define _CAN_MIR_ARB_XTD_STD 0x00000000UL /**< Mode STD for CAN_MIR_ARB */ +#define _CAN_MIR_ARB_XTD_EXT 0x00000001UL /**< Mode EXT for CAN_MIR_ARB */ +#define CAN_MIR_ARB_XTD_DEFAULT (_CAN_MIR_ARB_XTD_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_ARB */ +#define CAN_MIR_ARB_XTD_STD (_CAN_MIR_ARB_XTD_STD << 30) /**< Shifted mode STD for CAN_MIR_ARB */ +#define CAN_MIR_ARB_XTD_EXT (_CAN_MIR_ARB_XTD_EXT << 30) /**< Shifted mode EXT for CAN_MIR_ARB */ +#define CAN_MIR_ARB_MSGVAL (0x1UL << 31) /**< Message Valid */ +#define _CAN_MIR_ARB_MSGVAL_SHIFT 31 /**< Shift value for CAN_MSGVAL */ +#define _CAN_MIR_ARB_MSGVAL_MASK 0x80000000UL /**< Bit mask for CAN_MSGVAL */ +#define _CAN_MIR_ARB_MSGVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */ +#define CAN_MIR_ARB_MSGVAL_DEFAULT (_CAN_MIR_ARB_MSGVAL_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_ARB */ + +/* Bit fields for CAN MIR_CTRL */ +#define _CAN_MIR_CTRL_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_CTRL */ +#define _CAN_MIR_CTRL_MASK 0x0000FF8FUL /**< Mask for CAN_MIR_CTRL */ +#define _CAN_MIR_CTRL_DLC_SHIFT 0 /**< Shift value for CAN_DLC */ +#define _CAN_MIR_CTRL_DLC_MASK 0xFUL /**< Bit mask for CAN_DLC */ +#define _CAN_MIR_CTRL_DLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_DLC_DEFAULT (_CAN_MIR_CTRL_DLC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_EOB (0x1UL << 7) /**< End of Buffer */ +#define _CAN_MIR_CTRL_EOB_SHIFT 7 /**< Shift value for CAN_EOB */ +#define _CAN_MIR_CTRL_EOB_MASK 0x80UL /**< Bit mask for CAN_EOB */ +#define _CAN_MIR_CTRL_EOB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_EOB_DEFAULT (_CAN_MIR_CTRL_EOB_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_TXRQST (0x1UL << 8) /**< Transmit Request */ +#define _CAN_MIR_CTRL_TXRQST_SHIFT 8 /**< Shift value for CAN_TXRQST */ +#define _CAN_MIR_CTRL_TXRQST_MASK 0x100UL /**< Bit mask for CAN_TXRQST */ +#define _CAN_MIR_CTRL_TXRQST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_TXRQST_DEFAULT (_CAN_MIR_CTRL_TXRQST_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_RMTEN (0x1UL << 9) /**< Remote Enable */ +#define _CAN_MIR_CTRL_RMTEN_SHIFT 9 /**< Shift value for CAN_RMTEN */ +#define _CAN_MIR_CTRL_RMTEN_MASK 0x200UL /**< Bit mask for CAN_RMTEN */ +#define _CAN_MIR_CTRL_RMTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_RMTEN_DEFAULT (_CAN_MIR_CTRL_RMTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_RXIE (0x1UL << 10) /**< Receive Interrupt Enable */ +#define _CAN_MIR_CTRL_RXIE_SHIFT 10 /**< Shift value for CAN_RXIE */ +#define _CAN_MIR_CTRL_RXIE_MASK 0x400UL /**< Bit mask for CAN_RXIE */ +#define _CAN_MIR_CTRL_RXIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_RXIE_DEFAULT (_CAN_MIR_CTRL_RXIE_DEFAULT << 10) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_TXIE (0x1UL << 11) /**< Transmit Interrupt Enable */ +#define _CAN_MIR_CTRL_TXIE_SHIFT 11 /**< Shift value for CAN_TXIE */ +#define _CAN_MIR_CTRL_TXIE_MASK 0x800UL /**< Bit mask for CAN_TXIE */ +#define _CAN_MIR_CTRL_TXIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_TXIE_DEFAULT (_CAN_MIR_CTRL_TXIE_DEFAULT << 11) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_UMASK (0x1UL << 12) /**< Use Acceptance Mask */ +#define _CAN_MIR_CTRL_UMASK_SHIFT 12 /**< Shift value for CAN_UMASK */ +#define _CAN_MIR_CTRL_UMASK_MASK 0x1000UL /**< Bit mask for CAN_UMASK */ +#define _CAN_MIR_CTRL_UMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_UMASK_DEFAULT (_CAN_MIR_CTRL_UMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_INTPND (0x1UL << 13) /**< Interrupt Pending */ +#define _CAN_MIR_CTRL_INTPND_SHIFT 13 /**< Shift value for CAN_INTPND */ +#define _CAN_MIR_CTRL_INTPND_MASK 0x2000UL /**< Bit mask for CAN_INTPND */ +#define _CAN_MIR_CTRL_INTPND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_INTPND_DEFAULT (_CAN_MIR_CTRL_INTPND_DEFAULT << 13) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_MESSAGEOF (0x1UL << 14) /**< Message Lost (only Valid for Message Objects With Direction = Receive) */ +#define _CAN_MIR_CTRL_MESSAGEOF_SHIFT 14 /**< Shift value for CAN_MESSAGEOF */ +#define _CAN_MIR_CTRL_MESSAGEOF_MASK 0x4000UL /**< Bit mask for CAN_MESSAGEOF */ +#define _CAN_MIR_CTRL_MESSAGEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_MESSAGEOF_DEFAULT (_CAN_MIR_CTRL_MESSAGEOF_DEFAULT << 14) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_DATAVALID (0x1UL << 15) /**< New Data */ +#define _CAN_MIR_CTRL_DATAVALID_SHIFT 15 /**< Shift value for CAN_DATAVALID */ +#define _CAN_MIR_CTRL_DATAVALID_MASK 0x8000UL /**< Bit mask for CAN_DATAVALID */ +#define _CAN_MIR_CTRL_DATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */ +#define CAN_MIR_CTRL_DATAVALID_DEFAULT (_CAN_MIR_CTRL_DATAVALID_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */ + +/* Bit fields for CAN MIR_DATAL */ +#define _CAN_MIR_DATAL_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_DATAL */ +#define _CAN_MIR_DATAL_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_DATAL */ +#define _CAN_MIR_DATAL_DATA0_SHIFT 0 /**< Shift value for CAN_DATA0 */ +#define _CAN_MIR_DATAL_DATA0_MASK 0xFFUL /**< Bit mask for CAN_DATA0 */ +#define _CAN_MIR_DATAL_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */ +#define CAN_MIR_DATAL_DATA0_DEFAULT (_CAN_MIR_DATAL_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */ +#define _CAN_MIR_DATAL_DATA1_SHIFT 8 /**< Shift value for CAN_DATA1 */ +#define _CAN_MIR_DATAL_DATA1_MASK 0xFF00UL /**< Bit mask for CAN_DATA1 */ +#define _CAN_MIR_DATAL_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */ +#define CAN_MIR_DATAL_DATA1_DEFAULT (_CAN_MIR_DATAL_DATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */ +#define _CAN_MIR_DATAL_DATA2_SHIFT 16 /**< Shift value for CAN_DATA2 */ +#define _CAN_MIR_DATAL_DATA2_MASK 0xFF0000UL /**< Bit mask for CAN_DATA2 */ +#define _CAN_MIR_DATAL_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */ +#define CAN_MIR_DATAL_DATA2_DEFAULT (_CAN_MIR_DATAL_DATA2_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */ +#define _CAN_MIR_DATAL_DATA3_SHIFT 24 /**< Shift value for CAN_DATA3 */ +#define _CAN_MIR_DATAL_DATA3_MASK 0xFF000000UL /**< Bit mask for CAN_DATA3 */ +#define _CAN_MIR_DATAL_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */ +#define CAN_MIR_DATAL_DATA3_DEFAULT (_CAN_MIR_DATAL_DATA3_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */ + +/* Bit fields for CAN MIR_DATAH */ +#define _CAN_MIR_DATAH_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_DATAH */ +#define _CAN_MIR_DATAH_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_DATAH */ +#define _CAN_MIR_DATAH_DATA4_SHIFT 0 /**< Shift value for CAN_DATA4 */ +#define _CAN_MIR_DATAH_DATA4_MASK 0xFFUL /**< Bit mask for CAN_DATA4 */ +#define _CAN_MIR_DATAH_DATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */ +#define CAN_MIR_DATAH_DATA4_DEFAULT (_CAN_MIR_DATAH_DATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */ +#define _CAN_MIR_DATAH_DATA5_SHIFT 8 /**< Shift value for CAN_DATA5 */ +#define _CAN_MIR_DATAH_DATA5_MASK 0xFF00UL /**< Bit mask for CAN_DATA5 */ +#define _CAN_MIR_DATAH_DATA5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */ +#define CAN_MIR_DATAH_DATA5_DEFAULT (_CAN_MIR_DATAH_DATA5_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */ +#define _CAN_MIR_DATAH_DATA6_SHIFT 16 /**< Shift value for CAN_DATA6 */ +#define _CAN_MIR_DATAH_DATA6_MASK 0xFF0000UL /**< Bit mask for CAN_DATA6 */ +#define _CAN_MIR_DATAH_DATA6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */ +#define CAN_MIR_DATAH_DATA6_DEFAULT (_CAN_MIR_DATAH_DATA6_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */ +#define _CAN_MIR_DATAH_DATA7_SHIFT 24 /**< Shift value for CAN_DATA7 */ +#define _CAN_MIR_DATAH_DATA7_MASK 0xFF000000UL /**< Bit mask for CAN_DATA7 */ +#define _CAN_MIR_DATAH_DATA7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */ +#define CAN_MIR_DATAH_DATA7_DEFAULT (_CAN_MIR_DATAH_DATA7_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */ + +/* Bit fields for CAN MIR_CMDREQ */ +#define _CAN_MIR_CMDREQ_RESETVALUE 0x00000001UL /**< Default value for CAN_MIR_CMDREQ */ +#define _CAN_MIR_CMDREQ_MASK 0x0000803FUL /**< Mask for CAN_MIR_CMDREQ */ +#define _CAN_MIR_CMDREQ_MSGNUM_SHIFT 0 /**< Shift value for CAN_MSGNUM */ +#define _CAN_MIR_CMDREQ_MSGNUM_MASK 0x3FUL /**< Bit mask for CAN_MSGNUM */ +#define _CAN_MIR_CMDREQ_MSGNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_CMDREQ */ +#define CAN_MIR_CMDREQ_MSGNUM_DEFAULT (_CAN_MIR_CMDREQ_MSGNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */ +#define CAN_MIR_CMDREQ_BUSY (0x1UL << 15) /**< Busy Flag */ +#define _CAN_MIR_CMDREQ_BUSY_SHIFT 15 /**< Shift value for CAN_BUSY */ +#define _CAN_MIR_CMDREQ_BUSY_MASK 0x8000UL /**< Bit mask for CAN_BUSY */ +#define _CAN_MIR_CMDREQ_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDREQ */ +#define _CAN_MIR_CMDREQ_BUSY_FALSE 0x00000000UL /**< Mode FALSE for CAN_MIR_CMDREQ */ +#define _CAN_MIR_CMDREQ_BUSY_TRUE 0x00000001UL /**< Mode TRUE for CAN_MIR_CMDREQ */ +#define CAN_MIR_CMDREQ_BUSY_DEFAULT (_CAN_MIR_CMDREQ_BUSY_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */ +#define CAN_MIR_CMDREQ_BUSY_FALSE (_CAN_MIR_CMDREQ_BUSY_FALSE << 15) /**< Shifted mode FALSE for CAN_MIR_CMDREQ */ +#define CAN_MIR_CMDREQ_BUSY_TRUE (_CAN_MIR_CMDREQ_BUSY_TRUE << 15) /**< Shifted mode TRUE for CAN_MIR_CMDREQ */ + +/** @} */ +/** @} End of group EFM32GG11B_CAN */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can_mir.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can_mir.h new file mode 100644 index 0000000000000..3838f0331b31f --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can_mir.h @@ -0,0 +1,65 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_CAN_MIR register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief CAN_MIR CAN MIR Register + * @ingroup EFM32GG11B_CAN + ******************************************************************************/ +typedef struct { + __IOM uint32_t CMDMASK; /**< Interface Command Mask Register */ + __IOM uint32_t MASK; /**< Interface Mask Register */ + __IOM uint32_t ARB; /**< Interface Arbitration Register */ + __IOM uint32_t CTRL; /**< Interface Message Control Register */ + __IOM uint32_t DATAL; /**< Interface Data a Register */ + __IOM uint32_t DATAH; /**< Interface Data B Register */ + __IOM uint32_t CMDREQ; /**< Interface Command Request Register */ + uint32_t RESERVED0[1U]; /**< Reserved future */ +} CAN_MIR_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cmu.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cmu.h new file mode 100644 index 0000000000000..da7454df5c481 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cmu.h @@ -0,0 +1,2698 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_CMU register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_CMU CMU + * @{ + * @brief EFM32GG11B_CMU Register Declaration + ******************************************************************************/ +/** CMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< CMU Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ + + uint32_t RESERVED11[6U]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[3U]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ + __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ + __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ + + uint32_t RESERVED17[3U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED18[2U]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED19[2U]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + __IOM uint32_t SDIOCTRL; /**< SDIO Control Register */ + __IOM uint32_t QSPICTRL; /**< QSPI Control Register */ + + uint32_t RESERVED20[2U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ + + uint32_t RESERVED22[26U]; /**< Reserved for future use **/ + __IOM uint32_t USBCTRL; /**< USB Control Register */ + __IOM uint32_t USBCRCTRL; /**< USB Clock Recovery Control */ +} CMU_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_CMU + * @{ + * @defgroup EFM32GG11B_CMU_BitFields CMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ +#define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ +#define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ +#define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ +#define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ +#define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ +#define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ +#define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ +#define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ +#define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ +#define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ +#define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ +#define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ +#define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU LFCCLKSEL */ +#define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ +#define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ +#define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ +#define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x3A473FFFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ +#define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ +#define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ +#define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_SDIOCLKENS (0x1UL << 17) /**< SDIO Clock Enabled Status */ +#define _CMU_STATUS_SDIOCLKENS_SHIFT 17 /**< Shift value for CMU_SDIOCLKENS */ +#define _CMU_STATUS_SDIOCLKENS_MASK 0x20000UL /**< Bit mask for CMU_SDIOCLKENS */ +#define _CMU_STATUS_SDIOCLKENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_SDIOCLKENS_DEFAULT (_CMU_STATUS_SDIOCLKENS_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_QSPI0CLKENS (0x1UL << 18) /**< QSPI0 Clock Enabled Status */ +#define _CMU_STATUS_QSPI0CLKENS_SHIFT 18 /**< Shift value for CMU_QSPI0CLKENS */ +#define _CMU_STATUS_QSPI0CLKENS_MASK 0x40000UL /**< Bit mask for CMU_QSPI0CLKENS */ +#define _CMU_STATUS_QSPI0CLKENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_QSPI0CLKENS_DEFAULT (_CMU_STATUS_QSPI0CLKENS_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ +#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ +#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ +#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ +#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ +#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ +#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ +#define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ +#define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ +#define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ +#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ +#define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ +#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ +#define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ +#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ +#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ +#define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ +#define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ +#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ +#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ +#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ +#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ +#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x000007FFUL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ +#define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_ETH (0x1UL << 3) /**< Ethernet Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_ETH_SHIFT 3 /**< Shift value for CMU_ETH */ +#define _CMU_HFBUSCLKEN0_ETH_MASK 0x8UL /**< Bit mask for CMU_ETH */ +#define _CMU_HFBUSCLKEN0_ETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_ETH_DEFAULT (_CMU_HFBUSCLKEN0_ETH_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_SDIO (0x1UL << 4) /**< SDIO Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_SDIO_SHIFT 4 /**< Shift value for CMU_SDIO */ +#define _CMU_HFBUSCLKEN0_SDIO_MASK 0x10UL /**< Bit mask for CMU_SDIO */ +#define _CMU_HFBUSCLKEN0_SDIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_SDIO_DEFAULT (_CMU_HFBUSCLKEN0_SDIO_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_QSPI0 (0x1UL << 9) /**< Quad-SPI Clock Enable */ +#define _CMU_HFBUSCLKEN0_QSPI0_SHIFT 9 /**< Shift value for CMU_QSPI0 */ +#define _CMU_HFBUSCLKEN0_QSPI0_MASK 0x200UL /**< Bit mask for CMU_QSPI0 */ +#define _CMU_HFBUSCLKEN0_QSPI0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_QSPI0_DEFAULT (_CMU_HFBUSCLKEN0_QSPI0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_USB (0x1UL << 10) /**< Universal Serial Bus Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_USB_SHIFT 10 /**< Shift value for CMU_USB */ +#define _CMU_HFBUSCLKEN0_USB_MASK 0x400UL /**< Bit mask for CMU_USB */ +#define _CMU_HFBUSCLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_USB_DEFAULT (_CMU_HFBUSCLKEN0_USB_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ +#define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ +#define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ +#define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ +#define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ +#define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ +#define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ +#define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ +#define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ +#define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ +#define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ +#define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ +#define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ +#define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ +#define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ +#define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ +#define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ +#define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ +#define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ +#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ +#define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ +#define _CMU_LFCCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFCCLKEN0 */ +#define CMU_LFCCLKEN0_USB (0x1UL << 0) /**< Universal Serial Bus Interface Clock Enable */ +#define _CMU_LFCCLKEN0_USB_SHIFT 0 /**< Shift value for CMU_USB */ +#define _CMU_LFCCLKEN0_USB_MASK 0x1UL /**< Bit mask for CMU_USB */ +#define _CMU_LFCCLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKEN0 */ +#define CMU_LFCCLKEN0_USB_DEFAULT (_CMU_LFCCLKEN0_USB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ + +/* Bit fields for CMU HFBUSPRESC */ +#define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ +#define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ +#define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU HFPERPRESCB */ +#define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ +#define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ +#define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ + +/* Bit fields for CMU HFPERPRESCC */ +#define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ +#define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ +#define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ +#define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ +#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ +#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ +#define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ +#define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ +#define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ +#define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ +#define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ +#define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ +#define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU SDIOCTRL */ +#define _CMU_SDIOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_SDIOCTRL */ +#define _CMU_SDIOCTRL_MASK 0x00000083UL /**< Mask for CMU_SDIOCTRL */ +#define _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT 0 /**< Shift value for CMU_SDIOCLKSEL */ +#define _CMU_SDIOCTRL_SDIOCLKSEL_MASK 0x3UL /**< Bit mask for CMU_SDIOCLKSEL */ +#define _CMU_SDIOCTRL_SDIOCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SDIOCTRL */ +#define _CMU_SDIOCTRL_SDIOCLKSEL_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_SDIOCTRL */ +#define _CMU_SDIOCTRL_SDIOCLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_SDIOCTRL */ +#define _CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO 0x00000002UL /**< Mode AUXHFRCO for CMU_SDIOCTRL */ +#define _CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO 0x00000003UL /**< Mode USHFRCO for CMU_SDIOCTRL */ +#define CMU_SDIOCTRL_SDIOCLKSEL_DEFAULT (_CMU_SDIOCTRL_SDIOCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SDIOCTRL */ +#define CMU_SDIOCTRL_SDIOCLKSEL_HFRCO (_CMU_SDIOCTRL_SDIOCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_SDIOCTRL */ +#define CMU_SDIOCTRL_SDIOCLKSEL_HFXO (_CMU_SDIOCTRL_SDIOCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SDIOCTRL */ +#define CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO (_CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_SDIOCTRL */ +#define CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO (_CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_SDIOCTRL */ +#define CMU_SDIOCTRL_SDIOCLKDIS (0x1UL << 7) /**< SDIO Reference Clock Disable */ +#define _CMU_SDIOCTRL_SDIOCLKDIS_SHIFT 7 /**< Shift value for CMU_SDIOCLKDIS */ +#define _CMU_SDIOCTRL_SDIOCLKDIS_MASK 0x80UL /**< Bit mask for CMU_SDIOCLKDIS */ +#define _CMU_SDIOCTRL_SDIOCLKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SDIOCTRL */ +#define CMU_SDIOCTRL_SDIOCLKDIS_DEFAULT (_CMU_SDIOCTRL_SDIOCLKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_SDIOCTRL */ + +/* Bit fields for CMU QSPICTRL */ +#define _CMU_QSPICTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_QSPICTRL */ +#define _CMU_QSPICTRL_MASK 0x00000083UL /**< Mask for CMU_QSPICTRL */ +#define _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT 0 /**< Shift value for CMU_QSPI0CLKSEL */ +#define _CMU_QSPICTRL_QSPI0CLKSEL_MASK 0x3UL /**< Bit mask for CMU_QSPI0CLKSEL */ +#define _CMU_QSPICTRL_QSPI0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_QSPICTRL */ +#define _CMU_QSPICTRL_QSPI0CLKSEL_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_QSPICTRL */ +#define _CMU_QSPICTRL_QSPI0CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_QSPICTRL */ +#define _CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO 0x00000002UL /**< Mode AUXHFRCO for CMU_QSPICTRL */ +#define _CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO 0x00000003UL /**< Mode USHFRCO for CMU_QSPICTRL */ +#define CMU_QSPICTRL_QSPI0CLKSEL_DEFAULT (_CMU_QSPICTRL_QSPI0CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_QSPICTRL */ +#define CMU_QSPICTRL_QSPI0CLKSEL_HFRCO (_CMU_QSPICTRL_QSPI0CLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_QSPICTRL */ +#define CMU_QSPICTRL_QSPI0CLKSEL_HFXO (_CMU_QSPICTRL_QSPI0CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_QSPICTRL */ +#define CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO (_CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_QSPICTRL */ +#define CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO (_CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_QSPICTRL */ +#define CMU_QSPICTRL_QSPI0CLKDIS (0x1UL << 7) /**< QSPI0 Reference Clock Disable */ +#define _CMU_QSPICTRL_QSPI0CLKDIS_SHIFT 7 /**< Shift value for CMU_QSPI0CLKDIS */ +#define _CMU_QSPICTRL_QSPI0CLKDIS_MASK 0x80UL /**< Bit mask for CMU_QSPI0CLKDIS */ +#define _CMU_QSPICTRL_QSPI0CLKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_QSPICTRL */ +#define CMU_QSPICTRL_QSPI0CLKDIS_DEFAULT (_CMU_QSPICTRL_QSPI0CLKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_QSPICTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ +#define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/* Bit fields for CMU USBCTRL */ +#define _CMU_USBCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCTRL */ +#define _CMU_USBCTRL_MASK 0x00000087UL /**< Mask for CMU_USBCTRL */ +#define _CMU_USBCTRL_USBCLKSEL_SHIFT 0 /**< Shift value for CMU_USBCLKSEL */ +#define _CMU_USBCTRL_USBCLKSEL_MASK 0x7UL /**< Bit mask for CMU_USBCLKSEL */ +#define _CMU_USBCTRL_USBCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCTRL */ +#define _CMU_USBCTRL_USBCLKSEL_USHFRCO 0x00000000UL /**< Mode USHFRCO for CMU_USBCTRL */ +#define _CMU_USBCTRL_USBCLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_USBCTRL */ +#define _CMU_USBCTRL_USBCLKSEL_HFXOX2 0x00000002UL /**< Mode HFXOX2 for CMU_USBCTRL */ +#define _CMU_USBCTRL_USBCLKSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_USBCTRL */ +#define _CMU_USBCTRL_USBCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_USBCTRL */ +#define _CMU_USBCTRL_USBCLKSEL_LFRCO 0x00000005UL /**< Mode LFRCO for CMU_USBCTRL */ +#define CMU_USBCTRL_USBCLKSEL_DEFAULT (_CMU_USBCTRL_USBCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USBCTRL */ +#define CMU_USBCTRL_USBCLKSEL_USHFRCO (_CMU_USBCTRL_USBCLKSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_USBCTRL */ +#define CMU_USBCTRL_USBCLKSEL_HFXO (_CMU_USBCTRL_USBCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_USBCTRL */ +#define CMU_USBCTRL_USBCLKSEL_HFXOX2 (_CMU_USBCTRL_USBCLKSEL_HFXOX2 << 0) /**< Shifted mode HFXOX2 for CMU_USBCTRL */ +#define CMU_USBCTRL_USBCLKSEL_HFRCO (_CMU_USBCTRL_USBCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_USBCTRL */ +#define CMU_USBCTRL_USBCLKSEL_LFXO (_CMU_USBCTRL_USBCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_USBCTRL */ +#define CMU_USBCTRL_USBCLKSEL_LFRCO (_CMU_USBCTRL_USBCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_USBCTRL */ +#define CMU_USBCTRL_USBCLKEN (0x1UL << 7) /**< USB Rate Clock Enable */ +#define _CMU_USBCTRL_USBCLKEN_SHIFT 7 /**< Shift value for CMU_USBCLKEN */ +#define _CMU_USBCTRL_USBCLKEN_MASK 0x80UL /**< Bit mask for CMU_USBCLKEN */ +#define _CMU_USBCTRL_USBCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCTRL */ +#define CMU_USBCTRL_USBCLKEN_DEFAULT (_CMU_USBCTRL_USBCLKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_USBCTRL */ + +/* Bit fields for CMU USBCRCTRL */ +#define _CMU_USBCRCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCRCTRL */ +#define _CMU_USBCRCTRL_MASK 0x00000003UL /**< Mask for CMU_USBCRCTRL */ +#define CMU_USBCRCTRL_USBCREN (0x1UL << 0) /**< Clock Recovery Enable */ +#define _CMU_USBCRCTRL_USBCREN_SHIFT 0 /**< Shift value for CMU_USBCREN */ +#define _CMU_USBCRCTRL_USBCREN_MASK 0x1UL /**< Bit mask for CMU_USBCREN */ +#define _CMU_USBCRCTRL_USBCREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */ +#define CMU_USBCRCTRL_USBCREN_DEFAULT (_CMU_USBCRCTRL_USBCREN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */ +#define CMU_USBCRCTRL_USBLSCRMD (0x1UL << 1) /**< Low Speed Clock Recovery Mode */ +#define _CMU_USBCRCTRL_USBLSCRMD_SHIFT 1 /**< Shift value for CMU_USBLSCRMD */ +#define _CMU_USBCRCTRL_USBLSCRMD_MASK 0x2UL /**< Bit mask for CMU_USBLSCRMD */ +#define _CMU_USBCRCTRL_USBLSCRMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */ +#define CMU_USBCRCTRL_USBLSCRMD_DEFAULT (_CMU_USBCRCTRL_USBLSCRMD_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B_CMU */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cryotimer.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cryotimer.h new file mode 100644 index 0000000000000..9becb95932596 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cryotimer.h @@ -0,0 +1,183 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_CRYOTIMER register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_CRYOTIMER CRYOTIMER + * @{ + * @brief EFM32GG11B_CRYOTIMER Register Declaration + ******************************************************************************/ +/** CRYOTIMER Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t PERIODSEL; /**< Interrupt Duration */ + __IM uint32_t CNT; /**< Counter Value */ + __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} CRYOTIMER_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_CRYOTIMER + * @{ + * @defgroup EFM32GG11B_CRYOTIMER_BitFields CRYOTIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CRYOTIMER CTRL */ +#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_MASK 0x000000EFUL /**< Mask for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */ +#define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */ +#define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */ +#define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */ +#define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */ +#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */ +#define _CRYOTIMER_CTRL_OSCSEL_MASK 0xCUL /**< Bit mask for CRYOTIMER_OSCSEL */ +#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000002UL /**< Mode LFXO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_DISABLED (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2) /**< Shifted mode DISABLED for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */ +#define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */ +#define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */ + +/* Bit fields for CRYOTIMER PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */ +#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */ + +/* Bit fields for CRYOTIMER CNT */ +#define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */ +#define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */ + +/* Bit fields for CRYOTIMER EM4WUEN */ +#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */ +#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */ +#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */ +#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */ +#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */ +#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */ +#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */ + +/* Bit fields for CRYOTIMER IF */ +#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */ +#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */ +#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup Event/Interrupt */ +#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */ +#define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */ + +/* Bit fields for CRYOTIMER IFS */ +#define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */ +#define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */ +#define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */ +#define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */ +#define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */ + +/* Bit fields for CRYOTIMER IFC */ +#define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */ +#define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */ +#define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */ +#define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */ +#define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */ + +/* Bit fields for CRYOTIMER IEN */ +#define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */ +#define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */ +#define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */ +#define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */ +#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */ + +/** @} */ +/** @} End of group EFM32GG11B_CRYOTIMER */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_crypto.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_crypto.h new file mode 100644 index 0000000000000..e5e0b7342bc9b --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_crypto.h @@ -0,0 +1,1218 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_CRYPTO register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_CRYPTO CRYPTO + * @{ + * @brief EFM32GG11B_CRYPTO Register Declaration + ******************************************************************************/ +/** CRYPTO Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t WAC; /**< Wide Arithmetic Configuration */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t DSTATUS; /**< Data Status Register */ + __IM uint32_t CSTATUS; /**< Control Status Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t KEY; /**< KEY Register Access */ + __IOM uint32_t KEYBUF; /**< KEY Buffer Register Access */ + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t SEQCTRL; /**< Sequence Control */ + __IOM uint32_t SEQCTRLB; /**< Sequence Control B */ + uint32_t RESERVED3[2U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< AES Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t SEQ0; /**< Sequence Register 0 */ + __IOM uint32_t SEQ1; /**< Sequence Register 1 */ + __IOM uint32_t SEQ2; /**< Sequence Register 2 */ + __IOM uint32_t SEQ3; /**< Sequence Register 3 */ + __IOM uint32_t SEQ4; /**< Sequence Register 4 */ + uint32_t RESERVED4[7U]; /**< Reserved for future use **/ + __IOM uint32_t DATA0; /**< DATA0 Register Access */ + __IOM uint32_t DATA1; /**< DATA1 Register Access */ + __IOM uint32_t DATA2; /**< DATA2 Register Access */ + __IOM uint32_t DATA3; /**< DATA3 Register Access */ + uint32_t RESERVED5[4U]; /**< Reserved for future use **/ + __IOM uint32_t DATA0XOR; /**< DATA0XOR Register Access */ + uint32_t RESERVED6[3U]; /**< Reserved for future use **/ + __IOM uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */ + __IOM uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */ + uint32_t RESERVED7[1U]; /**< Reserved for future use **/ + __IOM uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */ + __IOM uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */ + __IOM uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */ + __IOM uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */ + __IOM uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */ + uint32_t RESERVED8[12U]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0; /**< DDATA0 Register Access */ + __IOM uint32_t DDATA1; /**< DDATA1 Register Access */ + __IOM uint32_t DDATA2; /**< DDATA2 Register Access */ + __IOM uint32_t DDATA3; /**< DDATA3 Register Access */ + __IOM uint32_t DDATA4; /**< DDATA4 Register Access */ + uint32_t RESERVED9[7U]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */ + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */ + __IOM uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */ + __IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 Access */ + uint32_t RESERVED11[13U]; /**< Reserved for future use **/ + __IOM uint32_t QDATA0; /**< QDATA0 Register Access */ + __IOM uint32_t QDATA1; /**< QDATA1 Register Access */ + uint32_t RESERVED12[7U]; /**< Reserved for future use **/ + __IOM uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */ + uint32_t RESERVED13[6U]; /**< Reserved for future use **/ + __IOM uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */ + __IOM uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */ +} CRYPTO_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_CRYPTO + * @{ + * @defgroup EFM32GG11B_CRYPTO_BitFields CRYPTO Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CRYPTO CTRL */ +#define _CRYPTO_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_MASK 0xB333C407UL /**< Mask for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES (0x1UL << 0) /**< AES Mode */ +#define _CRYPTO_CTRL_AES_SHIFT 0 /**< Shift value for CRYPTO_AES */ +#define _CRYPTO_CTRL_AES_MASK 0x1UL /**< Bit mask for CRYPTO_AES */ +#define _CRYPTO_CTRL_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_AES_AES128 0x00000000UL /**< Mode AES128 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_AES_AES256 0x00000001UL /**< Mode AES256 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_DEFAULT (_CRYPTO_CTRL_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_AES128 (_CRYPTO_CTRL_AES_AES128 << 0) /**< Shifted mode AES128 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_AES256 (_CRYPTO_CTRL_AES_AES256 << 0) /**< Shifted mode AES256 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_KEYBUFDIS (0x1UL << 1) /**< Key Buffer Disable */ +#define _CRYPTO_CTRL_KEYBUFDIS_SHIFT 1 /**< Shift value for CRYPTO_KEYBUFDIS */ +#define _CRYPTO_CTRL_KEYBUFDIS_MASK 0x2UL /**< Bit mask for CRYPTO_KEYBUFDIS */ +#define _CRYPTO_CTRL_KEYBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_KEYBUFDIS_DEFAULT (_CRYPTO_CTRL_KEYBUFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA (0x1UL << 2) /**< SHA Mode */ +#define _CRYPTO_CTRL_SHA_SHIFT 2 /**< Shift value for CRYPTO_SHA */ +#define _CRYPTO_CTRL_SHA_MASK 0x4UL /**< Bit mask for CRYPTO_SHA */ +#define _CRYPTO_CTRL_SHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_SHA_SHA1 0x00000000UL /**< Mode SHA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_SHA_SHA2 0x00000001UL /**< Mode SHA2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_DEFAULT (_CRYPTO_CTRL_SHA_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_SHA1 (_CRYPTO_CTRL_SHA_SHA1 << 2) /**< Shifted mode SHA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_SHA2 (_CRYPTO_CTRL_SHA_SHA2 << 2) /**< Shifted mode SHA2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_NOBUSYSTALL (0x1UL << 10) /**< No Stalling of Bus When Busy */ +#define _CRYPTO_CTRL_NOBUSYSTALL_SHIFT 10 /**< Shift value for CRYPTO_NOBUSYSTALL */ +#define _CRYPTO_CTRL_NOBUSYSTALL_MASK 0x400UL /**< Bit mask for CRYPTO_NOBUSYSTALL */ +#define _CRYPTO_CTRL_NOBUSYSTALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_NOBUSYSTALL_DEFAULT (_CRYPTO_CTRL_NOBUSYSTALL_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_SHIFT 14 /**< Shift value for CRYPTO_INCWIDTH */ +#define _CRYPTO_CTRL_INCWIDTH_MASK 0xC000UL /**< Bit mask for CRYPTO_INCWIDTH */ +#define _CRYPTO_CTRL_INCWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH1 0x00000000UL /**< Mode INCWIDTH1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH2 0x00000001UL /**< Mode INCWIDTH2 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH3 0x00000002UL /**< Mode INCWIDTH3 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH4 0x00000003UL /**< Mode INCWIDTH4 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_DEFAULT (_CRYPTO_CTRL_INCWIDTH_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH1 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH1 << 14) /**< Shifted mode INCWIDTH1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH2 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH2 << 14) /**< Shifted mode INCWIDTH2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH3 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH3 << 14) /**< Shifted mode INCWIDTH3 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH4 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH4 << 14) /**< Shifted mode INCWIDTH4 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_SHIFT 16 /**< Shift value for CRYPTO_DMA0MODE */ +#define _CRYPTO_CTRL_DMA0MODE_MASK 0x30000UL /**< Bit mask for CRYPTO_DMA0MODE */ +#define _CRYPTO_CTRL_DMA0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_DEFAULT (_CRYPTO_CTRL_DMA0MODE_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_FULL (_CRYPTO_CTRL_DMA0MODE_FULL << 16) /**< Shifted mode FULL for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_LENLIMIT (_CRYPTO_CTRL_DMA0MODE_LENLIMIT << 16) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_FULLBYTE (_CRYPTO_CTRL_DMA0MODE_FULLBYTE << 16) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE << 16) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_SHIFT 20 /**< Shift value for CRYPTO_DMA0RSEL */ +#define _CRYPTO_CTRL_DMA0RSEL_MASK 0x300000UL /**< Bit mask for CRYPTO_DMA0RSEL */ +#define _CRYPTO_CTRL_DMA0RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DATA0 0x00000000UL /**< Mode DATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DDATA0 0x00000001UL /**< Mode DDATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DDATA0BIG 0x00000002UL /**< Mode DDATA0BIG for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_QDATA0 0x00000003UL /**< Mode QDATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DEFAULT (_CRYPTO_CTRL_DMA0RSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DATA0 (_CRYPTO_CTRL_DMA0RSEL_DATA0 << 20) /**< Shifted mode DATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DDATA0 (_CRYPTO_CTRL_DMA0RSEL_DDATA0 << 20) /**< Shifted mode DDATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DDATA0BIG (_CRYPTO_CTRL_DMA0RSEL_DDATA0BIG << 20) /**< Shifted mode DDATA0BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_QDATA0 (_CRYPTO_CTRL_DMA0RSEL_QDATA0 << 20) /**< Shifted mode QDATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_SHIFT 24 /**< Shift value for CRYPTO_DMA1MODE */ +#define _CRYPTO_CTRL_DMA1MODE_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA1MODE */ +#define _CRYPTO_CTRL_DMA1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_DEFAULT (_CRYPTO_CTRL_DMA1MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_FULL (_CRYPTO_CTRL_DMA1MODE_FULL << 24) /**< Shifted mode FULL for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_LENLIMIT (_CRYPTO_CTRL_DMA1MODE_LENLIMIT << 24) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_FULLBYTE (_CRYPTO_CTRL_DMA1MODE_FULLBYTE << 24) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE << 24) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_SHIFT 28 /**< Shift value for CRYPTO_DMA1RSEL */ +#define _CRYPTO_CTRL_DMA1RSEL_MASK 0x30000000UL /**< Bit mask for CRYPTO_DMA1RSEL */ +#define _CRYPTO_CTRL_DMA1RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_DATA1 0x00000000UL /**< Mode DATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_QDATA1 0x00000002UL /**< Mode QDATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_QDATA1BIG 0x00000003UL /**< Mode QDATA1BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DEFAULT (_CRYPTO_CTRL_DMA1RSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DATA1 (_CRYPTO_CTRL_DMA1RSEL_DATA1 << 28) /**< Shifted mode DATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DDATA1 (_CRYPTO_CTRL_DMA1RSEL_DDATA1 << 28) /**< Shifted mode DDATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_QDATA1 (_CRYPTO_CTRL_DMA1RSEL_QDATA1 << 28) /**< Shifted mode QDATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_QDATA1BIG (_CRYPTO_CTRL_DMA1RSEL_QDATA1BIG << 28) /**< Shifted mode QDATA1BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_COMBDMA0WEREQ (0x1UL << 31) /**< Combined Data0 Write DMA Request */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_SHIFT 31 /**< Shift value for CRYPTO_COMBDMA0WEREQ */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_MASK 0x80000000UL /**< Bit mask for CRYPTO_COMBDMA0WEREQ */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT (_CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ + +/* Bit fields for CRYPTO WAC */ +#define _CRYPTO_WAC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_WAC */ +#define _CRYPTO_WAC_MASK 0x00000F1FUL /**< Mask for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_SHIFT 0 /**< Shift value for CRYPTO_MODULUS */ +#define _CRYPTO_WAC_MODULUS_MASK 0xFUL /**< Bit mask for CRYPTO_MODULUS */ +#define _CRYPTO_WAC_MODULUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_BIN256 0x00000000UL /**< Mode BIN256 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_BIN128 0x00000001UL /**< Mode BIN128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233P 0x00000002UL /**< Mode ECCBIN233P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163P 0x00000003UL /**< Mode ECCBIN163P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_GCMBIN128 0x00000004UL /**< Mode GCMBIN128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME256P 0x00000005UL /**< Mode ECCPRIME256P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME224P 0x00000006UL /**< Mode ECCPRIME224P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME192P 0x00000007UL /**< Mode ECCPRIME192P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233N 0x00000008UL /**< Mode ECCBIN233N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233KN 0x00000009UL /**< Mode ECCBIN233KN for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163N 0x0000000AUL /**< Mode ECCBIN163N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163KN 0x0000000BUL /**< Mode ECCBIN163KN for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME256N 0x0000000CUL /**< Mode ECCPRIME256N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME224N 0x0000000DUL /**< Mode ECCPRIME224N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME192N 0x0000000EUL /**< Mode ECCPRIME192N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_DEFAULT (_CRYPTO_WAC_MODULUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_BIN256 (_CRYPTO_WAC_MODULUS_BIN256 << 0) /**< Shifted mode BIN256 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_BIN128 (_CRYPTO_WAC_MODULUS_BIN128 << 0) /**< Shifted mode BIN128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233P (_CRYPTO_WAC_MODULUS_ECCBIN233P << 0) /**< Shifted mode ECCBIN233P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163P (_CRYPTO_WAC_MODULUS_ECCBIN163P << 0) /**< Shifted mode ECCBIN163P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_GCMBIN128 (_CRYPTO_WAC_MODULUS_GCMBIN128 << 0) /**< Shifted mode GCMBIN128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME256P (_CRYPTO_WAC_MODULUS_ECCPRIME256P << 0) /**< Shifted mode ECCPRIME256P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME224P (_CRYPTO_WAC_MODULUS_ECCPRIME224P << 0) /**< Shifted mode ECCPRIME224P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME192P (_CRYPTO_WAC_MODULUS_ECCPRIME192P << 0) /**< Shifted mode ECCPRIME192P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233N (_CRYPTO_WAC_MODULUS_ECCBIN233N << 0) /**< Shifted mode ECCBIN233N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233KN (_CRYPTO_WAC_MODULUS_ECCBIN233KN << 0) /**< Shifted mode ECCBIN233KN for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163N (_CRYPTO_WAC_MODULUS_ECCBIN163N << 0) /**< Shifted mode ECCBIN163N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163KN (_CRYPTO_WAC_MODULUS_ECCBIN163KN << 0) /**< Shifted mode ECCBIN163KN for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME256N (_CRYPTO_WAC_MODULUS_ECCPRIME256N << 0) /**< Shifted mode ECCPRIME256N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME224N (_CRYPTO_WAC_MODULUS_ECCPRIME224N << 0) /**< Shifted mode ECCPRIME224N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME192N (_CRYPTO_WAC_MODULUS_ECCPRIME192N << 0) /**< Shifted mode ECCPRIME192N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP (0x1UL << 4) /**< Modular Operation Field Type */ +#define _CRYPTO_WAC_MODOP_SHIFT 4 /**< Shift value for CRYPTO_MODOP */ +#define _CRYPTO_WAC_MODOP_MASK 0x10UL /**< Bit mask for CRYPTO_MODOP */ +#define _CRYPTO_WAC_MODOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODOP_BINARY 0x00000000UL /**< Mode BINARY for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODOP_REGULAR 0x00000001UL /**< Mode REGULAR for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_DEFAULT (_CRYPTO_WAC_MODOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_BINARY (_CRYPTO_WAC_MODOP_BINARY << 4) /**< Shifted mode BINARY for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_REGULAR (_CRYPTO_WAC_MODOP_REGULAR << 4) /**< Shifted mode REGULAR for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_SHIFT 8 /**< Shift value for CRYPTO_MULWIDTH */ +#define _CRYPTO_WAC_MULWIDTH_MASK 0x300UL /**< Bit mask for CRYPTO_MULWIDTH */ +#define _CRYPTO_WAC_MULWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MUL256 0x00000000UL /**< Mode MUL256 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MUL128 0x00000001UL /**< Mode MUL128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MULMOD 0x00000002UL /**< Mode MULMOD for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_DEFAULT (_CRYPTO_WAC_MULWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MUL256 (_CRYPTO_WAC_MULWIDTH_MUL256 << 8) /**< Shifted mode MUL256 for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MUL128 (_CRYPTO_WAC_MULWIDTH_MUL128 << 8) /**< Shifted mode MUL128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MULMOD (_CRYPTO_WAC_MULWIDTH_MULMOD << 8) /**< Shifted mode MULMOD for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_SHIFT 10 /**< Shift value for CRYPTO_RESULTWIDTH */ +#define _CRYPTO_WAC_RESULTWIDTH_MASK 0xC00UL /**< Bit mask for CRYPTO_RESULTWIDTH */ +#define _CRYPTO_WAC_RESULTWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_256BIT 0x00000000UL /**< Mode 256BIT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_128BIT 0x00000001UL /**< Mode 128BIT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_260BIT 0x00000002UL /**< Mode 260BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_DEFAULT (_CRYPTO_WAC_RESULTWIDTH_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_256BIT (_CRYPTO_WAC_RESULTWIDTH_256BIT << 10) /**< Shifted mode 256BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_128BIT (_CRYPTO_WAC_RESULTWIDTH_128BIT << 10) /**< Shifted mode 128BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_260BIT (_CRYPTO_WAC_RESULTWIDTH_260BIT << 10) /**< Shifted mode 260BIT for CRYPTO_WAC */ + +/* Bit fields for CRYPTO CMD */ +#define _CRYPTO_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CMD */ +#define _CRYPTO_CMD_MASK 0x00000EFFUL /**< Mask for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHIFT 0 /**< Shift value for CRYPTO_INSTR */ +#define _CRYPTO_CMD_INSTR_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR */ +#define _CRYPTO_CMD_INSTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_END 0x00000000UL /**< Mode END for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXEC 0x00000001UL /**< Mode EXEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1INC 0x00000003UL /**< Mode DATA1INC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1INCCLR 0x00000004UL /**< Mode DATA1INCCLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_AESENC 0x00000005UL /**< Mode AESENC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_AESDEC 0x00000006UL /**< Mode AESDEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHA 0x00000007UL /**< Mode SHA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADD 0x00000008UL /**< Mode ADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDC 0x00000009UL /**< Mode ADDC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADD 0x0000000AUL /**< Mode LADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDC 0x0000000BUL /**< Mode LADDC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MADD 0x0000000CUL /**< Mode MADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MADD32 0x0000000DUL /**< Mode MADD32 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SUB 0x00000010UL /**< Mode SUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SUBC 0x00000011UL /**< Mode SUBC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LSUB 0x00000012UL /**< Mode LSUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LSUBC 0x00000013UL /**< Mode LSUBC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MSUB 0x00000014UL /**< Mode MSUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MUL 0x00000018UL /**< Mode MUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MULC 0x00000019UL /**< Mode MULC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LMUL 0x0000001AUL /**< Mode LMUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MMUL 0x0000001CUL /**< Mode MMUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MULO 0x0000001DUL /**< Mode MULO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LMULO 0x0000001FUL /**< Mode LMULO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHL 0x00000020UL /**< Mode SHL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHLC 0x00000021UL /**< Mode SHLC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHLB 0x00000022UL /**< Mode SHLB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHL1 0x00000023UL /**< Mode SHL1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHR 0x00000024UL /**< Mode SHR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRC 0x00000025UL /**< Mode SHRC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRB 0x00000026UL /**< Mode SHRB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHR1 0x00000027UL /**< Mode SHR1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDO 0x00000028UL /**< Mode ADDO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDIC 0x00000029UL /**< Mode ADDIC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDO 0x0000002AUL /**< Mode LADDO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDIC 0x0000002BUL /**< Mode LADDIC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CLR 0x00000030UL /**< Mode CLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_XOR 0x00000031UL /**< Mode XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_INV 0x00000032UL /**< Mode INV for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CSET 0x00000034UL /**< Mode CSET for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CCLR 0x00000035UL /**< Mode CCLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BBSWAP128 0x00000036UL /**< Mode BBSWAP128 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_INC 0x00000038UL /**< Mode INC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DEC 0x00000039UL /**< Mode DEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LINC 0x0000003AUL /**< Mode LINC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LDEC 0x0000003BUL /**< Mode LDEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRA 0x0000003EUL /**< Mode SHRA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0 0x00000040UL /**< Mode DATA0TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0XOR 0x00000041UL /**< Mode DATA0TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN 0x00000042UL /**< Mode DATA0TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA1 0x00000044UL /**< Mode DATA0TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA2 0x00000045UL /**< Mode DATA0TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA3 0x00000046UL /**< Mode DATA0TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0 0x00000048UL /**< Mode DATA1TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0XOR 0x00000049UL /**< Mode DATA1TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN 0x0000004AUL /**< Mode DATA1TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA2 0x0000004DUL /**< Mode DATA1TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA3 0x0000004EUL /**< Mode DATA1TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0 0x00000050UL /**< Mode DATA2TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0XOR 0x00000051UL /**< Mode DATA2TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN 0x00000052UL /**< Mode DATA2TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA1 0x00000054UL /**< Mode DATA2TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA3 0x00000056UL /**< Mode DATA2TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0 0x00000058UL /**< Mode DATA3TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0XOR 0x00000059UL /**< Mode DATA3TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN 0x0000005AUL /**< Mode DATA3TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA1 0x0000005CUL /**< Mode DATA3TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA2 0x0000005DUL /**< Mode DATA3TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATATODMA0 0x00000063UL /**< Mode DATATODMA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATATODMA1 0x0000006BUL /**< Mode DATATODMA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA0TODATA 0x00000070UL /**< Mode DMA0TODATA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA0TODATAXOR 0x00000071UL /**< Mode DMA0TODATAXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA1TODATA 0x00000072UL /**< Mode DMA1TODATA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA1 0x00000081UL /**< Mode DDATA0TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA2 0x00000082UL /**< Mode DDATA0TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA3 0x00000083UL /**< Mode DDATA0TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA4 0x00000084UL /**< Mode DDATA0TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0LTODATA0 0x00000085UL /**< Mode DDATA0LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0HTODATA1 0x00000086UL /**< Mode DDATA0HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0LTODATA2 0x00000087UL /**< Mode DDATA0LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA0 0x00000088UL /**< Mode DDATA1TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA2 0x0000008AUL /**< Mode DDATA1TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA3 0x0000008BUL /**< Mode DDATA1TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA4 0x0000008CUL /**< Mode DDATA1TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1LTODATA0 0x0000008DUL /**< Mode DDATA1LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1HTODATA1 0x0000008EUL /**< Mode DDATA1HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1LTODATA2 0x0000008FUL /**< Mode DDATA1LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA0 0x00000090UL /**< Mode DDATA2TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA1 0x00000091UL /**< Mode DDATA2TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA3 0x00000093UL /**< Mode DDATA2TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA4 0x00000094UL /**< Mode DDATA2TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2LTODATA2 0x00000097UL /**< Mode DDATA2LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA0 0x00000098UL /**< Mode DDATA3TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA1 0x00000099UL /**< Mode DDATA3TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA2 0x0000009AUL /**< Mode DDATA3TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA4 0x0000009CUL /**< Mode DDATA3TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3LTODATA0 0x0000009DUL /**< Mode DDATA3LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3HTODATA1 0x0000009EUL /**< Mode DDATA3HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA0 0x000000A0UL /**< Mode DDATA4TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA1 0x000000A1UL /**< Mode DDATA4TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA2 0x000000A2UL /**< Mode DDATA4TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA3 0x000000A3UL /**< Mode DDATA4TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4LTODATA0 0x000000A5UL /**< Mode DDATA4LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4HTODATA1 0x000000A6UL /**< Mode DDATA4HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4LTODATA2 0x000000A7UL /**< Mode DDATA4LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODDATA0 0x000000A8UL /**< Mode DATA0TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODDATA1 0x000000A9UL /**< Mode DATA0TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODDATA0 0x000000B0UL /**< Mode DATA1TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODDATA1 0x000000B1UL /**< Mode DATA1TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA0 0x000000B8UL /**< Mode DATA2TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA1 0x000000B9UL /**< Mode DATA2TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA2 0x000000BAUL /**< Mode DATA2TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA0 0x000000C0UL /**< Mode SELDDATA0DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA0 0x000000C1UL /**< Mode SELDDATA1DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA0 0x000000C2UL /**< Mode SELDDATA2DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA0 0x000000C3UL /**< Mode SELDDATA3DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA0 0x000000C4UL /**< Mode SELDDATA4DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA0 0x000000C5UL /**< Mode SELDATA0DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA0 0x000000C6UL /**< Mode SELDATA1DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA0 0x000000C7UL /**< Mode SELDATA2DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA1 0x000000C8UL /**< Mode SELDDATA0DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA1 0x000000C9UL /**< Mode SELDDATA1DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA1 0x000000CAUL /**< Mode SELDDATA2DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA1 0x000000CBUL /**< Mode SELDDATA3DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA1 0x000000CCUL /**< Mode SELDDATA4DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA1 0x000000CDUL /**< Mode SELDATA0DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA1 0x000000CEUL /**< Mode SELDATA1DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA1 0x000000CFUL /**< Mode SELDATA2DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA2 0x000000D0UL /**< Mode SELDDATA0DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA2 0x000000D1UL /**< Mode SELDDATA1DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA2 0x000000D2UL /**< Mode SELDDATA2DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA2 0x000000D3UL /**< Mode SELDDATA3DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA2 0x000000D4UL /**< Mode SELDDATA4DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA2 0x000000D5UL /**< Mode SELDATA0DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA2 0x000000D6UL /**< Mode SELDATA1DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA2 0x000000D7UL /**< Mode SELDATA2DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA3 0x000000D8UL /**< Mode SELDDATA0DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA3 0x000000D9UL /**< Mode SELDDATA1DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA3 0x000000DAUL /**< Mode SELDDATA2DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA3 0x000000DBUL /**< Mode SELDDATA3DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA3 0x000000DCUL /**< Mode SELDDATA4DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA3 0x000000DDUL /**< Mode SELDATA0DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA3 0x000000DEUL /**< Mode SELDATA1DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA3 0x000000DFUL /**< Mode SELDATA2DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA4 0x000000E0UL /**< Mode SELDDATA0DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA4 0x000000E1UL /**< Mode SELDDATA1DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA4 0x000000E2UL /**< Mode SELDDATA2DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA4 0x000000E3UL /**< Mode SELDDATA3DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA4 0x000000E4UL /**< Mode SELDDATA4DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA4 0x000000E5UL /**< Mode SELDATA0DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA4 0x000000E6UL /**< Mode SELDATA1DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA4 0x000000E7UL /**< Mode SELDATA2DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DATA0 0x000000E8UL /**< Mode SELDDATA0DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DATA0 0x000000E9UL /**< Mode SELDDATA1DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DATA0 0x000000EAUL /**< Mode SELDDATA2DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DATA0 0x000000EBUL /**< Mode SELDDATA3DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DATA0 0x000000ECUL /**< Mode SELDDATA4DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DATA0 0x000000EDUL /**< Mode SELDATA0DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DATA0 0x000000EEUL /**< Mode SELDATA1DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DATA0 0x000000EFUL /**< Mode SELDATA2DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DATA1 0x000000F0UL /**< Mode SELDDATA0DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DATA1 0x000000F1UL /**< Mode SELDDATA1DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DATA1 0x000000F2UL /**< Mode SELDDATA2DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DATA1 0x000000F3UL /**< Mode SELDDATA3DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DATA1 0x000000F4UL /**< Mode SELDDATA4DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DATA1 0x000000F5UL /**< Mode SELDATA0DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DATA1 0x000000F6UL /**< Mode SELDATA1DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DATA1 0x000000F7UL /**< Mode SELDATA2DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFA 0x000000F8UL /**< Mode EXECIFA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFB 0x000000F9UL /**< Mode EXECIFB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFNLAST 0x000000FAUL /**< Mode EXECIFNLAST for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFLAST 0x000000FBUL /**< Mode EXECIFLAST for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFCARRY 0x000000FCUL /**< Mode EXECIFCARRY for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFNCARRY 0x000000FDUL /**< Mode EXECIFNCARRY for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECALWAYS 0x000000FEUL /**< Mode EXECALWAYS for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DEFAULT (_CRYPTO_CMD_INSTR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_END (_CRYPTO_CMD_INSTR_END << 0) /**< Shifted mode END for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXEC (_CRYPTO_CMD_INSTR_EXEC << 0) /**< Shifted mode EXEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1INC (_CRYPTO_CMD_INSTR_DATA1INC << 0) /**< Shifted mode DATA1INC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1INCCLR (_CRYPTO_CMD_INSTR_DATA1INCCLR << 0) /**< Shifted mode DATA1INCCLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_AESENC (_CRYPTO_CMD_INSTR_AESENC << 0) /**< Shifted mode AESENC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_AESDEC (_CRYPTO_CMD_INSTR_AESDEC << 0) /**< Shifted mode AESDEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHA (_CRYPTO_CMD_INSTR_SHA << 0) /**< Shifted mode SHA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADD (_CRYPTO_CMD_INSTR_ADD << 0) /**< Shifted mode ADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDC (_CRYPTO_CMD_INSTR_ADDC << 0) /**< Shifted mode ADDC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADD (_CRYPTO_CMD_INSTR_LADD << 0) /**< Shifted mode LADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDC (_CRYPTO_CMD_INSTR_LADDC << 0) /**< Shifted mode LADDC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MADD (_CRYPTO_CMD_INSTR_MADD << 0) /**< Shifted mode MADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MADD32 (_CRYPTO_CMD_INSTR_MADD32 << 0) /**< Shifted mode MADD32 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SUB (_CRYPTO_CMD_INSTR_SUB << 0) /**< Shifted mode SUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SUBC (_CRYPTO_CMD_INSTR_SUBC << 0) /**< Shifted mode SUBC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LSUB (_CRYPTO_CMD_INSTR_LSUB << 0) /**< Shifted mode LSUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LSUBC (_CRYPTO_CMD_INSTR_LSUBC << 0) /**< Shifted mode LSUBC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MSUB (_CRYPTO_CMD_INSTR_MSUB << 0) /**< Shifted mode MSUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MUL (_CRYPTO_CMD_INSTR_MUL << 0) /**< Shifted mode MUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MULC (_CRYPTO_CMD_INSTR_MULC << 0) /**< Shifted mode MULC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LMUL (_CRYPTO_CMD_INSTR_LMUL << 0) /**< Shifted mode LMUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MMUL (_CRYPTO_CMD_INSTR_MMUL << 0) /**< Shifted mode MMUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MULO (_CRYPTO_CMD_INSTR_MULO << 0) /**< Shifted mode MULO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LMULO (_CRYPTO_CMD_INSTR_LMULO << 0) /**< Shifted mode LMULO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHL (_CRYPTO_CMD_INSTR_SHL << 0) /**< Shifted mode SHL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHLC (_CRYPTO_CMD_INSTR_SHLC << 0) /**< Shifted mode SHLC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHLB (_CRYPTO_CMD_INSTR_SHLB << 0) /**< Shifted mode SHLB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHL1 (_CRYPTO_CMD_INSTR_SHL1 << 0) /**< Shifted mode SHL1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHR (_CRYPTO_CMD_INSTR_SHR << 0) /**< Shifted mode SHR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRC (_CRYPTO_CMD_INSTR_SHRC << 0) /**< Shifted mode SHRC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRB (_CRYPTO_CMD_INSTR_SHRB << 0) /**< Shifted mode SHRB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHR1 (_CRYPTO_CMD_INSTR_SHR1 << 0) /**< Shifted mode SHR1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDO (_CRYPTO_CMD_INSTR_ADDO << 0) /**< Shifted mode ADDO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDIC (_CRYPTO_CMD_INSTR_ADDIC << 0) /**< Shifted mode ADDIC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDO (_CRYPTO_CMD_INSTR_LADDO << 0) /**< Shifted mode LADDO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDIC (_CRYPTO_CMD_INSTR_LADDIC << 0) /**< Shifted mode LADDIC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CLR (_CRYPTO_CMD_INSTR_CLR << 0) /**< Shifted mode CLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_XOR (_CRYPTO_CMD_INSTR_XOR << 0) /**< Shifted mode XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_INV (_CRYPTO_CMD_INSTR_INV << 0) /**< Shifted mode INV for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CSET (_CRYPTO_CMD_INSTR_CSET << 0) /**< Shifted mode CSET for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CCLR (_CRYPTO_CMD_INSTR_CCLR << 0) /**< Shifted mode CCLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BBSWAP128 (_CRYPTO_CMD_INSTR_BBSWAP128 << 0) /**< Shifted mode BBSWAP128 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_INC (_CRYPTO_CMD_INSTR_INC << 0) /**< Shifted mode INC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DEC (_CRYPTO_CMD_INSTR_DEC << 0) /**< Shifted mode DEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LINC (_CRYPTO_CMD_INSTR_LINC << 0) /**< Shifted mode LINC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LDEC (_CRYPTO_CMD_INSTR_LDEC << 0) /**< Shifted mode LDEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRA (_CRYPTO_CMD_INSTR_SHRA << 0) /**< Shifted mode SHRA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0 (_CRYPTO_CMD_INSTR_DATA0TODATA0 << 0) /**< Shifted mode DATA0TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0XOR (_CRYPTO_CMD_INSTR_DATA0TODATA0XOR << 0) /**< Shifted mode DATA0TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN << 0) /**< Shifted mode DATA0TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA1 (_CRYPTO_CMD_INSTR_DATA0TODATA1 << 0) /**< Shifted mode DATA0TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA2 (_CRYPTO_CMD_INSTR_DATA0TODATA2 << 0) /**< Shifted mode DATA0TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA3 (_CRYPTO_CMD_INSTR_DATA0TODATA3 << 0) /**< Shifted mode DATA0TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0 (_CRYPTO_CMD_INSTR_DATA1TODATA0 << 0) /**< Shifted mode DATA1TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0XOR (_CRYPTO_CMD_INSTR_DATA1TODATA0XOR << 0) /**< Shifted mode DATA1TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN << 0) /**< Shifted mode DATA1TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA2 (_CRYPTO_CMD_INSTR_DATA1TODATA2 << 0) /**< Shifted mode DATA1TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA3 (_CRYPTO_CMD_INSTR_DATA1TODATA3 << 0) /**< Shifted mode DATA1TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0 (_CRYPTO_CMD_INSTR_DATA2TODATA0 << 0) /**< Shifted mode DATA2TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0XOR (_CRYPTO_CMD_INSTR_DATA2TODATA0XOR << 0) /**< Shifted mode DATA2TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN << 0) /**< Shifted mode DATA2TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA1 (_CRYPTO_CMD_INSTR_DATA2TODATA1 << 0) /**< Shifted mode DATA2TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA3 (_CRYPTO_CMD_INSTR_DATA2TODATA3 << 0) /**< Shifted mode DATA2TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0 (_CRYPTO_CMD_INSTR_DATA3TODATA0 << 0) /**< Shifted mode DATA3TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0XOR (_CRYPTO_CMD_INSTR_DATA3TODATA0XOR << 0) /**< Shifted mode DATA3TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN << 0) /**< Shifted mode DATA3TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA1 (_CRYPTO_CMD_INSTR_DATA3TODATA1 << 0) /**< Shifted mode DATA3TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA2 (_CRYPTO_CMD_INSTR_DATA3TODATA2 << 0) /**< Shifted mode DATA3TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATATODMA0 (_CRYPTO_CMD_INSTR_DATATODMA0 << 0) /**< Shifted mode DATATODMA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATATODMA1 (_CRYPTO_CMD_INSTR_DATATODMA1 << 0) /**< Shifted mode DATATODMA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA0TODATA (_CRYPTO_CMD_INSTR_DMA0TODATA << 0) /**< Shifted mode DMA0TODATA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA0TODATAXOR (_CRYPTO_CMD_INSTR_DMA0TODATAXOR << 0) /**< Shifted mode DMA0TODATAXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA1TODATA (_CRYPTO_CMD_INSTR_DMA1TODATA << 0) /**< Shifted mode DMA1TODATA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA1 (_CRYPTO_CMD_INSTR_DDATA0TODDATA1 << 0) /**< Shifted mode DDATA0TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA2 (_CRYPTO_CMD_INSTR_DDATA0TODDATA2 << 0) /**< Shifted mode DDATA0TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA3 (_CRYPTO_CMD_INSTR_DDATA0TODDATA3 << 0) /**< Shifted mode DDATA0TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA4 (_CRYPTO_CMD_INSTR_DDATA0TODDATA4 << 0) /**< Shifted mode DDATA0TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0LTODATA0 (_CRYPTO_CMD_INSTR_DDATA0LTODATA0 << 0) /**< Shifted mode DDATA0LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0HTODATA1 (_CRYPTO_CMD_INSTR_DDATA0HTODATA1 << 0) /**< Shifted mode DDATA0HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0LTODATA2 (_CRYPTO_CMD_INSTR_DDATA0LTODATA2 << 0) /**< Shifted mode DDATA0LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA0 (_CRYPTO_CMD_INSTR_DDATA1TODDATA0 << 0) /**< Shifted mode DDATA1TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA2 (_CRYPTO_CMD_INSTR_DDATA1TODDATA2 << 0) /**< Shifted mode DDATA1TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA3 (_CRYPTO_CMD_INSTR_DDATA1TODDATA3 << 0) /**< Shifted mode DDATA1TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA4 (_CRYPTO_CMD_INSTR_DDATA1TODDATA4 << 0) /**< Shifted mode DDATA1TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1LTODATA0 (_CRYPTO_CMD_INSTR_DDATA1LTODATA0 << 0) /**< Shifted mode DDATA1LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1HTODATA1 (_CRYPTO_CMD_INSTR_DDATA1HTODATA1 << 0) /**< Shifted mode DDATA1HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1LTODATA2 (_CRYPTO_CMD_INSTR_DDATA1LTODATA2 << 0) /**< Shifted mode DDATA1LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA0 (_CRYPTO_CMD_INSTR_DDATA2TODDATA0 << 0) /**< Shifted mode DDATA2TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA1 (_CRYPTO_CMD_INSTR_DDATA2TODDATA1 << 0) /**< Shifted mode DDATA2TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA3 (_CRYPTO_CMD_INSTR_DDATA2TODDATA3 << 0) /**< Shifted mode DDATA2TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA4 (_CRYPTO_CMD_INSTR_DDATA2TODDATA4 << 0) /**< Shifted mode DDATA2TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2LTODATA2 (_CRYPTO_CMD_INSTR_DDATA2LTODATA2 << 0) /**< Shifted mode DDATA2LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA0 (_CRYPTO_CMD_INSTR_DDATA3TODDATA0 << 0) /**< Shifted mode DDATA3TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA1 (_CRYPTO_CMD_INSTR_DDATA3TODDATA1 << 0) /**< Shifted mode DDATA3TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA2 (_CRYPTO_CMD_INSTR_DDATA3TODDATA2 << 0) /**< Shifted mode DDATA3TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA4 (_CRYPTO_CMD_INSTR_DDATA3TODDATA4 << 0) /**< Shifted mode DDATA3TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3LTODATA0 (_CRYPTO_CMD_INSTR_DDATA3LTODATA0 << 0) /**< Shifted mode DDATA3LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3HTODATA1 (_CRYPTO_CMD_INSTR_DDATA3HTODATA1 << 0) /**< Shifted mode DDATA3HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA0 (_CRYPTO_CMD_INSTR_DDATA4TODDATA0 << 0) /**< Shifted mode DDATA4TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA1 (_CRYPTO_CMD_INSTR_DDATA4TODDATA1 << 0) /**< Shifted mode DDATA4TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA2 (_CRYPTO_CMD_INSTR_DDATA4TODDATA2 << 0) /**< Shifted mode DDATA4TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA3 (_CRYPTO_CMD_INSTR_DDATA4TODDATA3 << 0) /**< Shifted mode DDATA4TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4LTODATA0 (_CRYPTO_CMD_INSTR_DDATA4LTODATA0 << 0) /**< Shifted mode DDATA4LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4HTODATA1 (_CRYPTO_CMD_INSTR_DDATA4HTODATA1 << 0) /**< Shifted mode DDATA4HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4LTODATA2 (_CRYPTO_CMD_INSTR_DDATA4LTODATA2 << 0) /**< Shifted mode DDATA4LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODDATA0 (_CRYPTO_CMD_INSTR_DATA0TODDATA0 << 0) /**< Shifted mode DATA0TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODDATA1 (_CRYPTO_CMD_INSTR_DATA0TODDATA1 << 0) /**< Shifted mode DATA0TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODDATA0 (_CRYPTO_CMD_INSTR_DATA1TODDATA0 << 0) /**< Shifted mode DATA1TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODDATA1 (_CRYPTO_CMD_INSTR_DATA1TODDATA1 << 0) /**< Shifted mode DATA1TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA0 (_CRYPTO_CMD_INSTR_DATA2TODDATA0 << 0) /**< Shifted mode DATA2TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA1 (_CRYPTO_CMD_INSTR_DATA2TODDATA1 << 0) /**< Shifted mode DATA2TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA2 (_CRYPTO_CMD_INSTR_DATA2TODDATA2 << 0) /**< Shifted mode DATA2TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA0 << 0) /**< Shifted mode SELDDATA0DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA0 << 0) /**< Shifted mode SELDDATA1DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA0 << 0) /**< Shifted mode SELDDATA2DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA0 << 0) /**< Shifted mode SELDDATA3DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA0 << 0) /**< Shifted mode SELDDATA4DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDATA0DDATA0 << 0) /**< Shifted mode SELDATA0DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDATA1DDATA0 << 0) /**< Shifted mode SELDATA1DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDATA2DDATA0 << 0) /**< Shifted mode SELDATA2DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA1 << 0) /**< Shifted mode SELDDATA0DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA1 << 0) /**< Shifted mode SELDDATA1DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA1 << 0) /**< Shifted mode SELDDATA2DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA1 << 0) /**< Shifted mode SELDDATA3DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA1 << 0) /**< Shifted mode SELDDATA4DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDATA0DDATA1 << 0) /**< Shifted mode SELDATA0DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDATA1DDATA1 << 0) /**< Shifted mode SELDATA1DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDATA2DDATA1 << 0) /**< Shifted mode SELDATA2DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA2 << 0) /**< Shifted mode SELDDATA0DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA2 << 0) /**< Shifted mode SELDDATA1DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA2 << 0) /**< Shifted mode SELDDATA2DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA2 << 0) /**< Shifted mode SELDDATA3DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA2 << 0) /**< Shifted mode SELDDATA4DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDATA0DDATA2 << 0) /**< Shifted mode SELDATA0DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDATA1DDATA2 << 0) /**< Shifted mode SELDATA1DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDATA2DDATA2 << 0) /**< Shifted mode SELDATA2DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA3 << 0) /**< Shifted mode SELDDATA0DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA3 << 0) /**< Shifted mode SELDDATA1DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA3 << 0) /**< Shifted mode SELDDATA2DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA3 << 0) /**< Shifted mode SELDDATA3DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA3 << 0) /**< Shifted mode SELDDATA4DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDATA0DDATA3 << 0) /**< Shifted mode SELDATA0DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDATA1DDATA3 << 0) /**< Shifted mode SELDATA1DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDATA2DDATA3 << 0) /**< Shifted mode SELDATA2DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA4 << 0) /**< Shifted mode SELDDATA0DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA4 << 0) /**< Shifted mode SELDDATA1DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA4 << 0) /**< Shifted mode SELDDATA2DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA4 << 0) /**< Shifted mode SELDDATA3DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA4 << 0) /**< Shifted mode SELDDATA4DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDATA0DDATA4 << 0) /**< Shifted mode SELDATA0DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDATA1DDATA4 << 0) /**< Shifted mode SELDATA1DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDATA2DDATA4 << 0) /**< Shifted mode SELDATA2DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DATA0 << 0) /**< Shifted mode SELDDATA0DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DATA0 << 0) /**< Shifted mode SELDDATA1DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DATA0 << 0) /**< Shifted mode SELDDATA2DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DATA0 << 0) /**< Shifted mode SELDDATA3DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DATA0 << 0) /**< Shifted mode SELDDATA4DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDATA0DATA0 << 0) /**< Shifted mode SELDATA0DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDATA1DATA0 << 0) /**< Shifted mode SELDATA1DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDATA2DATA0 << 0) /**< Shifted mode SELDATA2DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DATA1 << 0) /**< Shifted mode SELDDATA0DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DATA1 << 0) /**< Shifted mode SELDDATA1DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DATA1 << 0) /**< Shifted mode SELDDATA2DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DATA1 << 0) /**< Shifted mode SELDDATA3DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DATA1 << 0) /**< Shifted mode SELDDATA4DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDATA0DATA1 << 0) /**< Shifted mode SELDATA0DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDATA1DATA1 << 0) /**< Shifted mode SELDATA1DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDATA2DATA1 << 0) /**< Shifted mode SELDATA2DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFA (_CRYPTO_CMD_INSTR_EXECIFA << 0) /**< Shifted mode EXECIFA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFB (_CRYPTO_CMD_INSTR_EXECIFB << 0) /**< Shifted mode EXECIFB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFNLAST (_CRYPTO_CMD_INSTR_EXECIFNLAST << 0) /**< Shifted mode EXECIFNLAST for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFLAST (_CRYPTO_CMD_INSTR_EXECIFLAST << 0) /**< Shifted mode EXECIFLAST for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFCARRY (_CRYPTO_CMD_INSTR_EXECIFCARRY << 0) /**< Shifted mode EXECIFCARRY for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFNCARRY (_CRYPTO_CMD_INSTR_EXECIFNCARRY << 0) /**< Shifted mode EXECIFNCARRY for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECALWAYS (_CRYPTO_CMD_INSTR_EXECALWAYS << 0) /**< Shifted mode EXECALWAYS for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTART (0x1UL << 9) /**< Encryption/Decryption SEQUENCE Start */ +#define _CRYPTO_CMD_SEQSTART_SHIFT 9 /**< Shift value for CRYPTO_SEQSTART */ +#define _CRYPTO_CMD_SEQSTART_MASK 0x200UL /**< Bit mask for CRYPTO_SEQSTART */ +#define _CRYPTO_CMD_SEQSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTART_DEFAULT (_CRYPTO_CMD_SEQSTART_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTOP (0x1UL << 10) /**< Sequence Stop */ +#define _CRYPTO_CMD_SEQSTOP_SHIFT 10 /**< Shift value for CRYPTO_SEQSTOP */ +#define _CRYPTO_CMD_SEQSTOP_MASK 0x400UL /**< Bit mask for CRYPTO_SEQSTOP */ +#define _CRYPTO_CMD_SEQSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTOP_DEFAULT (_CRYPTO_CMD_SEQSTOP_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTEP (0x1UL << 11) /**< Sequence Step */ +#define _CRYPTO_CMD_SEQSTEP_SHIFT 11 /**< Shift value for CRYPTO_SEQSTEP */ +#define _CRYPTO_CMD_SEQSTEP_MASK 0x800UL /**< Bit mask for CRYPTO_SEQSTEP */ +#define _CRYPTO_CMD_SEQSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTEP_DEFAULT (_CRYPTO_CMD_SEQSTEP_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTO_CMD */ + +/* Bit fields for CRYPTO STATUS */ +#define _CRYPTO_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_STATUS */ +#define _CRYPTO_STATUS_MASK 0x00000007UL /**< Mask for CRYPTO_STATUS */ +#define CRYPTO_STATUS_SEQRUNNING (0x1UL << 0) /**< AES SEQUENCE Running */ +#define _CRYPTO_STATUS_SEQRUNNING_SHIFT 0 /**< Shift value for CRYPTO_SEQRUNNING */ +#define _CRYPTO_STATUS_SEQRUNNING_MASK 0x1UL /**< Bit mask for CRYPTO_SEQRUNNING */ +#define _CRYPTO_STATUS_SEQRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_SEQRUNNING_DEFAULT (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is Active */ +#define _CRYPTO_STATUS_INSTRRUNNING_SHIFT 1 /**< Shift value for CRYPTO_INSTRRUNNING */ +#define _CRYPTO_STATUS_INSTRRUNNING_MASK 0x2UL /**< Bit mask for CRYPTO_INSTRRUNNING */ +#define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_INSTRRUNNING_DEFAULT (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is Active */ +#define _CRYPTO_STATUS_DMAACTIVE_SHIFT 2 /**< Shift value for CRYPTO_DMAACTIVE */ +#define _CRYPTO_STATUS_DMAACTIVE_MASK 0x4UL /**< Bit mask for CRYPTO_DMAACTIVE */ +#define _CRYPTO_STATUS_DMAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_DMAACTIVE_DEFAULT (_CRYPTO_STATUS_DMAACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ + +/* Bit fields for CRYPTO DSTATUS */ +#define _CRYPTO_DSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_MASK 0x011F0F0FUL /**< Mask for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_SHIFT 0 /**< Shift value for CRYPTO_DATA0ZERO */ +#define _CRYPTO_DSTATUS_DATA0ZERO_MASK 0xFUL /**< Bit mask for CRYPTO_DATA0ZERO */ +#define _CRYPTO_DSTATUS_DATA0ZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 0x00000001UL /**< Mode ZERO0TO31 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 0x00000002UL /**< Mode ZERO32TO63 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 0x00000004UL /**< Mode ZERO64TO95 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 0x00000008UL /**< Mode ZERO96TO127 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_DEFAULT (_CRYPTO_DSTATUS_DATA0ZERO_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 << 0) /**< Shifted mode ZERO0TO31 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 << 0) /**< Shifted mode ZERO32TO63 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 << 0) /**< Shifted mode ZERO64TO95 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 << 0) /**< Shifted mode ZERO96TO127 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT 8 /**< Shift value for CRYPTO_DDATA0LSBS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_MASK 0xF00UL /**< Bit mask for CRYPTO_DDATA0LSBS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT 16 /**< Shift value for CRYPTO_DDATA0MSBS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_MASK 0xF0000UL /**< Bit mask for CRYPTO_DDATA0MSBS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA1MSB (0x1UL << 20) /**< MSB in DDATA1 */ +#define _CRYPTO_DSTATUS_DDATA1MSB_SHIFT 20 /**< Shift value for CRYPTO_DDATA1MSB */ +#define _CRYPTO_DSTATUS_DDATA1MSB_MASK 0x100000UL /**< Bit mask for CRYPTO_DDATA1MSB */ +#define _CRYPTO_DSTATUS_DDATA1MSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA1MSB_DEFAULT (_CRYPTO_DSTATUS_DDATA1MSB_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_CARRY (0x1UL << 24) /**< Carry From Arithmetic Operation */ +#define _CRYPTO_DSTATUS_CARRY_SHIFT 24 /**< Shift value for CRYPTO_CARRY */ +#define _CRYPTO_DSTATUS_CARRY_MASK 0x1000000UL /**< Bit mask for CRYPTO_CARRY */ +#define _CRYPTO_DSTATUS_CARRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_CARRY_DEFAULT (_CRYPTO_DSTATUS_CARRY_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ + +/* Bit fields for CRYPTO CSTATUS */ +#define _CRYPTO_CSTATUS_RESETVALUE 0x00000201UL /**< Default value for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_MASK 0x01F30707UL /**< Mask for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_SHIFT 0 /**< Shift value for CRYPTO_V0 */ +#define _CRYPTO_CSTATUS_V0_MASK 0x7UL /**< Bit mask for CRYPTO_V0 */ +#define _CRYPTO_CSTATUS_V0_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA0 (_CRYPTO_CSTATUS_V0_DDATA0 << 0) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DEFAULT (_CRYPTO_CSTATUS_V0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA1 (_CRYPTO_CSTATUS_V0_DDATA1 << 0) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA2 (_CRYPTO_CSTATUS_V0_DDATA2 << 0) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA3 (_CRYPTO_CSTATUS_V0_DDATA3 << 0) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA4 (_CRYPTO_CSTATUS_V0_DDATA4 << 0) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA0 (_CRYPTO_CSTATUS_V0_DATA0 << 0) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA1 (_CRYPTO_CSTATUS_V0_DATA1 << 0) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA2 (_CRYPTO_CSTATUS_V0_DATA2 << 0) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_SHIFT 8 /**< Shift value for CRYPTO_V1 */ +#define _CRYPTO_CSTATUS_V1_MASK 0x700UL /**< Bit mask for CRYPTO_V1 */ +#define _CRYPTO_CSTATUS_V1_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DEFAULT 0x00000002UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA0 (_CRYPTO_CSTATUS_V1_DDATA0 << 8) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA1 (_CRYPTO_CSTATUS_V1_DDATA1 << 8) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DEFAULT (_CRYPTO_CSTATUS_V1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA2 (_CRYPTO_CSTATUS_V1_DDATA2 << 8) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA3 (_CRYPTO_CSTATUS_V1_DDATA3 << 8) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA4 (_CRYPTO_CSTATUS_V1_DDATA4 << 8) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA0 (_CRYPTO_CSTATUS_V1_DATA0 << 8) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA1 (_CRYPTO_CSTATUS_V1_DATA1 << 8) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA2 (_CRYPTO_CSTATUS_V1_DATA2 << 8) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART (0x1UL << 16) /**< Sequence Part */ +#define _CRYPTO_CSTATUS_SEQPART_SHIFT 16 /**< Shift value for CRYPTO_SEQPART */ +#define _CRYPTO_CSTATUS_SEQPART_MASK 0x10000UL /**< Bit mask for CRYPTO_SEQPART */ +#define _CRYPTO_CSTATUS_SEQPART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQPART_SEQA 0x00000000UL /**< Mode SEQA for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQPART_SEQB 0x00000001UL /**< Mode SEQB for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_DEFAULT (_CRYPTO_CSTATUS_SEQPART_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_SEQA (_CRYPTO_CSTATUS_SEQPART_SEQA << 16) /**< Shifted mode SEQA for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_SEQB (_CRYPTO_CSTATUS_SEQPART_SEQB << 16) /**< Shifted mode SEQB for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQSKIP (0x1UL << 17) /**< Sequence Skip Next Instruction */ +#define _CRYPTO_CSTATUS_SEQSKIP_SHIFT 17 /**< Shift value for CRYPTO_SEQSKIP */ +#define _CRYPTO_CSTATUS_SEQSKIP_MASK 0x20000UL /**< Bit mask for CRYPTO_SEQSKIP */ +#define _CRYPTO_CSTATUS_SEQSKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQSKIP_DEFAULT (_CRYPTO_CSTATUS_SEQSKIP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQIP_SHIFT 20 /**< Shift value for CRYPTO_SEQIP */ +#define _CRYPTO_CSTATUS_SEQIP_MASK 0x1F00000UL /**< Bit mask for CRYPTO_SEQIP */ +#define _CRYPTO_CSTATUS_SEQIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQIP_DEFAULT (_CRYPTO_CSTATUS_SEQIP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ + +/* Bit fields for CRYPTO KEY */ +#define _CRYPTO_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEY */ +#define _CRYPTO_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEY */ +#define CRYPTO_KEY_KEY_DEFAULT (_CRYPTO_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEY */ + +/* Bit fields for CRYPTO KEYBUF */ +#define _CRYPTO_KEYBUF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_SHIFT 0 /**< Shift value for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEYBUF */ +#define CRYPTO_KEYBUF_KEYBUF_DEFAULT (_CRYPTO_KEYBUF_KEYBUF_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEYBUF */ + +/* Bit fields for CRYPTO SEQCTRL */ +#define _CRYPTO_SEQCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_MASK 0xBF303FFFUL /**< Mask for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_LENGTHA_SHIFT 0 /**< Shift value for CRYPTO_LENGTHA */ +#define _CRYPTO_SEQCTRL_LENGTHA_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHA */ +#define _CRYPTO_SEQCTRL_LENGTHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_LENGTHA_DEFAULT (_CRYPTO_SEQCTRL_LENGTHA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_SHIFT 20 /**< Shift value for CRYPTO_BLOCKSIZE */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_MASK 0x300000UL /**< Bit mask for CRYPTO_BLOCKSIZE */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES 0x00000000UL /**< Mode 16BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES 0x00000001UL /**< Mode 32BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES 0x00000002UL /**< Mode 64BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT (_CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES << 20) /**< Shifted mode 16BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES << 20) /**< Shifted mode 32BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES << 20) /**< Shifted mode 64BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_SHIFT 24 /**< Shift value for CRYPTO_DMA0SKIP */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA0SKIP */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_SHIFT 26 /**< Shift value for CRYPTO_DMA1SKIP */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_MASK 0xC000000UL /**< Bit mask for CRYPTO_DMA1SKIP */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve a */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESA */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESA */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve a */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESA */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESA */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_HALT (0x1UL << 31) /**< Halt Sequence */ +#define _CRYPTO_SEQCTRL_HALT_SHIFT 31 /**< Shift value for CRYPTO_HALT */ +#define _CRYPTO_SEQCTRL_HALT_MASK 0x80000000UL /**< Bit mask for CRYPTO_HALT */ +#define _CRYPTO_SEQCTRL_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_HALT_DEFAULT (_CRYPTO_SEQCTRL_HALT_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ + +/* Bit fields for CRYPTO SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_MASK 0x30003FFFUL /**< Mask for CRYPTO_SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_SHIFT 0 /**< Shift value for CRYPTO_LENGTHB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_LENGTHB_DEFAULT (_CRYPTO_SEQCTRLB_LENGTHB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA0PRESB (0x1UL << 28) /**< DMA0 Preserve B */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESB */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESB */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA1PRESB (0x1UL << 29) /**< DMA1 Preserve B */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESB */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESB */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ + +/* Bit fields for CRYPTO IF */ +#define _CRYPTO_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IF */ +#define _CRYPTO_IF_MASK 0x00000003UL /**< Mask for CRYPTO_IF */ +#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction Done */ +#define _CRYPTO_IF_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IF_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IF_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_INSTRDONE_DEFAULT (_CRYPTO_IF_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_SEQDONE (0x1UL << 1) /**< Sequence Done */ +#define _CRYPTO_IF_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IF_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IF_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_SEQDONE_DEFAULT (_CRYPTO_IF_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IF */ + +/* Bit fields for CRYPTO IFS */ +#define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */ +#define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */ +#define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */ +#define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFS_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_INSTRDONE_DEFAULT (_CRYPTO_IFS_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_SEQDONE (0x1UL << 1) /**< Set SEQDONE Interrupt Flag */ +#define _CRYPTO_IFS_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */ + +/* Bit fields for CRYPTO IFC */ +#define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */ +#define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */ +#define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */ +#define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFC_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_INSTRDONE_DEFAULT (_CRYPTO_IFC_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_SEQDONE (0x1UL << 1) /**< Clear SEQDONE Interrupt Flag */ +#define _CRYPTO_IFC_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */ + +/* Bit fields for CRYPTO IEN */ +#define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */ +#define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */ +#define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */ +#define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IEN_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_INSTRDONE_DEFAULT (_CRYPTO_IEN_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_SEQDONE (0x1UL << 1) /**< SEQDONE Interrupt Enable */ +#define _CRYPTO_IEN_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */ + +/* Bit fields for CRYPTO SEQ0 */ +#define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR0_SHIFT 0 /**< Shift value for CRYPTO_INSTR0 */ +#define _CRYPTO_SEQ0_INSTR0_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR0 */ +#define _CRYPTO_SEQ0_INSTR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR0_DEFAULT (_CRYPTO_SEQ0_INSTR0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR1_SHIFT 8 /**< Shift value for CRYPTO_INSTR1 */ +#define _CRYPTO_SEQ0_INSTR1_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR1 */ +#define _CRYPTO_SEQ0_INSTR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR1_DEFAULT (_CRYPTO_SEQ0_INSTR1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR2_SHIFT 16 /**< Shift value for CRYPTO_INSTR2 */ +#define _CRYPTO_SEQ0_INSTR2_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR2 */ +#define _CRYPTO_SEQ0_INSTR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR2_DEFAULT (_CRYPTO_SEQ0_INSTR2_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR3_SHIFT 24 /**< Shift value for CRYPTO_INSTR3 */ +#define _CRYPTO_SEQ0_INSTR3_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR3 */ +#define _CRYPTO_SEQ0_INSTR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR3_DEFAULT (_CRYPTO_SEQ0_INSTR3_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ + +/* Bit fields for CRYPTO SEQ1 */ +#define _CRYPTO_SEQ1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR4_SHIFT 0 /**< Shift value for CRYPTO_INSTR4 */ +#define _CRYPTO_SEQ1_INSTR4_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR4 */ +#define _CRYPTO_SEQ1_INSTR4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR4_DEFAULT (_CRYPTO_SEQ1_INSTR4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR5_SHIFT 8 /**< Shift value for CRYPTO_INSTR5 */ +#define _CRYPTO_SEQ1_INSTR5_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR5 */ +#define _CRYPTO_SEQ1_INSTR5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR5_DEFAULT (_CRYPTO_SEQ1_INSTR5_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR6_SHIFT 16 /**< Shift value for CRYPTO_INSTR6 */ +#define _CRYPTO_SEQ1_INSTR6_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR6 */ +#define _CRYPTO_SEQ1_INSTR6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR6_DEFAULT (_CRYPTO_SEQ1_INSTR6_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR7_SHIFT 24 /**< Shift value for CRYPTO_INSTR7 */ +#define _CRYPTO_SEQ1_INSTR7_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR7 */ +#define _CRYPTO_SEQ1_INSTR7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR7_DEFAULT (_CRYPTO_SEQ1_INSTR7_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ + +/* Bit fields for CRYPTO SEQ2 */ +#define _CRYPTO_SEQ2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR8_SHIFT 0 /**< Shift value for CRYPTO_INSTR8 */ +#define _CRYPTO_SEQ2_INSTR8_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR8 */ +#define _CRYPTO_SEQ2_INSTR8_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR8_DEFAULT (_CRYPTO_SEQ2_INSTR8_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR9_SHIFT 8 /**< Shift value for CRYPTO_INSTR9 */ +#define _CRYPTO_SEQ2_INSTR9_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR9 */ +#define _CRYPTO_SEQ2_INSTR9_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR9_DEFAULT (_CRYPTO_SEQ2_INSTR9_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR10_SHIFT 16 /**< Shift value for CRYPTO_INSTR10 */ +#define _CRYPTO_SEQ2_INSTR10_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR10 */ +#define _CRYPTO_SEQ2_INSTR10_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR10_DEFAULT (_CRYPTO_SEQ2_INSTR10_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR11_SHIFT 24 /**< Shift value for CRYPTO_INSTR11 */ +#define _CRYPTO_SEQ2_INSTR11_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR11 */ +#define _CRYPTO_SEQ2_INSTR11_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR11_DEFAULT (_CRYPTO_SEQ2_INSTR11_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ + +/* Bit fields for CRYPTO SEQ3 */ +#define _CRYPTO_SEQ3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR12_SHIFT 0 /**< Shift value for CRYPTO_INSTR12 */ +#define _CRYPTO_SEQ3_INSTR12_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR12 */ +#define _CRYPTO_SEQ3_INSTR12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR12_DEFAULT (_CRYPTO_SEQ3_INSTR12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR13_SHIFT 8 /**< Shift value for CRYPTO_INSTR13 */ +#define _CRYPTO_SEQ3_INSTR13_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR13 */ +#define _CRYPTO_SEQ3_INSTR13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR13_DEFAULT (_CRYPTO_SEQ3_INSTR13_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR14_SHIFT 16 /**< Shift value for CRYPTO_INSTR14 */ +#define _CRYPTO_SEQ3_INSTR14_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR14 */ +#define _CRYPTO_SEQ3_INSTR14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR14_DEFAULT (_CRYPTO_SEQ3_INSTR14_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR15_SHIFT 24 /**< Shift value for CRYPTO_INSTR15 */ +#define _CRYPTO_SEQ3_INSTR15_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR15 */ +#define _CRYPTO_SEQ3_INSTR15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR15_DEFAULT (_CRYPTO_SEQ3_INSTR15_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ + +/* Bit fields for CRYPTO SEQ4 */ +#define _CRYPTO_SEQ4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR16_SHIFT 0 /**< Shift value for CRYPTO_INSTR16 */ +#define _CRYPTO_SEQ4_INSTR16_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR16 */ +#define _CRYPTO_SEQ4_INSTR16_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR16_DEFAULT (_CRYPTO_SEQ4_INSTR16_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR17_SHIFT 8 /**< Shift value for CRYPTO_INSTR17 */ +#define _CRYPTO_SEQ4_INSTR17_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR17 */ +#define _CRYPTO_SEQ4_INSTR17_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR17_DEFAULT (_CRYPTO_SEQ4_INSTR17_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR18_SHIFT 16 /**< Shift value for CRYPTO_INSTR18 */ +#define _CRYPTO_SEQ4_INSTR18_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR18 */ +#define _CRYPTO_SEQ4_INSTR18_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR18_DEFAULT (_CRYPTO_SEQ4_INSTR18_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR19_SHIFT 24 /**< Shift value for CRYPTO_INSTR19 */ +#define _CRYPTO_SEQ4_INSTR19_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR19 */ +#define _CRYPTO_SEQ4_INSTR19_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR19_DEFAULT (_CRYPTO_SEQ4_INSTR19_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ + +/* Bit fields for CRYPTO DATA0 */ +#define _CRYPTO_DATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_SHIFT 0 /**< Shift value for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0 */ +#define CRYPTO_DATA0_DATA0_DEFAULT (_CRYPTO_DATA0_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0 */ + +/* Bit fields for CRYPTO DATA1 */ +#define _CRYPTO_DATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_SHIFT 0 /**< Shift value for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1 */ +#define CRYPTO_DATA1_DATA1_DEFAULT (_CRYPTO_DATA1_DATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1 */ + +/* Bit fields for CRYPTO DATA2 */ +#define _CRYPTO_DATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_SHIFT 0 /**< Shift value for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA2 */ +#define CRYPTO_DATA2_DATA2_DEFAULT (_CRYPTO_DATA2_DATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA2 */ + +/* Bit fields for CRYPTO DATA3 */ +#define _CRYPTO_DATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_SHIFT 0 /**< Shift value for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA3 */ +#define CRYPTO_DATA3_DATA3_DEFAULT (_CRYPTO_DATA3_DATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA3 */ + +/* Bit fields for CRYPTO DATA0XOR */ +#define _CRYPTO_DATA0XOR_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_SHIFT 0 /**< Shift value for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XOR */ +#define CRYPTO_DATA0XOR_DATA0XOR_DEFAULT (_CRYPTO_DATA0XOR_DATA0XOR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XOR */ + +/* Bit fields for CRYPTO DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE */ +#define CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT (_CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE */ + +/* Bit fields for CRYPTO DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1BYTE */ +#define CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT (_CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1BYTE */ + +/* Bit fields for CRYPTO DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XORBYTE */ +#define CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT (_CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XORBYTE */ + +/* Bit fields for CRYPTO DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE12 */ +#define CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT (_CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE12 */ + +/* Bit fields for CRYPTO DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE13 */ +#define CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT (_CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE13 */ + +/* Bit fields for CRYPTO DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE14 */ +#define CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT (_CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE14 */ + +/* Bit fields for CRYPTO DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE15 */ +#define CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT (_CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE15 */ + +/* Bit fields for CRYPTO DDATA0 */ +#define _CRYPTO_DDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_SHIFT 0 /**< Shift value for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0 */ +#define CRYPTO_DDATA0_DDATA0_DEFAULT (_CRYPTO_DDATA0_DDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0 */ + +/* Bit fields for CRYPTO DDATA1 */ +#define _CRYPTO_DDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_SHIFT 0 /**< Shift value for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1 */ +#define CRYPTO_DDATA1_DDATA1_DEFAULT (_CRYPTO_DDATA1_DDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1 */ + +/* Bit fields for CRYPTO DDATA2 */ +#define _CRYPTO_DDATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_SHIFT 0 /**< Shift value for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA2 */ +#define CRYPTO_DDATA2_DDATA2_DEFAULT (_CRYPTO_DDATA2_DDATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA2 */ + +/* Bit fields for CRYPTO DDATA3 */ +#define _CRYPTO_DDATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_SHIFT 0 /**< Shift value for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA3 */ +#define CRYPTO_DDATA3_DDATA3_DEFAULT (_CRYPTO_DDATA3_DDATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA3 */ + +/* Bit fields for CRYPTO DDATA4 */ +#define _CRYPTO_DDATA4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_SHIFT 0 /**< Shift value for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA4 */ +#define CRYPTO_DDATA4_DDATA4_DEFAULT (_CRYPTO_DDATA4_DDATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA4 */ + +/* Bit fields for CRYPTO DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BIG */ +#define CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT (_CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BIG */ + +/* Bit fields for CRYPTO DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE */ +#define CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT (_CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE */ + +/* Bit fields for CRYPTO DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1BYTE */ +#define CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT (_CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1BYTE */ + +/* Bit fields for CRYPTO DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_MASK 0x0000000FUL /**< Mask for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK 0xFUL /**< Bit mask for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE32 */ +#define CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT (_CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE32 */ + +/* Bit fields for CRYPTO QDATA0 */ +#define _CRYPTO_QDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_SHIFT 0 /**< Shift value for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0 */ +#define CRYPTO_QDATA0_QDATA0_DEFAULT (_CRYPTO_QDATA0_QDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0 */ + +/* Bit fields for CRYPTO QDATA1 */ +#define _CRYPTO_QDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_SHIFT 0 /**< Shift value for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1 */ +#define CRYPTO_QDATA1_QDATA1_DEFAULT (_CRYPTO_QDATA1_QDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1 */ + +/* Bit fields for CRYPTO QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BIG */ +#define CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT (_CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BIG */ + +/* Bit fields for CRYPTO QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0BYTE */ +#define CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT (_CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0BYTE */ + +/* Bit fields for CRYPTO QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */ +#define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */ + +/** @} */ +/** @} End of group EFM32GG11B_CRYPTO */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_csen.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_csen.h new file mode 100644 index 0000000000000..86c804192e6b3 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_csen.h @@ -0,0 +1,1010 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_CSEN register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_CSEN CSEN + * @{ + * @brief EFM32GG11B_CSEN Register Declaration + ******************************************************************************/ +/** CSEN Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t TIMCTRL; /**< Timing Control */ + __IOM uint32_t CMD; /**< Command */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t PRSSEL; /**< PRS Select */ + __IOM uint32_t DATA; /**< Output Data */ + __IOM uint32_t SCANMASK0; /**< Scan Channel Mask 0 */ + __IOM uint32_t SCANINPUTSEL0; /**< Scan Input Selection 0 */ + __IOM uint32_t SCANMASK1; /**< Scan Channel Mask 1 */ + __IOM uint32_t SCANINPUTSEL1; /**< Scan Input Selection 1 */ + __IM uint32_t APORTREQ; /**< APORT Request Status */ + __IM uint32_t APORTCONFLICT; /**< APORT Request Conflict */ + __IOM uint32_t CMPTHR; /**< Comparator Threshold */ + __IOM uint32_t EMA; /**< Exponential Moving Average */ + __IOM uint32_t EMACTRL; /**< Exponential Moving Average Control */ + __IOM uint32_t SINGLECTRL; /**< Single Conversion Control */ + __IOM uint32_t DMBASELINE; /**< Delta Modulation Baseline */ + __IOM uint32_t DMCFG; /**< Delta Modulation Configuration */ + __IOM uint32_t ANACTRL; /**< Analog Control */ + + uint32_t RESERVED0[2U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IFS; /**< Interrupt Flag Set */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear */ + __IOM uint32_t IEN; /**< Interrupt Enable */ +} CSEN_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_CSEN + * @{ + * @defgroup EFM32GG11B_CSEN_BitFields CSEN Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for CSEN CTRL */ +#define _CSEN_CTRL_RESETVALUE 0x00030000UL /**< Default value for CSEN_CTRL */ +#define _CSEN_CTRL_MASK 0x1FFFF336UL /**< Mask for CSEN_CTRL */ +#define CSEN_CTRL_EN (0x1UL << 1) /**< CSEN Enable */ +#define _CSEN_CTRL_EN_SHIFT 1 /**< Shift value for CSEN_EN */ +#define _CSEN_CTRL_EN_MASK 0x2UL /**< Bit mask for CSEN_EN */ +#define _CSEN_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_EN_DEFAULT (_CSEN_CTRL_EN_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_EN_DISABLE (_CSEN_CTRL_EN_DISABLE << 1) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_EN_ENABLE (_CSEN_CTRL_EN_ENABLE << 1) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL (0x1UL << 2) /**< CSEN Digital Comparator Polarity Select */ +#define _CSEN_CTRL_CMPPOL_SHIFT 2 /**< Shift value for CSEN_CMPPOL */ +#define _CSEN_CTRL_CMPPOL_MASK 0x4UL /**< Bit mask for CSEN_CMPPOL */ +#define _CSEN_CTRL_CMPPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPPOL_GT 0x00000000UL /**< Mode GT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPPOL_LTE 0x00000001UL /**< Mode LTE for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_DEFAULT (_CSEN_CTRL_CMPPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_GT (_CSEN_CTRL_CMPPOL_GT << 2) /**< Shifted mode GT for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_LTE (_CSEN_CTRL_CMPPOL_LTE << 2) /**< Shifted mode LTE for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SHIFT 4 /**< Shift value for CSEN_CM */ +#define _CSEN_CTRL_CM_MASK 0x30UL /**< Bit mask for CSEN_CM */ +#define _CSEN_CTRL_CM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SGL 0x00000000UL /**< Mode SGL for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SCAN 0x00000001UL /**< Mode SCAN for CSEN_CTRL */ +#define _CSEN_CTRL_CM_CONTSGL 0x00000002UL /**< Mode CONTSGL for CSEN_CTRL */ +#define _CSEN_CTRL_CM_CONTSCAN 0x00000003UL /**< Mode CONTSCAN for CSEN_CTRL */ +#define CSEN_CTRL_CM_DEFAULT (_CSEN_CTRL_CM_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CM_SGL (_CSEN_CTRL_CM_SGL << 4) /**< Shifted mode SGL for CSEN_CTRL */ +#define CSEN_CTRL_CM_SCAN (_CSEN_CTRL_CM_SCAN << 4) /**< Shifted mode SCAN for CSEN_CTRL */ +#define CSEN_CTRL_CM_CONTSGL (_CSEN_CTRL_CM_CONTSGL << 4) /**< Shifted mode CONTSGL for CSEN_CTRL */ +#define CSEN_CTRL_CM_CONTSCAN (_CSEN_CTRL_CM_CONTSCAN << 4) /**< Shifted mode CONTSCAN for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_SHIFT 8 /**< Shift value for CSEN_SARCR */ +#define _CSEN_CTRL_SARCR_MASK 0x300UL /**< Bit mask for CSEN_SARCR */ +#define _CSEN_CTRL_SARCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK10 0x00000000UL /**< Mode CLK10 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK12 0x00000001UL /**< Mode CLK12 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK14 0x00000002UL /**< Mode CLK14 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK16 0x00000003UL /**< Mode CLK16 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_DEFAULT (_CSEN_CTRL_SARCR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK10 (_CSEN_CTRL_SARCR_CLK10 << 8) /**< Shifted mode CLK10 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK12 (_CSEN_CTRL_SARCR_CLK12 << 8) /**< Shifted mode CLK12 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK14 (_CSEN_CTRL_SARCR_CLK14 << 8) /**< Shifted mode CLK14 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK16 (_CSEN_CTRL_SARCR_CLK16 << 8) /**< Shifted mode CLK16 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_SHIFT 12 /**< Shift value for CSEN_ACU */ +#define _CSEN_CTRL_ACU_MASK 0x7000UL /**< Bit mask for CSEN_ACU */ +#define _CSEN_CTRL_ACU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC1 0x00000000UL /**< Mode ACC1 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC2 0x00000001UL /**< Mode ACC2 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC4 0x00000002UL /**< Mode ACC4 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC8 0x00000003UL /**< Mode ACC8 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC16 0x00000004UL /**< Mode ACC16 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC32 0x00000005UL /**< Mode ACC32 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC64 0x00000006UL /**< Mode ACC64 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_DEFAULT (_CSEN_CTRL_ACU_DEFAULT << 12) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC1 (_CSEN_CTRL_ACU_ACC1 << 12) /**< Shifted mode ACC1 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC2 (_CSEN_CTRL_ACU_ACC2 << 12) /**< Shifted mode ACC2 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC4 (_CSEN_CTRL_ACU_ACC4 << 12) /**< Shifted mode ACC4 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC8 (_CSEN_CTRL_ACU_ACC8 << 12) /**< Shifted mode ACC8 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC16 (_CSEN_CTRL_ACU_ACC16 << 12) /**< Shifted mode ACC16 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC32 (_CSEN_CTRL_ACU_ACC32 << 12) /**< Shifted mode ACC32 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC64 (_CSEN_CTRL_ACU_ACC64 << 12) /**< Shifted mode ACC64 for CSEN_CTRL */ +#define CSEN_CTRL_MCEN (0x1UL << 15) /**< CSEN Multiple Channel Enable */ +#define _CSEN_CTRL_MCEN_SHIFT 15 /**< Shift value for CSEN_MCEN */ +#define _CSEN_CTRL_MCEN_MASK 0x8000UL /**< Bit mask for CSEN_MCEN */ +#define _CSEN_CTRL_MCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_MCEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_MCEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_DEFAULT (_CSEN_CTRL_MCEN_DEFAULT << 15) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_DISABLE (_CSEN_CTRL_MCEN_DISABLE << 15) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_ENABLE (_CSEN_CTRL_MCEN_ENABLE << 15) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define _CSEN_CTRL_STM_SHIFT 16 /**< Shift value for CSEN_STM */ +#define _CSEN_CTRL_STM_MASK 0x30000UL /**< Bit mask for CSEN_STM */ +#define _CSEN_CTRL_STM_PRS 0x00000000UL /**< Mode PRS for CSEN_CTRL */ +#define _CSEN_CTRL_STM_TIMER 0x00000001UL /**< Mode TIMER for CSEN_CTRL */ +#define _CSEN_CTRL_STM_START 0x00000002UL /**< Mode START for CSEN_CTRL */ +#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_STM_PRS (_CSEN_CTRL_STM_PRS << 16) /**< Shifted mode PRS for CSEN_CTRL */ +#define CSEN_CTRL_STM_TIMER (_CSEN_CTRL_STM_TIMER << 16) /**< Shifted mode TIMER for CSEN_CTRL */ +#define CSEN_CTRL_STM_START (_CSEN_CTRL_STM_START << 16) /**< Shifted mode START for CSEN_CTRL */ +#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN (0x1UL << 18) /**< CSEN Digital Comparator Enable */ +#define _CSEN_CTRL_CMPEN_SHIFT 18 /**< Shift value for CSEN_CMPEN */ +#define _CSEN_CTRL_CMPEN_MASK 0x40000UL /**< Bit mask for CSEN_CMPEN */ +#define _CSEN_CTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_CMPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_DEFAULT (_CSEN_CTRL_CMPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_DISABLE (_CSEN_CTRL_CMPEN_DISABLE << 18) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_ENABLE (_CSEN_CTRL_CMPEN_ENABLE << 18) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF (0x1UL << 19) /**< CSEN Disable Right-Shift */ +#define _CSEN_CTRL_DRSF_SHIFT 19 /**< Shift value for CSEN_DRSF */ +#define _CSEN_CTRL_DRSF_MASK 0x80000UL /**< Bit mask for CSEN_DRSF */ +#define _CSEN_CTRL_DRSF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_DRSF_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_DRSF_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_DEFAULT (_CSEN_CTRL_DRSF_DEFAULT << 19) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_DISABLE (_CSEN_CTRL_DRSF_DISABLE << 19) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_ENABLE (_CSEN_CTRL_DRSF_ENABLE << 19) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN (0x1UL << 20) /**< CSEN DMA Enable Bit */ +#define _CSEN_CTRL_DMAEN_SHIFT 20 /**< Shift value for CSEN_DMAEN */ +#define _CSEN_CTRL_DMAEN_MASK 0x100000UL /**< Bit mask for CSEN_DMAEN */ +#define _CSEN_CTRL_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_DEFAULT (_CSEN_CTRL_DMAEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_DISABLE (_CSEN_CTRL_DMAEN_DISABLE << 20) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_ENABLE (_CSEN_CTRL_DMAEN_ENABLE << 20) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL (0x1UL << 21) /**< CSEN Converter Select */ +#define _CSEN_CTRL_CONVSEL_SHIFT 21 /**< Shift value for CSEN_CONVSEL */ +#define _CSEN_CTRL_CONVSEL_MASK 0x200000UL /**< Bit mask for CSEN_CONVSEL */ +#define _CSEN_CTRL_CONVSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CONVSEL_SAR 0x00000000UL /**< Mode SAR for CSEN_CTRL */ +#define _CSEN_CTRL_CONVSEL_DM 0x00000001UL /**< Mode DM for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_DEFAULT (_CSEN_CTRL_CONVSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_SAR (_CSEN_CTRL_CONVSEL_SAR << 21) /**< Shifted mode SAR for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_DM (_CSEN_CTRL_CONVSEL_DM << 21) /**< Shifted mode DM for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN (0x1UL << 22) /**< CSEN Chop Enable */ +#define _CSEN_CTRL_CHOPEN_SHIFT 22 /**< Shift value for CSEN_CHOPEN */ +#define _CSEN_CTRL_CHOPEN_MASK 0x400000UL /**< Bit mask for CSEN_CHOPEN */ +#define _CSEN_CTRL_CHOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CHOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_CHOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_DEFAULT (_CSEN_CTRL_CHOPEN_DEFAULT << 22) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_DISABLE (_CSEN_CTRL_CHOPEN_DISABLE << 22) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_ENABLE (_CSEN_CTRL_CHOPEN_ENABLE << 22) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND (0x1UL << 23) /**< CSEN Automatic Ground Enable */ +#define _CSEN_CTRL_AUTOGND_SHIFT 23 /**< Shift value for CSEN_AUTOGND */ +#define _CSEN_CTRL_AUTOGND_MASK 0x800000UL /**< Bit mask for CSEN_AUTOGND */ +#define _CSEN_CTRL_AUTOGND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_AUTOGND_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_AUTOGND_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_DEFAULT (_CSEN_CTRL_AUTOGND_DEFAULT << 23) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_DISABLE (_CSEN_CTRL_AUTOGND_DISABLE << 23) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_ENABLE (_CSEN_CTRL_AUTOGND_ENABLE << 23) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_MXUC (0x1UL << 24) /**< CSEN Mux Disconnect */ +#define _CSEN_CTRL_MXUC_SHIFT 24 /**< Shift value for CSEN_MXUC */ +#define _CSEN_CTRL_MXUC_MASK 0x1000000UL /**< Bit mask for CSEN_MXUC */ +#define _CSEN_CTRL_MXUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_MXUC_CONN 0x00000000UL /**< Mode CONN for CSEN_CTRL */ +#define _CSEN_CTRL_MXUC_UNC 0x00000001UL /**< Mode UNC for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_DEFAULT (_CSEN_CTRL_MXUC_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_CONN (_CSEN_CTRL_MXUC_CONN << 24) /**< Shifted mode CONN for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_UNC (_CSEN_CTRL_MXUC_UNC << 24) /**< Shifted mode UNC for CSEN_CTRL */ +#define CSEN_CTRL_EMACMPEN (0x1UL << 25) /**< Greater and Less Than Comparison Using the Exponential Moving Average (EMA) is Enabled */ +#define _CSEN_CTRL_EMACMPEN_SHIFT 25 /**< Shift value for CSEN_EMACMPEN */ +#define _CSEN_CTRL_EMACMPEN_MASK 0x2000000UL /**< Bit mask for CSEN_EMACMPEN */ +#define _CSEN_CTRL_EMACMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_EMACMPEN_DEFAULT (_CSEN_CTRL_EMACMPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE (0x1UL << 26) /**< Select Warmup Mode for CSEN */ +#define _CSEN_CTRL_WARMUPMODE_SHIFT 26 /**< Shift value for CSEN_WARMUPMODE */ +#define _CSEN_CTRL_WARMUPMODE_MASK 0x4000000UL /**< Bit mask for CSEN_WARMUPMODE */ +#define _CSEN_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for CSEN_CTRL */ +#define _CSEN_CTRL_WARMUPMODE_KEEPCSENWARM 0x00000001UL /**< Mode KEEPCSENWARM for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_DEFAULT (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_NORMAL (_CSEN_CTRL_WARMUPMODE_NORMAL << 26) /**< Shifted mode NORMAL for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */ +#define CSEN_CTRL_LOCALSENS (0x1UL << 27) /**< Local Sensing Enable */ +#define _CSEN_CTRL_LOCALSENS_SHIFT 27 /**< Shift value for CSEN_LOCALSENS */ +#define _CSEN_CTRL_LOCALSENS_MASK 0x8000000UL /**< Bit mask for CSEN_LOCALSENS */ +#define _CSEN_CTRL_LOCALSENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_LOCALSENS_DEFAULT (_CSEN_CTRL_LOCALSENS_DEFAULT << 27) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY (0x1UL << 28) /**< Charge Pump Accuracy */ +#define _CSEN_CTRL_CPACCURACY_SHIFT 28 /**< Shift value for CSEN_CPACCURACY */ +#define _CSEN_CTRL_CPACCURACY_MASK 0x10000000UL /**< Bit mask for CSEN_CPACCURACY */ +#define _CSEN_CTRL_CPACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CPACCURACY_LO 0x00000000UL /**< Mode LO for CSEN_CTRL */ +#define _CSEN_CTRL_CPACCURACY_HI 0x00000001UL /**< Mode HI for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_DEFAULT (_CSEN_CTRL_CPACCURACY_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_LO (_CSEN_CTRL_CPACCURACY_LO << 28) /**< Shifted mode LO for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_HI (_CSEN_CTRL_CPACCURACY_HI << 28) /**< Shifted mode HI for CSEN_CTRL */ + +/* Bit fields for CSEN TIMCTRL */ +#define _CSEN_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_MASK 0x0003FF07UL /**< Mask for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_SHIFT 0 /**< Shift value for CSEN_PCPRESC */ +#define _CSEN_TIMCTRL_PCPRESC_MASK 0x7UL /**< Bit mask for CSEN_PCPRESC */ +#define _CSEN_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DEFAULT (_CSEN_TIMCTRL_PCPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV1 (_CSEN_TIMCTRL_PCPRESC_DIV1 << 0) /**< Shifted mode DIV1 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV2 (_CSEN_TIMCTRL_PCPRESC_DIV2 << 0) /**< Shifted mode DIV2 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV4 (_CSEN_TIMCTRL_PCPRESC_DIV4 << 0) /**< Shifted mode DIV4 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV8 (_CSEN_TIMCTRL_PCPRESC_DIV8 << 0) /**< Shifted mode DIV8 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV16 (_CSEN_TIMCTRL_PCPRESC_DIV16 << 0) /**< Shifted mode DIV16 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV32 (_CSEN_TIMCTRL_PCPRESC_DIV32 << 0) /**< Shifted mode DIV32 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) /**< Shifted mode DIV64 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV128 (_CSEN_TIMCTRL_PCPRESC_DIV128 << 0) /**< Shifted mode DIV128 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCTOP_SHIFT 8 /**< Shift value for CSEN_PCTOP */ +#define _CSEN_TIMCTRL_PCTOP_MASK 0xFF00UL /**< Bit mask for CSEN_PCTOP */ +#define _CSEN_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCTOP_DEFAULT (_CSEN_TIMCTRL_PCTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_WARMUPCNT_SHIFT 16 /**< Shift value for CSEN_WARMUPCNT */ +#define _CSEN_TIMCTRL_WARMUPCNT_MASK 0x30000UL /**< Bit mask for CSEN_WARMUPCNT */ +#define _CSEN_TIMCTRL_WARMUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_WARMUPCNT_DEFAULT (_CSEN_TIMCTRL_WARMUPCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ + +/* Bit fields for CSEN CMD */ +#define _CSEN_CMD_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMD */ +#define _CSEN_CMD_MASK 0x00000001UL /**< Mask for CSEN_CMD */ +#define CSEN_CMD_START (0x1UL << 0) /**< Start Software-Triggered Conversions */ +#define _CSEN_CMD_START_SHIFT 0 /**< Shift value for CSEN_START */ +#define _CSEN_CMD_START_MASK 0x1UL /**< Bit mask for CSEN_START */ +#define _CSEN_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMD */ +#define CSEN_CMD_START_DEFAULT (_CSEN_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMD */ + +/* Bit fields for CSEN STATUS */ +#define _CSEN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CSEN_STATUS */ +#define _CSEN_STATUS_MASK 0x00000001UL /**< Mask for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY (0x1UL << 0) /**< Busy Flag */ +#define _CSEN_STATUS_CSENBUSY_SHIFT 0 /**< Shift value for CSEN_CSENBUSY */ +#define _CSEN_STATUS_CSENBUSY_MASK 0x1UL /**< Bit mask for CSEN_CSENBUSY */ +#define _CSEN_STATUS_CSENBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_STATUS */ +#define _CSEN_STATUS_CSENBUSY_IDLE 0x00000000UL /**< Mode IDLE for CSEN_STATUS */ +#define _CSEN_STATUS_CSENBUSY_BUSY 0x00000001UL /**< Mode BUSY for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_DEFAULT (_CSEN_STATUS_CSENBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_IDLE (_CSEN_STATUS_CSENBUSY_IDLE << 0) /**< Shifted mode IDLE for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_BUSY (_CSEN_STATUS_CSENBUSY_BUSY << 0) /**< Shifted mode BUSY for CSEN_STATUS */ + +/* Bit fields for CSEN PRSSEL */ +#define _CSEN_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_MASK 0x0000001FUL /**< Mask for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_SHIFT 0 /**< Shift value for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_MASK 0x1FUL /**< Bit mask for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_DEFAULT (_CSEN_PRSSEL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH0 (_CSEN_PRSSEL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH1 (_CSEN_PRSSEL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH2 (_CSEN_PRSSEL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH3 (_CSEN_PRSSEL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH4 (_CSEN_PRSSEL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH5 (_CSEN_PRSSEL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH6 (_CSEN_PRSSEL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH7 (_CSEN_PRSSEL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH8 (_CSEN_PRSSEL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH9 (_CSEN_PRSSEL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH10 (_CSEN_PRSSEL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH11 (_CSEN_PRSSEL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH12 (_CSEN_PRSSEL_PRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH13 (_CSEN_PRSSEL_PRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH14 (_CSEN_PRSSEL_PRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH15 (_CSEN_PRSSEL_PRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH16 (_CSEN_PRSSEL_PRSSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH17 (_CSEN_PRSSEL_PRSSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH18 (_CSEN_PRSSEL_PRSSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH19 (_CSEN_PRSSEL_PRSSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH20 (_CSEN_PRSSEL_PRSSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH21 (_CSEN_PRSSEL_PRSSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH22 (_CSEN_PRSSEL_PRSSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH23 (_CSEN_PRSSEL_PRSSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for CSEN_PRSSEL */ + +/* Bit fields for CSEN DATA */ +#define _CSEN_DATA_RESETVALUE 0x00000000UL /**< Default value for CSEN_DATA */ +#define _CSEN_DATA_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DATA */ +#define _CSEN_DATA_DATA_SHIFT 0 /**< Shift value for CSEN_DATA */ +#define _CSEN_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_DATA */ +#define _CSEN_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DATA */ +#define CSEN_DATA_DATA_DEFAULT (_CSEN_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DATA */ + +/* Bit fields for CSEN SCANMASK0 */ +#define _CSEN_SCANMASK0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK0 */ +#define _CSEN_SCANMASK0_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK0 */ +#define _CSEN_SCANMASK0_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK0_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK0_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK0 */ +#define CSEN_SCANMASK0_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK0_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK0 */ + +/* Bit fields for CSEN SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT 0 /**< Shift value for CSEN_INPUT0TO7SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT0TO7SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT 8 /**< Shift value for CSEN_INPUT8TO15SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT8TO15SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT 16 /**< Shift value for CSEN_INPUT16TO23SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT16TO23SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT 24 /**< Shift value for CSEN_INPUT24TO31SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT24TO31SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ + +/* Bit fields for CSEN SCANMASK1 */ +#define _CSEN_SCANMASK1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK1 */ +#define _CSEN_SCANMASK1_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK1 */ +#define _CSEN_SCANMASK1_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK1_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK1_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK1 */ +#define CSEN_SCANMASK1_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK1_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK1 */ + +/* Bit fields for CSEN SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT 0 /**< Shift value for CSEN_INPUT32TO39SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT32TO39SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT 8 /**< Shift value for CSEN_INPUT40TO47SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT40TO47SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT 16 /**< Shift value for CSEN_INPUT48TO55SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT48TO55SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT 24 /**< Shift value for CSEN_INPUT56TO63SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT56TO63SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ + +/* Bit fields for CSEN APORTREQ */ +#define _CSEN_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTREQ */ +#define _CSEN_APORTREQ_MASK 0x000003FCUL /**< Mask for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */ +#define _CSEN_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for CSEN_APORT1XREQ */ +#define _CSEN_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for CSEN_APORT1XREQ */ +#define _CSEN_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1XREQ_DEFAULT (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */ +#define _CSEN_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for CSEN_APORT1YREQ */ +#define _CSEN_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for CSEN_APORT1YREQ */ +#define _CSEN_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1YREQ_DEFAULT (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */ +#define _CSEN_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for CSEN_APORT2XREQ */ +#define _CSEN_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for CSEN_APORT2XREQ */ +#define _CSEN_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2XREQ_DEFAULT (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */ +#define _CSEN_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for CSEN_APORT2YREQ */ +#define _CSEN_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for CSEN_APORT2YREQ */ +#define _CSEN_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2YREQ_DEFAULT (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */ +#define _CSEN_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for CSEN_APORT3XREQ */ +#define _CSEN_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for CSEN_APORT3XREQ */ +#define _CSEN_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3XREQ_DEFAULT (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */ +#define _CSEN_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for CSEN_APORT3YREQ */ +#define _CSEN_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for CSEN_APORT3YREQ */ +#define _CSEN_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3YREQ_DEFAULT (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */ +#define _CSEN_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for CSEN_APORT4XREQ */ +#define _CSEN_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for CSEN_APORT4XREQ */ +#define _CSEN_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4XREQ_DEFAULT (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */ +#define _CSEN_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for CSEN_APORT4YREQ */ +#define _CSEN_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for CSEN_APORT4YREQ */ +#define _CSEN_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4YREQ_DEFAULT (_CSEN_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ + +/* Bit fields for CSEN APORTCONFLICT */ +#define _CSEN_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTCONFLICT */ +#define _CSEN_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for CSEN_APORT1XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for CSEN_APORT1XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for CSEN_APORT1YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for CSEN_APORT1YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORT2XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORT2XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for CSEN_APORT2YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for CSEN_APORT2YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for CSEN_APORT3XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for CSEN_APORT3XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for CSEN_APORT3YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for CSEN_APORT3YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for CSEN_APORT4XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for CSEN_APORT4XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for CSEN_APORT4YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for CSEN_APORT4YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ + +/* Bit fields for CSEN CMPTHR */ +#define _CSEN_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_MASK 0x0000FFFFUL /**< Mask for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_SHIFT 0 /**< Shift value for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_MASK 0xFFFFUL /**< Bit mask for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMPTHR */ +#define CSEN_CMPTHR_CMPTHR_DEFAULT (_CSEN_CMPTHR_CMPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMPTHR */ + +/* Bit fields for CSEN EMA */ +#define _CSEN_EMA_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMA */ +#define _CSEN_EMA_MASK 0x003FFFFFUL /**< Mask for CSEN_EMA */ +#define _CSEN_EMA_EMA_SHIFT 0 /**< Shift value for CSEN_EMA */ +#define _CSEN_EMA_EMA_MASK 0x3FFFFFUL /**< Bit mask for CSEN_EMA */ +#define _CSEN_EMA_EMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMA */ +#define CSEN_EMA_EMA_DEFAULT (_CSEN_EMA_EMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMA */ + +/* Bit fields for CSEN EMACTRL */ +#define _CSEN_EMACTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_MASK 0x00000007UL /**< Mask for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_SHIFT 0 /**< Shift value for CSEN_EMASAMPLE */ +#define _CSEN_EMACTRL_EMASAMPLE_MASK 0x7UL /**< Bit mask for CSEN_EMASAMPLE */ +#define _CSEN_EMACTRL_EMASAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W1 0x00000000UL /**< Mode W1 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W2 0x00000001UL /**< Mode W2 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W4 0x00000002UL /**< Mode W4 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W8 0x00000003UL /**< Mode W8 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W16 0x00000004UL /**< Mode W16 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W32 0x00000005UL /**< Mode W32 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W64 0x00000006UL /**< Mode W64 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_DEFAULT (_CSEN_EMACTRL_EMASAMPLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W1 (_CSEN_EMACTRL_EMASAMPLE_W1 << 0) /**< Shifted mode W1 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W2 (_CSEN_EMACTRL_EMASAMPLE_W2 << 0) /**< Shifted mode W2 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W4 (_CSEN_EMACTRL_EMASAMPLE_W4 << 0) /**< Shifted mode W4 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W8 (_CSEN_EMACTRL_EMASAMPLE_W8 << 0) /**< Shifted mode W8 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W16 (_CSEN_EMACTRL_EMASAMPLE_W16 << 0) /**< Shifted mode W16 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W32 (_CSEN_EMACTRL_EMASAMPLE_W32 << 0) /**< Shifted mode W32 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W64 (_CSEN_EMACTRL_EMASAMPLE_W64 << 0) /**< Shifted mode W64 for CSEN_EMACTRL */ + +/* Bit fields for CSEN SINGLECTRL */ +#define _CSEN_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_MASK 0x000007F0UL /**< Mask for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_SHIFT 4 /**< Shift value for CSEN_SINGLESEL */ +#define _CSEN_SINGLECTRL_SINGLESEL_MASK 0x7F0UL /**< Bit mask for CSEN_SINGLESEL */ +#define _CSEN_SINGLECTRL_SINGLESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_DEFAULT (_CSEN_SINGLECTRL_SINGLESEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 << 4) /**< Shifted mode APORT3XCH0 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 << 4) /**< Shifted mode APORT3YCH1 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 << 4) /**< Shifted mode APORT3XCH2 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 << 4) /**< Shifted mode APORT3YCH3 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 << 4) /**< Shifted mode APORT3XCH4 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 << 4) /**< Shifted mode APORT3YCH5 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 << 4) /**< Shifted mode APORT3XCH6 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 << 4) /**< Shifted mode APORT3YCH7 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 << 4) /**< Shifted mode APORT3XCH8 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 << 4) /**< Shifted mode APORT3YCH9 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 << 4) /**< Shifted mode APORT3XCH10 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 << 4) /**< Shifted mode APORT3YCH11 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 << 4) /**< Shifted mode APORT3XCH12 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 << 4) /**< Shifted mode APORT3YCH13 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 << 4) /**< Shifted mode APORT3XCH14 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 << 4) /**< Shifted mode APORT3YCH15 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 << 4) /**< Shifted mode APORT3XCH16 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 << 4) /**< Shifted mode APORT3YCH17 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 << 4) /**< Shifted mode APORT3XCH18 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 << 4) /**< Shifted mode APORT3YCH19 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 << 4) /**< Shifted mode APORT3XCH20 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 << 4) /**< Shifted mode APORT3YCH21 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 << 4) /**< Shifted mode APORT3XCH22 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 << 4) /**< Shifted mode APORT3YCH23 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 << 4) /**< Shifted mode APORT3XCH24 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 << 4) /**< Shifted mode APORT3YCH25 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 << 4) /**< Shifted mode APORT3XCH26 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 << 4) /**< Shifted mode APORT3YCH27 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 << 4) /**< Shifted mode APORT3XCH28 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 << 4) /**< Shifted mode APORT3YCH29 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 << 4) /**< Shifted mode APORT3XCH30 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 << 4) /**< Shifted mode APORT3YCH31 for CSEN_SINGLECTRL */ + +/* Bit fields for CSEN DMBASELINE */ +#define _CSEN_DMBASELINE_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_BASELINEUP_SHIFT 0 /**< Shift value for CSEN_BASELINEUP */ +#define _CSEN_DMBASELINE_BASELINEUP_MASK 0xFFFFUL /**< Bit mask for CSEN_BASELINEUP */ +#define _CSEN_DMBASELINE_BASELINEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ +#define CSEN_DMBASELINE_BASELINEUP_DEFAULT (_CSEN_DMBASELINE_BASELINEUP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_BASELINEDN_SHIFT 16 /**< Shift value for CSEN_BASELINEDN */ +#define _CSEN_DMBASELINE_BASELINEDN_MASK 0xFFFF0000UL /**< Bit mask for CSEN_BASELINEDN */ +#define _CSEN_DMBASELINE_BASELINEDN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ +#define CSEN_DMBASELINE_BASELINEDN_DEFAULT (_CSEN_DMBASELINE_BASELINEDN_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ + +/* Bit fields for CSEN DMCFG */ +#define _CSEN_DMCFG_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMCFG */ +#define _CSEN_DMCFG_MASK 0x103F0FFFUL /**< Mask for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMG_SHIFT 0 /**< Shift value for CSEN_DMG */ +#define _CSEN_DMCFG_DMG_MASK 0xFFUL /**< Bit mask for CSEN_DMG */ +#define _CSEN_DMCFG_DMG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMG_DEFAULT (_CSEN_DMCFG_DMG_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMR_SHIFT 8 /**< Shift value for CSEN_DMR */ +#define _CSEN_DMCFG_DMR_MASK 0xF00UL /**< Bit mask for CSEN_DMR */ +#define _CSEN_DMCFG_DMR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMR_DEFAULT (_CSEN_DMCFG_DMR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMCR_SHIFT 16 /**< Shift value for CSEN_DMCR */ +#define _CSEN_DMCFG_DMCR_MASK 0xF0000UL /**< Bit mask for CSEN_DMCR */ +#define _CSEN_DMCFG_DMCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMCR_DEFAULT (_CSEN_DMCFG_DMCR_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_SHIFT 20 /**< Shift value for CSEN_CRMODE */ +#define _CSEN_DMCFG_CRMODE_MASK 0x300000UL /**< Bit mask for CSEN_CRMODE */ +#define _CSEN_DMCFG_CRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM10 0x00000000UL /**< Mode DM10 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM12 0x00000001UL /**< Mode DM12 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM14 0x00000002UL /**< Mode DM14 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM16 0x00000003UL /**< Mode DM16 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DEFAULT (_CSEN_DMCFG_CRMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM10 (_CSEN_DMCFG_CRMODE_DM10 << 20) /**< Shifted mode DM10 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM12 (_CSEN_DMCFG_CRMODE_DM12 << 20) /**< Shifted mode DM12 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM14 (_CSEN_DMCFG_CRMODE_DM14 << 20) /**< Shifted mode DM14 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM16 (_CSEN_DMCFG_CRMODE_DM16 << 20) /**< Shifted mode DM16 for CSEN_DMCFG */ +#define CSEN_DMCFG_DMGRDIS (0x1UL << 28) /**< Delta Modulation Gain Step Reduction Disable */ +#define _CSEN_DMCFG_DMGRDIS_SHIFT 28 /**< Shift value for CSEN_DMGRDIS */ +#define _CSEN_DMCFG_DMGRDIS_MASK 0x10000000UL /**< Bit mask for CSEN_DMGRDIS */ +#define _CSEN_DMCFG_DMGRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMGRDIS_DEFAULT (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */ + +/* Bit fields for CSEN ANACTRL */ +#define _CSEN_ANACTRL_RESETVALUE 0x00000070UL /**< Default value for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_MASK 0x00700770UL /**< Mask for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_IREFPROG_SHIFT 4 /**< Shift value for CSEN_IREFPROG */ +#define _CSEN_ANACTRL_IREFPROG_MASK 0x70UL /**< Bit mask for CSEN_IREFPROG */ +#define _CSEN_ANACTRL_IREFPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_IREFPROG_DEFAULT (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_IDACIREFS_SHIFT 8 /**< Shift value for CSEN_IDACIREFS */ +#define _CSEN_ANACTRL_IDACIREFS_MASK 0x700UL /**< Bit mask for CSEN_IDACIREFS */ +#define _CSEN_ANACTRL_IDACIREFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_IDACIREFS_DEFAULT (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_TRSTPROG_SHIFT 20 /**< Shift value for CSEN_TRSTPROG */ +#define _CSEN_ANACTRL_TRSTPROG_MASK 0x700000UL /**< Bit mask for CSEN_TRSTPROG */ +#define _CSEN_ANACTRL_TRSTPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_TRSTPROG_DEFAULT (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ + +/* Bit fields for CSEN IF */ +#define _CSEN_IF_RESETVALUE 0x00000000UL /**< Default value for CSEN_IF */ +#define _CSEN_IF_MASK 0x0000001FUL /**< Mask for CSEN_IF */ +#define CSEN_IF_CMP (0x1UL << 0) /**< Digital Comparator Interrupt Flag */ +#define _CSEN_IF_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IF_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IF_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CMP_DEFAULT (_CSEN_IF_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CONV (0x1UL << 1) /**< Conversion Done Interrupt Flag */ +#define _CSEN_IF_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IF_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IF_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CONV_DEFAULT (_CSEN_IF_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_EOS (0x1UL << 2) /**< End of Scan Interrupt Flag. */ +#define _CSEN_IF_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IF_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IF_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_EOS_DEFAULT (_CSEN_IF_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_DMAOF (0x1UL << 3) /**< DMA Overflow Interrupt Flag. */ +#define _CSEN_IF_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IF_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IF_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_DMAOF_DEFAULT (_CSEN_IF_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_APORTCONFLICT (0x1UL << 4) /**< APORT Conflict Interrupt Flag */ +#define _CSEN_IF_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IF_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_APORTCONFLICT_DEFAULT (_CSEN_IF_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IF */ + +/* Bit fields for CSEN IFS */ +#define _CSEN_IFS_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFS */ +#define _CSEN_IFS_MASK 0x0000001FUL /**< Mask for CSEN_IFS */ +#define CSEN_IFS_CMP (0x1UL << 0) /**< Set CMP Interrupt Flag */ +#define _CSEN_IFS_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IFS_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IFS_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CMP_DEFAULT (_CSEN_IFS_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CONV (0x1UL << 1) /**< Set CONV Interrupt Flag */ +#define _CSEN_IFS_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IFS_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IFS_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CONV_DEFAULT (_CSEN_IFS_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_EOS (0x1UL << 2) /**< Set EOS Interrupt Flag */ +#define _CSEN_IFS_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IFS_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IFS_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_EOS_DEFAULT (_CSEN_IFS_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_DMAOF (0x1UL << 3) /**< Set DMAOF Interrupt Flag */ +#define _CSEN_IFS_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IFS_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IFS_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_DMAOF_DEFAULT (_CSEN_IFS_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_APORTCONFLICT (0x1UL << 4) /**< Set APORTCONFLICT Interrupt Flag */ +#define _CSEN_IFS_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IFS_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_APORTCONFLICT_DEFAULT (_CSEN_IFS_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFS */ + +/* Bit fields for CSEN IFC */ +#define _CSEN_IFC_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFC */ +#define _CSEN_IFC_MASK 0x0000001FUL /**< Mask for CSEN_IFC */ +#define CSEN_IFC_CMP (0x1UL << 0) /**< Clear CMP Interrupt Flag */ +#define _CSEN_IFC_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IFC_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IFC_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CMP_DEFAULT (_CSEN_IFC_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CONV (0x1UL << 1) /**< Clear CONV Interrupt Flag */ +#define _CSEN_IFC_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IFC_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IFC_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CONV_DEFAULT (_CSEN_IFC_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_EOS (0x1UL << 2) /**< Clear EOS Interrupt Flag */ +#define _CSEN_IFC_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IFC_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IFC_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_EOS_DEFAULT (_CSEN_IFC_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_DMAOF (0x1UL << 3) /**< Clear DMAOF Interrupt Flag */ +#define _CSEN_IFC_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IFC_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IFC_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_DMAOF_DEFAULT (_CSEN_IFC_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_APORTCONFLICT (0x1UL << 4) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _CSEN_IFC_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IFC_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_APORTCONFLICT_DEFAULT (_CSEN_IFC_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFC */ + +/* Bit fields for CSEN IEN */ +#define _CSEN_IEN_RESETVALUE 0x00000000UL /**< Default value for CSEN_IEN */ +#define _CSEN_IEN_MASK 0x0000001FUL /**< Mask for CSEN_IEN */ +#define CSEN_IEN_CMP (0x1UL << 0) /**< CMP Interrupt Enable */ +#define _CSEN_IEN_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IEN_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IEN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CMP_DEFAULT (_CSEN_IEN_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CONV (0x1UL << 1) /**< CONV Interrupt Enable */ +#define _CSEN_IEN_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IEN_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IEN_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CONV_DEFAULT (_CSEN_IEN_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_EOS (0x1UL << 2) /**< EOS Interrupt Enable */ +#define _CSEN_IEN_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IEN_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IEN_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_EOS_DEFAULT (_CSEN_IEN_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_DMAOF (0x1UL << 3) /**< DMAOF Interrupt Enable */ +#define _CSEN_IEN_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IEN_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IEN_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_DMAOF_DEFAULT (_CSEN_IEN_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_APORTCONFLICT (0x1UL << 4) /**< APORTCONFLICT Interrupt Enable */ +#define _CSEN_IEN_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IEN_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_APORTCONFLICT_DEFAULT (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */ + +/** @} */ +/** @} End of group EFM32GG11B_CSEN */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_devinfo.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_devinfo.h new file mode 100644 index 0000000000000..2c77bedfd872a --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_devinfo.h @@ -0,0 +1,1798 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_DEVINFO register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_DEVINFO Device Information and Calibration + * @{ + ******************************************************************************/ + +/** DEVINFO Register Declaration */ +typedef struct { + __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */ + __IM uint32_t MODULEINFO; /**< Module trace information */ + __IM uint32_t MODXOCAL; /**< Module Crystal Oscillator Calibration */ + uint32_t RESERVED0[5U]; /**< Reserved for future use **/ + __IM uint32_t EXTINFO; /**< External Component description */ + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */ + __IM uint32_t EUI48H; /**< OUI */ + __IM uint32_t CUSTOMINFO; /**< Custom information */ + __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */ + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */ + __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */ + __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */ + __IM uint32_t PART; /**< Part description */ + __IM uint32_t DEVINFOREV; /**< Device information page revision */ + __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */ + uint32_t RESERVED3[2U]; /**< Reserved for future use **/ + __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */ + __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */ + __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */ + __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */ + __IM uint32_t ADC1CAL0; /**< ADC1 calibration register 0 */ + __IM uint32_t ADC1CAL1; /**< ADC1 calibration register 1 */ + __IM uint32_t ADC1CAL2; /**< ADC1 calibration register 2 */ + __IM uint32_t ADC1CAL3; /**< ADC1 calibration register 3 */ + __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */ + uint32_t RESERVED4[2U]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */ + uint32_t RESERVED5[2U]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */ + __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */ + __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */ + uint32_t RESERVED6[1U]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */ + __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */ + __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */ + __IM uint32_t HFRCOCAL13; /**< HFRCO Calibration Register (48 MHz) */ + __IM uint32_t HFRCOCAL14; /**< HFRCO Calibration Register (56 MHz) */ + __IM uint32_t HFRCOCAL15; /**< HFRCO Calibration Register (64 MHz) */ + __IM uint32_t HFRCOCAL16; /**< HFRCO Calibration Register (72 MHz) */ + uint32_t RESERVED7[7U]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */ + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */ + __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */ + __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */ + uint32_t RESERVED10[1U]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */ + __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */ + __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */ + __IM uint32_t AUXHFRCOCAL13; /**< AUXHFRCO Calibration Register (48 MHz) */ + __IM uint32_t AUXHFRCOCAL14; /**< AUXHFRCO Calibration Register (50 MHz) */ + uint32_t RESERVED11[9U]; /**< Reserved for future use **/ + __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */ + __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */ + __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */ + uint32_t RESERVED12[3U]; /**< Reserved for future use **/ + __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */ + __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */ + uint32_t RESERVED13[2U]; /**< Reserved for future use **/ + __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */ + __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */ + __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */ + __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */ + __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */ + __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */ + __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */ + __IM uint32_t VDAC0MAINCAL; /**< VDAC0 Cals for Main Path */ + __IM uint32_t VDAC0ALTCAL; /**< VDAC0 Cals for Alternate Path */ + __IM uint32_t VDAC0CH1CAL; /**< VDAC0 CH1 Error Cal */ + __IM uint32_t OPA0CAL0; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA0CAL1; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA0CAL2; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA0CAL3; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA0CAL4; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA0CAL5; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA0CAL6; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA0CAL7; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t OPA1CAL0; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA1CAL1; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA1CAL2; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA1CAL3; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA1CAL4; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA1CAL5; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA1CAL6; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA1CAL7; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t OPA2CAL0; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA2CAL1; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA2CAL2; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA2CAL3; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA2CAL4; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA2CAL5; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA2CAL6; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA2CAL7; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t OPA3CAL0; /**< OPA3 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA3CAL1; /**< OPA3 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA3CAL2; /**< OPA3 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA3CAL3; /**< OPA3 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA3CAL4; /**< OPA3 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA3CAL5; /**< OPA3 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA3CAL6; /**< OPA3 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA3CAL7; /**< OPA3 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t CSENGAINCAL; /**< Cap Sense Gain Adjustment */ + uint32_t RESERVED14[22U]; /**< Reserved for future use **/ + __IM uint32_t USHFRCOCAL7; /**< USHFRCO Calibration Register (16 MHz) */ + uint32_t RESERVED15[3U]; /**< Reserved for future use **/ + __IM uint32_t USHFRCOCAL11; /**< USHFRCO Calibration Register (32 MHz) */ + uint32_t RESERVED16[1U]; /**< Reserved for future use **/ + __IM uint32_t USHFRCOCAL13; /**< USHFRCO Calibration Register (48 MHz) */ + __IM uint32_t USHFRCOCAL14; /**< USHFRCO Calibration Register (50 MHz) */ + uint32_t RESERVED17[9U]; /**< Reserved for future use **/ + __IM uint32_t CURRMON5V; /**< 5V Current monitor Transconductance */ +} DEVINFO_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_DEVINFO + * @{ + * @defgroup EFM32GG11B_DEVINFO_BitFields DEVINFO Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for DEVINFO CAL */ +#define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */ +#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */ +#define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */ +#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */ +#define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */ + +/* Bit fields for DEVINFO MODULEINFO */ +#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for HWREV */ +#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for MODNUMBER */ +#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_RESERVED1_SHIFT 20 /**< Shift value for RESERVED1 */ +#define _DEVINFO_MODULEINFO_RESERVED1_MASK 0xFFF00000UL /**< Bit mask for RESERVED1 */ + +/* Bit fields for DEVINFO MODXOCAL */ +#define _DEVINFO_MODXOCAL_MASK 0x0000FFFFUL /**< Mask for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNE_SHIFT 0 /**< Shift value for HFXOCTUNE */ +#define _DEVINFO_MODXOCAL_HFXOCTUNE_MASK 0x1FFUL /**< Bit mask for HFXOCTUNE */ +#define _DEVINFO_MODXOCAL_LFXOTUNING_SHIFT 9 /**< Shift value for LFXOTUNING */ +#define _DEVINFO_MODXOCAL_LFXOTUNING_MASK 0xFE00UL /**< Bit mask for LFXOTUNING */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */ +#define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_WF200 0x00000003UL /**< Mode WF200 for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_WF200 (_DEVINFO_EXTINFO_TYPE_WF200 << 0) /**< Shifted mode WF200 for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SDIO 0x00000002UL /**< Mode SDIO for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SDIO (_DEVINFO_EXTINFO_CONNECTION_SDIO << 8) /**< Shifted mode SDIO for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */ +#define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */ +#define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */ +#define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */ +#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_BGA (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */ +#define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */ +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */ +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */ + +/* Bit fields for DEVINFO UNIQUEL */ +#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */ +#define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */ + +/* Bit fields for DEVINFO UNIQUEH */ +#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */ +#define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */ +#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */ +#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */ +#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL /**< Mode EFR32ZG13P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L 0x0000002FUL /**< Mode EFR32ZG13L for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S 0x00000030UL /**< Mode EFR32ZG13S for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P 0x0000003AUL /**< Mode EFR32ZG14P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B 0x0000006AUL /**< Mode EFM32GG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P << 16) /**< Shifted mode EFR32ZG13P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L << 16) /**< Shifted mode EFR32ZG13L for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S << 16) /**< Shifted mode EFR32ZG13S for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P << 16) /**< Shifted mode EFR32ZG14P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B << 16) /**< Shifted mode EFM32GG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */ +#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */ +#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */ + +/* Bit fields for DEVINFO DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_MINOR_SHIFT 0 /**< Shift value for MINOR */ +#define _DEVINFO_DEVINFOREV_MINOR_MASK 0x1FUL /**< Bit mask for MINOR */ +#define _DEVINFO_DEVINFOREV_MAJOR_SHIFT 5 /**< Shift value for MAJOR */ +#define _DEVINFO_DEVINFOREV_MAJOR_MASK 0xE0UL /**< Bit mask for MAJOR */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */ + +/* Bit fields for DEVINFO ADC0CAL0 */ +#define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */ +#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */ +#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */ +#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */ +#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */ + +/* Bit fields for DEVINFO ADC0CAL1 */ +#define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */ +#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */ +#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */ +#define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */ +#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */ +#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */ + +/* Bit fields for DEVINFO ADC0CAL2 */ +#define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */ +#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */ + +/* Bit fields for DEVINFO ADC0CAL3 */ +#define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */ +#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */ +#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */ + +/* Bit fields for DEVINFO ADC1CAL0 */ +#define _DEVINFO_ADC1CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC1CAL0 */ +#define _DEVINFO_ADC1CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */ +#define _DEVINFO_ADC1CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */ +#define _DEVINFO_ADC1CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC1CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC1CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */ +#define _DEVINFO_ADC1CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */ +#define _DEVINFO_ADC1CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */ +#define _DEVINFO_ADC1CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */ +#define _DEVINFO_ADC1CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC1CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC1CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */ +#define _DEVINFO_ADC1CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */ + +/* Bit fields for DEVINFO ADC1CAL1 */ +#define _DEVINFO_ADC1CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC1CAL1 */ +#define _DEVINFO_ADC1CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */ +#define _DEVINFO_ADC1CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */ +#define _DEVINFO_ADC1CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC1CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC1CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */ +#define _DEVINFO_ADC1CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */ +#define _DEVINFO_ADC1CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */ +#define _DEVINFO_ADC1CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */ +#define _DEVINFO_ADC1CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC1CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC1CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */ +#define _DEVINFO_ADC1CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */ + +/* Bit fields for DEVINFO ADC1CAL2 */ +#define _DEVINFO_ADC1CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC1CAL2 */ +#define _DEVINFO_ADC1CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */ +#define _DEVINFO_ADC1CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */ +#define _DEVINFO_ADC1CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */ +#define _DEVINFO_ADC1CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */ + +/* Bit fields for DEVINFO ADC1CAL3 */ +#define _DEVINFO_ADC1CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC1CAL3 */ +#define _DEVINFO_ADC1CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */ +#define _DEVINFO_ADC1CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */ + +/* Bit fields for DEVINFO HFRCOCAL0 */ +#define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */ +#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL3 */ +#define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */ +#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL6 */ +#define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */ +#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL7 */ +#define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */ +#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL8 */ +#define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */ +#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL10 */ +#define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */ +#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL11 */ +#define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */ +#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL12 */ +#define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */ +#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL13 */ +#define _DEVINFO_HFRCOCAL13_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL13 */ +#define _DEVINFO_HFRCOCAL13_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL13_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL13_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL13_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL13_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL13_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL13_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL13_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL13_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL13_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL13_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL13_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL13_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL13_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL13_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL13_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL14 */ +#define _DEVINFO_HFRCOCAL14_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL14 */ +#define _DEVINFO_HFRCOCAL14_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL14_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL14_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL14_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL14_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL14_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL14_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL14_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL14_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL14_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL14_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL14_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL14_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL14_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL14_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL14_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL15 */ +#define _DEVINFO_HFRCOCAL15_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL15 */ +#define _DEVINFO_HFRCOCAL15_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL15_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL15_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL15_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL15_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL15_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL15_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL15_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL15_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL15_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL15_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL15_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL15_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL15_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL15_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL15_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL16 */ +#define _DEVINFO_HFRCOCAL16_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL16 */ +#define _DEVINFO_HFRCOCAL16_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL16_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL16_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL16_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL16_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL16_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL16_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL16_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL16_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL16_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL16_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL16_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL16_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL16_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL16_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL16_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL0 */ +#define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */ +#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL3 */ +#define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */ +#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL6 */ +#define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */ +#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL7 */ +#define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */ +#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL8 */ +#define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */ +#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL10 */ +#define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */ +#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL11 */ +#define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */ +#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL12 */ +#define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */ +#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL13 */ +#define _DEVINFO_AUXHFRCOCAL13_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL13 */ +#define _DEVINFO_AUXHFRCOCAL13_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL13_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL13_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL13_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL13_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL13_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL13_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL13_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL13_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL13_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL13_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL13_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL13_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL13_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL13_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL13_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL14 */ +#define _DEVINFO_AUXHFRCOCAL14_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL14 */ +#define _DEVINFO_AUXHFRCOCAL14_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL14_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL14_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL14_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL14_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL14_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL14_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL14_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL14_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL14_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL14_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL14_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL14_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL14_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL14_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL14_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO VMONCAL0 */ +#define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */ + +/* Bit fields for DEVINFO VMONCAL1 */ +#define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */ + +/* Bit fields for DEVINFO VMONCAL2 */ +#define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */ +#define _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_SHIFT 0 /**< Shift value for BUVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for BUVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for BUVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for BUVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_SHIFT 8 /**< Shift value for BUVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for BUVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for BUVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for BUVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_IO11V86THRESFINE_SHIFT 16 /**< Shift value for IO11V86THRESFINE */ +#define _DEVINFO_VMONCAL2_IO11V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO11V86THRESFINE */ +#define _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_SHIFT 20 /**< Shift value for IO11V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO11V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_IO12V98THRESFINE_SHIFT 24 /**< Shift value for IO12V98THRESFINE */ +#define _DEVINFO_VMONCAL2_IO12V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO12V98THRESFINE */ +#define _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_SHIFT 28 /**< Shift value for IO12V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO12V98THRESCOARSE */ + +/* Bit fields for DEVINFO IDAC0CAL0 */ +#define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */ + +/* Bit fields for DEVINFO IDAC0CAL1 */ +#define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */ + +/* Bit fields for DEVINFO DCDCLNVCTRL0 */ +#define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL0 */ +#define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL1 */ +#define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL2 */ +#define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL3 */ +#define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */ + +/* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */ + +/* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */ + +/* Bit fields for DEVINFO VDAC0MAINCAL */ +#define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0MAINCAL */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12 /**< Shift value for GAINERRTRIM1V25 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18 /**< Shift value for GAINERRTRIM2V5 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPIN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPIN */ + +/* Bit fields for DEVINFO VDAC0ALTCAL */ +#define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0ALTCAL */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12 /**< Shift value for GAINERRTRIM1V25ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18 /**< Shift value for GAINERRTRIM2V5ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPINALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPINALT */ + +/* Bit fields for DEVINFO VDAC0CH1CAL */ +#define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL /**< Mask for DEVINFO_VDAC0CH1CAL */ +#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for OFFSETTRIM */ +#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for OFFSETTRIM */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4 /**< Shift value for GAINERRTRIMCH1A */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL /**< Bit mask for GAINERRTRIMCH1A */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8 /**< Shift value for GAINERRTRIMCH1B */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL /**< Bit mask for GAINERRTRIMCH1B */ + +/* Bit fields for DEVINFO OPA0CAL0 */ +#define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL0 */ +#define _DEVINFO_OPA0CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL1 */ +#define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL1 */ +#define _DEVINFO_OPA0CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL2 */ +#define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL2 */ +#define _DEVINFO_OPA0CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL3 */ +#define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL3 */ +#define _DEVINFO_OPA0CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL4 */ +#define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL4 */ +#define _DEVINFO_OPA0CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL5 */ +#define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL5 */ +#define _DEVINFO_OPA0CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL6 */ +#define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL6 */ +#define _DEVINFO_OPA0CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL7 */ +#define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL7 */ +#define _DEVINFO_OPA0CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL0 */ +#define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL0 */ +#define _DEVINFO_OPA1CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL1 */ +#define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL1 */ +#define _DEVINFO_OPA1CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL2 */ +#define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL2 */ +#define _DEVINFO_OPA1CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL3 */ +#define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL3 */ +#define _DEVINFO_OPA1CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL4 */ +#define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL4 */ +#define _DEVINFO_OPA1CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL5 */ +#define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL5 */ +#define _DEVINFO_OPA1CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL6 */ +#define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL6 */ +#define _DEVINFO_OPA1CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL7 */ +#define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL7 */ +#define _DEVINFO_OPA1CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL0 */ +#define _DEVINFO_OPA2CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL0 */ +#define _DEVINFO_OPA2CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL1 */ +#define _DEVINFO_OPA2CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL1 */ +#define _DEVINFO_OPA2CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL2 */ +#define _DEVINFO_OPA2CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL2 */ +#define _DEVINFO_OPA2CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL3 */ +#define _DEVINFO_OPA2CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL3 */ +#define _DEVINFO_OPA2CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL4 */ +#define _DEVINFO_OPA2CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL4 */ +#define _DEVINFO_OPA2CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL5 */ +#define _DEVINFO_OPA2CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL5 */ +#define _DEVINFO_OPA2CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL6 */ +#define _DEVINFO_OPA2CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL6 */ +#define _DEVINFO_OPA2CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL7 */ +#define _DEVINFO_OPA2CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL7 */ +#define _DEVINFO_OPA2CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA3CAL0 */ +#define _DEVINFO_OPA3CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL0 */ +#define _DEVINFO_OPA3CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA3CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA3CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA3CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA3CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA3CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA3CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA3CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA3CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA3CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA3CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA3CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA3CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA3CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA3CAL1 */ +#define _DEVINFO_OPA3CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL1 */ +#define _DEVINFO_OPA3CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA3CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA3CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA3CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA3CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA3CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA3CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA3CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA3CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA3CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA3CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA3CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA3CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA3CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA3CAL2 */ +#define _DEVINFO_OPA3CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL2 */ +#define _DEVINFO_OPA3CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA3CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA3CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA3CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA3CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA3CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA3CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA3CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA3CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA3CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA3CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA3CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA3CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA3CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA3CAL3 */ +#define _DEVINFO_OPA3CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL3 */ +#define _DEVINFO_OPA3CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA3CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA3CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA3CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA3CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA3CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA3CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA3CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA3CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA3CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA3CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA3CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA3CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA3CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA3CAL4 */ +#define _DEVINFO_OPA3CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL4 */ +#define _DEVINFO_OPA3CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA3CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA3CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA3CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA3CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA3CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA3CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA3CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA3CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA3CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA3CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA3CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA3CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA3CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA3CAL5 */ +#define _DEVINFO_OPA3CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL5 */ +#define _DEVINFO_OPA3CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA3CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA3CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA3CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA3CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA3CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA3CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA3CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA3CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA3CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA3CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA3CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA3CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA3CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA3CAL6 */ +#define _DEVINFO_OPA3CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL6 */ +#define _DEVINFO_OPA3CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA3CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA3CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA3CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA3CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA3CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA3CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA3CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA3CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA3CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA3CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA3CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA3CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA3CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA3CAL7 */ +#define _DEVINFO_OPA3CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA3CAL7 */ +#define _DEVINFO_OPA3CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA3CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA3CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA3CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA3CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA3CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA3CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA3CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA3CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA3CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA3CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA3CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA3CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA3CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO CSENGAINCAL */ +#define _DEVINFO_CSENGAINCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_CSENGAINCAL */ +#define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT 0 /**< Shift value for GAINCAL */ +#define _DEVINFO_CSENGAINCAL_GAINCAL_MASK 0xFFUL /**< Bit mask for GAINCAL */ + +/* Bit fields for DEVINFO USHFRCOCAL7 */ +#define _DEVINFO_USHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_USHFRCOCAL7 */ +#define _DEVINFO_USHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_USHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_USHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_USHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_USHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_USHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_USHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_USHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_USHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_USHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_USHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_USHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_USHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_USHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_USHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_USHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO USHFRCOCAL11 */ +#define _DEVINFO_USHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_USHFRCOCAL11 */ +#define _DEVINFO_USHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_USHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_USHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_USHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_USHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_USHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_USHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_USHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_USHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_USHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_USHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_USHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_USHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_USHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_USHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_USHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO USHFRCOCAL13 */ +#define _DEVINFO_USHFRCOCAL13_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_USHFRCOCAL13 */ +#define _DEVINFO_USHFRCOCAL13_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_USHFRCOCAL13_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_USHFRCOCAL13_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_USHFRCOCAL13_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_USHFRCOCAL13_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_USHFRCOCAL13_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_USHFRCOCAL13_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_USHFRCOCAL13_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_USHFRCOCAL13_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_USHFRCOCAL13_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_USHFRCOCAL13_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_USHFRCOCAL13_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_USHFRCOCAL13_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_USHFRCOCAL13_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_USHFRCOCAL13_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_USHFRCOCAL13_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO USHFRCOCAL14 */ +#define _DEVINFO_USHFRCOCAL14_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_USHFRCOCAL14 */ +#define _DEVINFO_USHFRCOCAL14_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_USHFRCOCAL14_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_USHFRCOCAL14_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_USHFRCOCAL14_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_USHFRCOCAL14_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_USHFRCOCAL14_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_USHFRCOCAL14_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_USHFRCOCAL14_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_USHFRCOCAL14_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_USHFRCOCAL14_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_USHFRCOCAL14_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_USHFRCOCAL14_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_USHFRCOCAL14_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_USHFRCOCAL14_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_USHFRCOCAL14_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_USHFRCOCAL14_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO CURRMON5V */ +#define _DEVINFO_CURRMON5V_MASK 0x00000000UL /**< Mask for DEVINFO_CURRMON5V */ + +/** @} */ +/** @} End of group EFM32GG11B_DEVINFO */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dma_descriptor.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dma_descriptor.h new file mode 100644 index 0000000000000..95add43209dd5 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dma_descriptor.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_DMA_DESCRIPTOR register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_DMA_DESCRIPTOR DMA Descriptor + * @{ + ******************************************************************************/ +/** DMA_DESCRIPTOR Register Declaration */ +typedef struct { + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dmareq.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dmareq.h new file mode 100644 index 0000000000000..70fb8a973e134 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dmareq.h @@ -0,0 +1,171 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_DMAREQ register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_DMAREQ DMAREQ + * @{ + * @defgroup EFM32GG11B_DMAREQ_BitFields DMAREQ Bit Fields + * @{ + ******************************************************************************/ +#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */ +#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */ +#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */ +#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */ +#define DMAREQ_ADC1_SINGLE ((9 << 16) + 0) /**< DMA channel select for ADC1_SINGLE */ +#define DMAREQ_ADC1_SCAN ((9 << 16) + 1) /**< DMA channel select for ADC1_SCAN */ +#define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */ +#define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */ +#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */ +#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */ +#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */ +#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */ +#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */ +#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */ +#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */ +#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */ +#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */ +#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */ +#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */ +#define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */ +#define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */ +#define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */ +#define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */ +#define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */ +#define DMAREQ_USART4_RXDATAV ((16 << 16) + 0) /**< DMA channel select for USART4_RXDATAV */ +#define DMAREQ_USART4_TXBL ((16 << 16) + 1) /**< DMA channel select for USART4_TXBL */ +#define DMAREQ_USART4_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for USART4_TXEMPTY */ +#define DMAREQ_USART4_RXDATAVRIGHT ((16 << 16) + 3) /**< DMA channel select for USART4_RXDATAVRIGHT */ +#define DMAREQ_USART4_TXBLRIGHT ((16 << 16) + 4) /**< DMA channel select for USART4_TXBLRIGHT */ +#define DMAREQ_USART5_RXDATAV ((17 << 16) + 0) /**< DMA channel select for USART5_RXDATAV */ +#define DMAREQ_USART5_TXBL ((17 << 16) + 1) /**< DMA channel select for USART5_TXBL */ +#define DMAREQ_USART5_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for USART5_TXEMPTY */ +#define DMAREQ_UART0_RXDATAV ((18 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */ +#define DMAREQ_UART0_TXBL ((18 << 16) + 1) /**< DMA channel select for UART0_TXBL */ +#define DMAREQ_UART0_TXEMPTY ((18 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */ +#define DMAREQ_UART1_RXDATAV ((19 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */ +#define DMAREQ_UART1_TXBL ((19 << 16) + 1) /**< DMA channel select for UART1_TXBL */ +#define DMAREQ_UART1_TXEMPTY ((19 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */ +#define DMAREQ_LEUART0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */ +#define DMAREQ_LEUART0_TXBL ((20 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */ +#define DMAREQ_LEUART0_TXEMPTY ((20 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */ +#define DMAREQ_LEUART1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */ +#define DMAREQ_LEUART1_TXBL ((21 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */ +#define DMAREQ_LEUART1_TXEMPTY ((21 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */ +#define DMAREQ_I2C0_RXDATAV ((22 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */ +#define DMAREQ_I2C0_TXBL ((22 << 16) + 1) /**< DMA channel select for I2C0_TXBL */ +#define DMAREQ_I2C1_RXDATAV ((23 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */ +#define DMAREQ_I2C1_TXBL ((23 << 16) + 1) /**< DMA channel select for I2C1_TXBL */ +#define DMAREQ_I2C2_RXDATAV ((24 << 16) + 0) /**< DMA channel select for I2C2_RXDATAV */ +#define DMAREQ_I2C2_TXBL ((24 << 16) + 1) /**< DMA channel select for I2C2_TXBL */ +#define DMAREQ_TIMER0_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */ +#define DMAREQ_TIMER0_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */ +#define DMAREQ_TIMER0_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */ +#define DMAREQ_TIMER0_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */ +#define DMAREQ_TIMER1_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */ +#define DMAREQ_TIMER1_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */ +#define DMAREQ_TIMER1_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */ +#define DMAREQ_TIMER1_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */ +#define DMAREQ_TIMER1_CC3 ((26 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */ +#define DMAREQ_TIMER2_UFOF ((27 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */ +#define DMAREQ_TIMER2_CC0 ((27 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */ +#define DMAREQ_TIMER2_CC1 ((27 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */ +#define DMAREQ_TIMER2_CC2 ((27 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */ +#define DMAREQ_TIMER3_UFOF ((28 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */ +#define DMAREQ_TIMER3_CC0 ((28 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */ +#define DMAREQ_TIMER3_CC1 ((28 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */ +#define DMAREQ_TIMER3_CC2 ((28 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */ +#define DMAREQ_TIMER4_UFOF ((29 << 16) + 0) /**< DMA channel select for TIMER4_UFOF */ +#define DMAREQ_TIMER4_CC0 ((29 << 16) + 1) /**< DMA channel select for TIMER4_CC0 */ +#define DMAREQ_TIMER4_CC1 ((29 << 16) + 2) /**< DMA channel select for TIMER4_CC1 */ +#define DMAREQ_TIMER4_CC2 ((29 << 16) + 3) /**< DMA channel select for TIMER4_CC2 */ +#define DMAREQ_TIMER5_UFOF ((30 << 16) + 0) /**< DMA channel select for TIMER5_UFOF */ +#define DMAREQ_TIMER5_CC0 ((30 << 16) + 1) /**< DMA channel select for TIMER5_CC0 */ +#define DMAREQ_TIMER5_CC1 ((30 << 16) + 2) /**< DMA channel select for TIMER5_CC1 */ +#define DMAREQ_TIMER5_CC2 ((30 << 16) + 3) /**< DMA channel select for TIMER5_CC2 */ +#define DMAREQ_TIMER6_UFOF ((31 << 16) + 0) /**< DMA channel select for TIMER6_UFOF */ +#define DMAREQ_TIMER6_CC0 ((31 << 16) + 1) /**< DMA channel select for TIMER6_CC0 */ +#define DMAREQ_TIMER6_CC1 ((31 << 16) + 2) /**< DMA channel select for TIMER6_CC1 */ +#define DMAREQ_TIMER6_CC2 ((31 << 16) + 3) /**< DMA channel select for TIMER6_CC2 */ +#define DMAREQ_WTIMER0_UFOF ((32 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */ +#define DMAREQ_WTIMER0_CC0 ((32 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */ +#define DMAREQ_WTIMER0_CC1 ((32 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */ +#define DMAREQ_WTIMER0_CC2 ((32 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */ +#define DMAREQ_WTIMER1_UFOF ((33 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */ +#define DMAREQ_WTIMER1_CC0 ((33 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */ +#define DMAREQ_WTIMER1_CC1 ((33 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */ +#define DMAREQ_WTIMER1_CC2 ((33 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */ +#define DMAREQ_WTIMER1_CC3 ((33 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */ +#define DMAREQ_WTIMER2_UFOF ((34 << 16) + 0) /**< DMA channel select for WTIMER2_UFOF */ +#define DMAREQ_WTIMER2_CC0 ((34 << 16) + 1) /**< DMA channel select for WTIMER2_CC0 */ +#define DMAREQ_WTIMER2_CC1 ((34 << 16) + 2) /**< DMA channel select for WTIMER2_CC1 */ +#define DMAREQ_WTIMER2_CC2 ((34 << 16) + 3) /**< DMA channel select for WTIMER2_CC2 */ +#define DMAREQ_WTIMER3_UFOF ((35 << 16) + 0) /**< DMA channel select for WTIMER3_UFOF */ +#define DMAREQ_WTIMER3_CC0 ((35 << 16) + 1) /**< DMA channel select for WTIMER3_CC0 */ +#define DMAREQ_WTIMER3_CC1 ((35 << 16) + 2) /**< DMA channel select for WTIMER3_CC1 */ +#define DMAREQ_WTIMER3_CC2 ((35 << 16) + 3) /**< DMA channel select for WTIMER3_CC2 */ +#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */ +#define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */ +#define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */ +#define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */ +#define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */ +#define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */ +#define DMAREQ_EBI_PXL0EMPTY ((50 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */ +#define DMAREQ_EBI_PXL1EMPTY ((50 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */ +#define DMAREQ_EBI_PXLFULL ((50 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */ +#define DMAREQ_EBI_DDEMPTY ((50 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */ +#define DMAREQ_EBI_VSYNC ((50 << 16) + 4) /**< DMA channel select for EBI_VSYNC */ +#define DMAREQ_EBI_HSYNC ((50 << 16) + 5) /**< DMA channel select for EBI_HSYNC */ +#define DMAREQ_CSEN_DATA ((61 << 16) + 0) /**< DMA channel select for CSEN_DATA */ +#define DMAREQ_CSEN_BSLN ((61 << 16) + 1) /**< DMA channel select for CSEN_BSLN */ +#define DMAREQ_LESENSE_BUFDATAV ((62 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */ + +/** @} */ +/** @} End of group EFM32GG11B_DMAREQ */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ebi.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ebi.h new file mode 100644 index 0000000000000..d1c09dc985f58 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ebi.h @@ -0,0 +1,1712 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_EBI register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_EBI EBI + * @{ + * @brief EFM32GG11B_EBI Register Declaration + ******************************************************************************/ +/** EBI Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t ADDRTIMING; /**< Address Timing Register */ + __IOM uint32_t RDTIMING; /**< Read Timing Register */ + __IOM uint32_t WRTIMING; /**< Write Timing Register */ + __IOM uint32_t POLARITY; /**< Polarity Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ADDRTIMING1; /**< Address Timing Register 1 */ + __IOM uint32_t RDTIMING1; /**< Read Timing Register 1 */ + __IOM uint32_t WRTIMING1; /**< Write Timing Register 1 */ + __IOM uint32_t POLARITY1; /**< Polarity Register 1 */ + __IOM uint32_t ADDRTIMING2; /**< Address Timing Register 2 */ + __IOM uint32_t RDTIMING2; /**< Read Timing Register 2 */ + __IOM uint32_t WRTIMING2; /**< Write Timing Register 2 */ + __IOM uint32_t POLARITY2; /**< Polarity Register 2 */ + __IOM uint32_t ADDRTIMING3; /**< Address Timing Register 3 */ + __IOM uint32_t RDTIMING3; /**< Read Timing Register 3 */ + __IOM uint32_t WRTIMING3; /**< Write Timing Register 3 */ + __IOM uint32_t POLARITY3; /**< Polarity Register 3 */ + __IOM uint32_t PAGECTRL; /**< Page Control Register */ + __IOM uint32_t NANDCTRL; /**< NAND Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t ECCPARITY; /**< ECC Parity Register */ + __IOM uint32_t TFTCTRL; /**< TFT Control Register */ + __IM uint32_t TFTSTATUS; /**< TFT Status Register */ + __IOM uint32_t TFTCOLORFORMAT; /**< Color Format Register */ + __IOM uint32_t TFTFRAMEBASE; /**< TFT Frame Base Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t TFTSTRIDE; /**< TFT Stride Register */ + __IOM uint32_t TFTSIZE; /**< TFT Size Register */ + __IOM uint32_t TFTHPORCH; /**< TFT Horizontal Porch Register */ + __IOM uint32_t TFTVPORCH; /**< TFT Vertical Porch Register */ + __IOM uint32_t TFTTIMING; /**< TFT Timing Register */ + __IOM uint32_t TFTPOLARITY; /**< TFT Polarity Register */ + __IOM uint32_t TFTDD; /**< TFT Direct Drive Data Register */ + __IOM uint32_t TFTALPHA; /**< TFT Alpha Blending Register */ + __IOM uint32_t TFTPIXEL0; /**< TFT Pixel 0 Register */ + __IOM uint32_t TFTPIXEL1; /**< TFT Pixel 1 Register */ + __IM uint32_t TFTPIXEL; /**< TFT Alpha Blending Result Pixel Register */ + __IOM uint32_t TFTMASK; /**< TFT Masking Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ +} EBI_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_EBI + * @{ + * @defgroup EFM32GG11B_EBI_BitFields EBI Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EBI CTRL */ +#define _EBI_CTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_CTRL */ +#define _EBI_CTRL_MASK 0xCFFFFFFFUL /**< Mask for EBI_CTRL */ +#define _EBI_CTRL_MODE_SHIFT 0 /**< Shift value for EBI_MODE */ +#define _EBI_CTRL_MODE_MASK 0x3UL /**< Bit mask for EBI_MODE */ +#define _EBI_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define _EBI_CTRL_MODE_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ +#define _EBI_CTRL_MODE_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ +#define _EBI_CTRL_MODE_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ +#define _EBI_CTRL_MODE_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ +#define EBI_CTRL_MODE_DEFAULT (_EBI_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_MODE_D8A8 (_EBI_CTRL_MODE_D8A8 << 0) /**< Shifted mode D8A8 for EBI_CTRL */ +#define EBI_CTRL_MODE_D16A16ALE (_EBI_CTRL_MODE_D16A16ALE << 0) /**< Shifted mode D16A16ALE for EBI_CTRL */ +#define EBI_CTRL_MODE_D8A24ALE (_EBI_CTRL_MODE_D8A24ALE << 0) /**< Shifted mode D8A24ALE for EBI_CTRL */ +#define EBI_CTRL_MODE_D16 (_EBI_CTRL_MODE_D16 << 0) /**< Shifted mode D16 for EBI_CTRL */ +#define _EBI_CTRL_MODE1_SHIFT 2 /**< Shift value for EBI_MODE1 */ +#define _EBI_CTRL_MODE1_MASK 0xCUL /**< Bit mask for EBI_MODE1 */ +#define _EBI_CTRL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define _EBI_CTRL_MODE1_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ +#define _EBI_CTRL_MODE1_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ +#define _EBI_CTRL_MODE1_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ +#define _EBI_CTRL_MODE1_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ +#define EBI_CTRL_MODE1_DEFAULT (_EBI_CTRL_MODE1_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_MODE1_D8A8 (_EBI_CTRL_MODE1_D8A8 << 2) /**< Shifted mode D8A8 for EBI_CTRL */ +#define EBI_CTRL_MODE1_D16A16ALE (_EBI_CTRL_MODE1_D16A16ALE << 2) /**< Shifted mode D16A16ALE for EBI_CTRL */ +#define EBI_CTRL_MODE1_D8A24ALE (_EBI_CTRL_MODE1_D8A24ALE << 2) /**< Shifted mode D8A24ALE for EBI_CTRL */ +#define EBI_CTRL_MODE1_D16 (_EBI_CTRL_MODE1_D16 << 2) /**< Shifted mode D16 for EBI_CTRL */ +#define _EBI_CTRL_MODE2_SHIFT 4 /**< Shift value for EBI_MODE2 */ +#define _EBI_CTRL_MODE2_MASK 0x30UL /**< Bit mask for EBI_MODE2 */ +#define _EBI_CTRL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define _EBI_CTRL_MODE2_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ +#define _EBI_CTRL_MODE2_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ +#define _EBI_CTRL_MODE2_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ +#define _EBI_CTRL_MODE2_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ +#define EBI_CTRL_MODE2_DEFAULT (_EBI_CTRL_MODE2_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_MODE2_D8A8 (_EBI_CTRL_MODE2_D8A8 << 4) /**< Shifted mode D8A8 for EBI_CTRL */ +#define EBI_CTRL_MODE2_D16A16ALE (_EBI_CTRL_MODE2_D16A16ALE << 4) /**< Shifted mode D16A16ALE for EBI_CTRL */ +#define EBI_CTRL_MODE2_D8A24ALE (_EBI_CTRL_MODE2_D8A24ALE << 4) /**< Shifted mode D8A24ALE for EBI_CTRL */ +#define EBI_CTRL_MODE2_D16 (_EBI_CTRL_MODE2_D16 << 4) /**< Shifted mode D16 for EBI_CTRL */ +#define _EBI_CTRL_MODE3_SHIFT 6 /**< Shift value for EBI_MODE3 */ +#define _EBI_CTRL_MODE3_MASK 0xC0UL /**< Bit mask for EBI_MODE3 */ +#define _EBI_CTRL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define _EBI_CTRL_MODE3_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ +#define _EBI_CTRL_MODE3_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ +#define _EBI_CTRL_MODE3_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ +#define _EBI_CTRL_MODE3_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ +#define EBI_CTRL_MODE3_DEFAULT (_EBI_CTRL_MODE3_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_MODE3_D8A8 (_EBI_CTRL_MODE3_D8A8 << 6) /**< Shifted mode D8A8 for EBI_CTRL */ +#define EBI_CTRL_MODE3_D16A16ALE (_EBI_CTRL_MODE3_D16A16ALE << 6) /**< Shifted mode D16A16ALE for EBI_CTRL */ +#define EBI_CTRL_MODE3_D8A24ALE (_EBI_CTRL_MODE3_D8A24ALE << 6) /**< Shifted mode D8A24ALE for EBI_CTRL */ +#define EBI_CTRL_MODE3_D16 (_EBI_CTRL_MODE3_D16 << 6) /**< Shifted mode D16 for EBI_CTRL */ +#define EBI_CTRL_BANK0EN (0x1UL << 8) /**< Bank 0 Enable */ +#define _EBI_CTRL_BANK0EN_SHIFT 8 /**< Shift value for EBI_BANK0EN */ +#define _EBI_CTRL_BANK0EN_MASK 0x100UL /**< Bit mask for EBI_BANK0EN */ +#define _EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BANK0EN_DEFAULT (_EBI_CTRL_BANK0EN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BANK1EN (0x1UL << 9) /**< Bank 1 Enable */ +#define _EBI_CTRL_BANK1EN_SHIFT 9 /**< Shift value for EBI_BANK1EN */ +#define _EBI_CTRL_BANK1EN_MASK 0x200UL /**< Bit mask for EBI_BANK1EN */ +#define _EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BANK1EN_DEFAULT (_EBI_CTRL_BANK1EN_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BANK2EN (0x1UL << 10) /**< Bank 2 Enable */ +#define _EBI_CTRL_BANK2EN_SHIFT 10 /**< Shift value for EBI_BANK2EN */ +#define _EBI_CTRL_BANK2EN_MASK 0x400UL /**< Bit mask for EBI_BANK2EN */ +#define _EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BANK2EN_DEFAULT (_EBI_CTRL_BANK2EN_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BANK3EN (0x1UL << 11) /**< Bank 3 Enable */ +#define _EBI_CTRL_BANK3EN_SHIFT 11 /**< Shift value for EBI_BANK3EN */ +#define _EBI_CTRL_BANK3EN_MASK 0x800UL /**< Bit mask for EBI_BANK3EN */ +#define _EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BANK3EN_DEFAULT (_EBI_CTRL_BANK3EN_DEFAULT << 11) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_NOIDLE (0x1UL << 12) /**< No Idle Cycle Insertion on Bank 0 */ +#define _EBI_CTRL_NOIDLE_SHIFT 12 /**< Shift value for EBI_NOIDLE */ +#define _EBI_CTRL_NOIDLE_MASK 0x1000UL /**< Bit mask for EBI_NOIDLE */ +#define _EBI_CTRL_NOIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_NOIDLE_DEFAULT (_EBI_CTRL_NOIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_NOIDLE1 (0x1UL << 13) /**< No Idle Cycle Insertion on Bank 1 */ +#define _EBI_CTRL_NOIDLE1_SHIFT 13 /**< Shift value for EBI_NOIDLE1 */ +#define _EBI_CTRL_NOIDLE1_MASK 0x2000UL /**< Bit mask for EBI_NOIDLE1 */ +#define _EBI_CTRL_NOIDLE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_NOIDLE1_DEFAULT (_EBI_CTRL_NOIDLE1_DEFAULT << 13) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_NOIDLE2 (0x1UL << 14) /**< No Idle Cycle Insertion on Bank 2 */ +#define _EBI_CTRL_NOIDLE2_SHIFT 14 /**< Shift value for EBI_NOIDLE2 */ +#define _EBI_CTRL_NOIDLE2_MASK 0x4000UL /**< Bit mask for EBI_NOIDLE2 */ +#define _EBI_CTRL_NOIDLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_NOIDLE2_DEFAULT (_EBI_CTRL_NOIDLE2_DEFAULT << 14) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_NOIDLE3 (0x1UL << 15) /**< No Idle Cycle Insertion on Bank 3 */ +#define _EBI_CTRL_NOIDLE3_SHIFT 15 /**< Shift value for EBI_NOIDLE3 */ +#define _EBI_CTRL_NOIDLE3_MASK 0x8000UL /**< Bit mask for EBI_NOIDLE3 */ +#define _EBI_CTRL_NOIDLE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_NOIDLE3_DEFAULT (_EBI_CTRL_NOIDLE3_DEFAULT << 15) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYEN (0x1UL << 16) /**< ARDY Enable */ +#define _EBI_CTRL_ARDYEN_SHIFT 16 /**< Shift value for EBI_ARDYEN */ +#define _EBI_CTRL_ARDYEN_MASK 0x10000UL /**< Bit mask for EBI_ARDYEN */ +#define _EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYEN_DEFAULT (_EBI_CTRL_ARDYEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYTODIS (0x1UL << 17) /**< ARDY Timeout Disable */ +#define _EBI_CTRL_ARDYTODIS_SHIFT 17 /**< Shift value for EBI_ARDYTODIS */ +#define _EBI_CTRL_ARDYTODIS_MASK 0x20000UL /**< Bit mask for EBI_ARDYTODIS */ +#define _EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYTODIS_DEFAULT (_EBI_CTRL_ARDYTODIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDY1EN (0x1UL << 18) /**< ARDY Enable for Bank 1 */ +#define _EBI_CTRL_ARDY1EN_SHIFT 18 /**< Shift value for EBI_ARDY1EN */ +#define _EBI_CTRL_ARDY1EN_MASK 0x40000UL /**< Bit mask for EBI_ARDY1EN */ +#define _EBI_CTRL_ARDY1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDY1EN_DEFAULT (_EBI_CTRL_ARDY1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYTO1DIS (0x1UL << 19) /**< ARDY Timeout Disable for Bank 1 */ +#define _EBI_CTRL_ARDYTO1DIS_SHIFT 19 /**< Shift value for EBI_ARDYTO1DIS */ +#define _EBI_CTRL_ARDYTO1DIS_MASK 0x80000UL /**< Bit mask for EBI_ARDYTO1DIS */ +#define _EBI_CTRL_ARDYTO1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYTO1DIS_DEFAULT (_EBI_CTRL_ARDYTO1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDY2EN (0x1UL << 20) /**< ARDY Enable for Bank 2 */ +#define _EBI_CTRL_ARDY2EN_SHIFT 20 /**< Shift value for EBI_ARDY2EN */ +#define _EBI_CTRL_ARDY2EN_MASK 0x100000UL /**< Bit mask for EBI_ARDY2EN */ +#define _EBI_CTRL_ARDY2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDY2EN_DEFAULT (_EBI_CTRL_ARDY2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYTO2DIS (0x1UL << 21) /**< ARDY Timeout Disable for Bank 2 */ +#define _EBI_CTRL_ARDYTO2DIS_SHIFT 21 /**< Shift value for EBI_ARDYTO2DIS */ +#define _EBI_CTRL_ARDYTO2DIS_MASK 0x200000UL /**< Bit mask for EBI_ARDYTO2DIS */ +#define _EBI_CTRL_ARDYTO2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYTO2DIS_DEFAULT (_EBI_CTRL_ARDYTO2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDY3EN (0x1UL << 22) /**< ARDY Enable for Bank 3 */ +#define _EBI_CTRL_ARDY3EN_SHIFT 22 /**< Shift value for EBI_ARDY3EN */ +#define _EBI_CTRL_ARDY3EN_MASK 0x400000UL /**< Bit mask for EBI_ARDY3EN */ +#define _EBI_CTRL_ARDY3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDY3EN_DEFAULT (_EBI_CTRL_ARDY3EN_DEFAULT << 22) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYTO3DIS (0x1UL << 23) /**< ARDY Timeout Disable for Bank 3 */ +#define _EBI_CTRL_ARDYTO3DIS_SHIFT 23 /**< Shift value for EBI_ARDYTO3DIS */ +#define _EBI_CTRL_ARDYTO3DIS_MASK 0x800000UL /**< Bit mask for EBI_ARDYTO3DIS */ +#define _EBI_CTRL_ARDYTO3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ARDYTO3DIS_DEFAULT (_EBI_CTRL_ARDYTO3DIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BL (0x1UL << 24) /**< Byte Lane Enable for Bank 0 */ +#define _EBI_CTRL_BL_SHIFT 24 /**< Shift value for EBI_BL */ +#define _EBI_CTRL_BL_MASK 0x1000000UL /**< Bit mask for EBI_BL */ +#define _EBI_CTRL_BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BL_DEFAULT (_EBI_CTRL_BL_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BL1 (0x1UL << 25) /**< Byte Lane Enable for Bank 1 */ +#define _EBI_CTRL_BL1_SHIFT 25 /**< Shift value for EBI_BL1 */ +#define _EBI_CTRL_BL1_MASK 0x2000000UL /**< Bit mask for EBI_BL1 */ +#define _EBI_CTRL_BL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BL1_DEFAULT (_EBI_CTRL_BL1_DEFAULT << 25) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BL2 (0x1UL << 26) /**< Byte Lane Enable for Bank 2 */ +#define _EBI_CTRL_BL2_SHIFT 26 /**< Shift value for EBI_BL2 */ +#define _EBI_CTRL_BL2_MASK 0x4000000UL /**< Bit mask for EBI_BL2 */ +#define _EBI_CTRL_BL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BL2_DEFAULT (_EBI_CTRL_BL2_DEFAULT << 26) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BL3 (0x1UL << 27) /**< Byte Lane Enable for Bank 3 */ +#define _EBI_CTRL_BL3_SHIFT 27 /**< Shift value for EBI_BL3 */ +#define _EBI_CTRL_BL3_MASK 0x8000000UL /**< Bit mask for EBI_BL3 */ +#define _EBI_CTRL_BL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_BL3_DEFAULT (_EBI_CTRL_BL3_DEFAULT << 27) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ITS (0x1UL << 30) /**< Individual Timing Set, Line Polarity and Mode Definition Enable */ +#define _EBI_CTRL_ITS_SHIFT 30 /**< Shift value for EBI_ITS */ +#define _EBI_CTRL_ITS_MASK 0x40000000UL /**< Bit mask for EBI_ITS */ +#define _EBI_CTRL_ITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ITS_DEFAULT (_EBI_CTRL_ITS_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ALTMAP (0x1UL << 31) /**< Alternative Address Map Enable */ +#define _EBI_CTRL_ALTMAP_SHIFT 31 /**< Shift value for EBI_ALTMAP */ +#define _EBI_CTRL_ALTMAP_MASK 0x80000000UL /**< Bit mask for EBI_ALTMAP */ +#define _EBI_CTRL_ALTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ +#define EBI_CTRL_ALTMAP_DEFAULT (_EBI_CTRL_ALTMAP_DEFAULT << 31) /**< Shifted mode DEFAULT for EBI_CTRL */ + +/* Bit fields for EBI ADDRTIMING */ +#define _EBI_ADDRTIMING_RESETVALUE 0x00000707UL /**< Default value for EBI_ADDRTIMING */ +#define _EBI_ADDRTIMING_MASK 0x10000707UL /**< Mask for EBI_ADDRTIMING */ +#define _EBI_ADDRTIMING_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ +#define _EBI_ADDRTIMING_ADDRSETUP_MASK 0x7UL /**< Bit mask for EBI_ADDRSETUP */ +#define _EBI_ADDRTIMING_ADDRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING */ +#define EBI_ADDRTIMING_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */ +#define _EBI_ADDRTIMING_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ +#define _EBI_ADDRTIMING_ADDRHOLD_MASK 0x700UL /**< Bit mask for EBI_ADDRHOLD */ +#define _EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING */ +#define EBI_ADDRTIMING_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */ +#define EBI_ADDRTIMING_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ +#define _EBI_ADDRTIMING_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ +#define _EBI_ADDRTIMING_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ +#define _EBI_ADDRTIMING_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING */ +#define EBI_ADDRTIMING_HALFALE_DEFAULT (_EBI_ADDRTIMING_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */ + +/* Bit fields for EBI RDTIMING */ +#define _EBI_RDTIMING_RESETVALUE 0x00077F07UL /**< Default value for EBI_RDTIMING */ +#define _EBI_RDTIMING_MASK 0x70077F07UL /**< Mask for EBI_RDTIMING */ +#define _EBI_RDTIMING_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ +#define _EBI_RDTIMING_RDSETUP_MASK 0x7UL /**< Bit mask for EBI_RDSETUP */ +#define _EBI_RDTIMING_RDSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING */ +#define EBI_RDTIMING_RDSETUP_DEFAULT (_EBI_RDTIMING_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING */ +#define _EBI_RDTIMING_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ +#define _EBI_RDTIMING_RDSTRB_MASK 0x7F00UL /**< Bit mask for EBI_RDSTRB */ +#define _EBI_RDTIMING_RDSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_RDTIMING */ +#define EBI_RDTIMING_RDSTRB_DEFAULT (_EBI_RDTIMING_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING */ +#define _EBI_RDTIMING_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ +#define _EBI_RDTIMING_RDHOLD_MASK 0x70000UL /**< Bit mask for EBI_RDHOLD */ +#define _EBI_RDTIMING_RDHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING */ +#define EBI_RDTIMING_RDHOLD_DEFAULT (_EBI_RDTIMING_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING */ +#define EBI_RDTIMING_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ +#define _EBI_RDTIMING_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ +#define _EBI_RDTIMING_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ +#define _EBI_RDTIMING_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ +#define EBI_RDTIMING_HALFRE_DEFAULT (_EBI_RDTIMING_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING */ +#define EBI_RDTIMING_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ +#define _EBI_RDTIMING_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ +#define _EBI_RDTIMING_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ +#define _EBI_RDTIMING_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ +#define EBI_RDTIMING_PREFETCH_DEFAULT (_EBI_RDTIMING_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING */ +#define EBI_RDTIMING_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ +#define _EBI_RDTIMING_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ +#define _EBI_RDTIMING_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ +#define _EBI_RDTIMING_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ +#define EBI_RDTIMING_PAGEMODE_DEFAULT (_EBI_RDTIMING_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING */ + +/* Bit fields for EBI WRTIMING */ +#define _EBI_WRTIMING_RESETVALUE 0x00077F07UL /**< Default value for EBI_WRTIMING */ +#define _EBI_WRTIMING_MASK 0x30077F07UL /**< Mask for EBI_WRTIMING */ +#define _EBI_WRTIMING_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ +#define _EBI_WRTIMING_WRSETUP_MASK 0x7UL /**< Bit mask for EBI_WRSETUP */ +#define _EBI_WRTIMING_WRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING */ +#define EBI_WRTIMING_WRSETUP_DEFAULT (_EBI_WRTIMING_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING */ +#define _EBI_WRTIMING_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ +#define _EBI_WRTIMING_WRSTRB_MASK 0x7F00UL /**< Bit mask for EBI_WRSTRB */ +#define _EBI_WRTIMING_WRSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_WRTIMING */ +#define EBI_WRTIMING_WRSTRB_DEFAULT (_EBI_WRTIMING_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING */ +#define _EBI_WRTIMING_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ +#define _EBI_WRTIMING_WRHOLD_MASK 0x70000UL /**< Bit mask for EBI_WRHOLD */ +#define _EBI_WRTIMING_WRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING */ +#define EBI_WRTIMING_WRHOLD_DEFAULT (_EBI_WRTIMING_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING */ +#define EBI_WRTIMING_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ +#define _EBI_WRTIMING_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ +#define _EBI_WRTIMING_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ +#define _EBI_WRTIMING_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */ +#define EBI_WRTIMING_HALFWE_DEFAULT (_EBI_WRTIMING_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING */ +#define EBI_WRTIMING_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ +#define _EBI_WRTIMING_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ +#define _EBI_WRTIMING_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ +#define _EBI_WRTIMING_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */ +#define EBI_WRTIMING_WBUFDIS_DEFAULT (_EBI_WRTIMING_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING */ + +/* Bit fields for EBI POLARITY */ +#define _EBI_POLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY */ +#define _EBI_POLARITY_MASK 0x0000003FUL /**< Mask for EBI_POLARITY */ +#define EBI_POLARITY_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ +#define _EBI_POLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ +#define _EBI_POLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ +#define _EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ +#define _EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ +#define _EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_CSPOL_DEFAULT (_EBI_POLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY */ +#define EBI_POLARITY_CSPOL_ACTIVELOW (_EBI_POLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ +#define EBI_POLARITY_CSPOL_ACTIVEHIGH (_EBI_POLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_REPOL (0x1UL << 1) /**< Read Enable Polarity */ +#define _EBI_POLARITY_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ +#define _EBI_POLARITY_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ +#define _EBI_POLARITY_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ +#define _EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ +#define _EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_REPOL_DEFAULT (_EBI_POLARITY_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY */ +#define EBI_POLARITY_REPOL_ACTIVELOW (_EBI_POLARITY_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ +#define EBI_POLARITY_REPOL_ACTIVEHIGH (_EBI_POLARITY_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ +#define _EBI_POLARITY_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ +#define _EBI_POLARITY_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ +#define _EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ +#define _EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ +#define _EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_WEPOL_DEFAULT (_EBI_POLARITY_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY */ +#define EBI_POLARITY_WEPOL_ACTIVELOW (_EBI_POLARITY_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ +#define EBI_POLARITY_WEPOL_ACTIVEHIGH (_EBI_POLARITY_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ +#define _EBI_POLARITY_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ +#define _EBI_POLARITY_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ +#define _EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ +#define _EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ +#define _EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_ALEPOL_DEFAULT (_EBI_POLARITY_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY */ +#define EBI_POLARITY_ALEPOL_ACTIVELOW (_EBI_POLARITY_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ +#define EBI_POLARITY_ALEPOL_ACTIVEHIGH (_EBI_POLARITY_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ +#define _EBI_POLARITY_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ +#define _EBI_POLARITY_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ +#define _EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ +#define _EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ +#define _EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_ARDYPOL_DEFAULT (_EBI_POLARITY_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY */ +#define EBI_POLARITY_ARDYPOL_ACTIVELOW (_EBI_POLARITY_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ +#define EBI_POLARITY_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_BLPOL (0x1UL << 5) /**< BL Polarity */ +#define _EBI_POLARITY_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ +#define _EBI_POLARITY_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ +#define _EBI_POLARITY_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ +#define _EBI_POLARITY_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ +#define _EBI_POLARITY_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ +#define EBI_POLARITY_BLPOL_DEFAULT (_EBI_POLARITY_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY */ +#define EBI_POLARITY_BLPOL_ACTIVELOW (_EBI_POLARITY_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ +#define EBI_POLARITY_BLPOL_ACTIVEHIGH (_EBI_POLARITY_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ + +/* Bit fields for EBI ADDRTIMING1 */ +#define _EBI_ADDRTIMING1_RESETVALUE 0x00000707UL /**< Default value for EBI_ADDRTIMING1 */ +#define _EBI_ADDRTIMING1_MASK 0x10000707UL /**< Mask for EBI_ADDRTIMING1 */ +#define _EBI_ADDRTIMING1_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ +#define _EBI_ADDRTIMING1_ADDRSETUP_MASK 0x7UL /**< Bit mask for EBI_ADDRSETUP */ +#define _EBI_ADDRTIMING1_ADDRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */ +#define EBI_ADDRTIMING1_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING1_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */ +#define _EBI_ADDRTIMING1_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ +#define _EBI_ADDRTIMING1_ADDRHOLD_MASK 0x700UL /**< Bit mask for EBI_ADDRHOLD */ +#define _EBI_ADDRTIMING1_ADDRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */ +#define EBI_ADDRTIMING1_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING1_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */ +#define EBI_ADDRTIMING1_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ +#define _EBI_ADDRTIMING1_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ +#define _EBI_ADDRTIMING1_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ +#define _EBI_ADDRTIMING1_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */ +#define EBI_ADDRTIMING1_HALFALE_DEFAULT (_EBI_ADDRTIMING1_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */ + +/* Bit fields for EBI RDTIMING1 */ +#define _EBI_RDTIMING1_RESETVALUE 0x00077F07UL /**< Default value for EBI_RDTIMING1 */ +#define _EBI_RDTIMING1_MASK 0x70077F07UL /**< Mask for EBI_RDTIMING1 */ +#define _EBI_RDTIMING1_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ +#define _EBI_RDTIMING1_RDSETUP_MASK 0x7UL /**< Bit mask for EBI_RDSETUP */ +#define _EBI_RDTIMING1_RDSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING1 */ +#define EBI_RDTIMING1_RDSETUP_DEFAULT (_EBI_RDTIMING1_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ +#define _EBI_RDTIMING1_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ +#define _EBI_RDTIMING1_RDSTRB_MASK 0x7F00UL /**< Bit mask for EBI_RDSTRB */ +#define _EBI_RDTIMING1_RDSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_RDTIMING1 */ +#define EBI_RDTIMING1_RDSTRB_DEFAULT (_EBI_RDTIMING1_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ +#define _EBI_RDTIMING1_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ +#define _EBI_RDTIMING1_RDHOLD_MASK 0x70000UL /**< Bit mask for EBI_RDHOLD */ +#define _EBI_RDTIMING1_RDHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING1 */ +#define EBI_RDTIMING1_RDHOLD_DEFAULT (_EBI_RDTIMING1_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ +#define EBI_RDTIMING1_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ +#define _EBI_RDTIMING1_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ +#define _EBI_RDTIMING1_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ +#define _EBI_RDTIMING1_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */ +#define EBI_RDTIMING1_HALFRE_DEFAULT (_EBI_RDTIMING1_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ +#define EBI_RDTIMING1_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ +#define _EBI_RDTIMING1_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ +#define _EBI_RDTIMING1_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ +#define _EBI_RDTIMING1_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */ +#define EBI_RDTIMING1_PREFETCH_DEFAULT (_EBI_RDTIMING1_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ +#define EBI_RDTIMING1_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ +#define _EBI_RDTIMING1_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ +#define _EBI_RDTIMING1_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ +#define _EBI_RDTIMING1_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */ +#define EBI_RDTIMING1_PAGEMODE_DEFAULT (_EBI_RDTIMING1_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ + +/* Bit fields for EBI WRTIMING1 */ +#define _EBI_WRTIMING1_RESETVALUE 0x00077F07UL /**< Default value for EBI_WRTIMING1 */ +#define _EBI_WRTIMING1_MASK 0x30077F07UL /**< Mask for EBI_WRTIMING1 */ +#define _EBI_WRTIMING1_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ +#define _EBI_WRTIMING1_WRSETUP_MASK 0x7UL /**< Bit mask for EBI_WRSETUP */ +#define _EBI_WRTIMING1_WRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING1 */ +#define EBI_WRTIMING1_WRSETUP_DEFAULT (_EBI_WRTIMING1_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ +#define _EBI_WRTIMING1_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ +#define _EBI_WRTIMING1_WRSTRB_MASK 0x7F00UL /**< Bit mask for EBI_WRSTRB */ +#define _EBI_WRTIMING1_WRSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_WRTIMING1 */ +#define EBI_WRTIMING1_WRSTRB_DEFAULT (_EBI_WRTIMING1_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ +#define _EBI_WRTIMING1_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ +#define _EBI_WRTIMING1_WRHOLD_MASK 0x70000UL /**< Bit mask for EBI_WRHOLD */ +#define _EBI_WRTIMING1_WRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING1 */ +#define EBI_WRTIMING1_WRHOLD_DEFAULT (_EBI_WRTIMING1_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ +#define EBI_WRTIMING1_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ +#define _EBI_WRTIMING1_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ +#define _EBI_WRTIMING1_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ +#define _EBI_WRTIMING1_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING1 */ +#define EBI_WRTIMING1_HALFWE_DEFAULT (_EBI_WRTIMING1_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ +#define EBI_WRTIMING1_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ +#define _EBI_WRTIMING1_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ +#define _EBI_WRTIMING1_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ +#define _EBI_WRTIMING1_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING1 */ +#define EBI_WRTIMING1_WBUFDIS_DEFAULT (_EBI_WRTIMING1_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ + +/* Bit fields for EBI POLARITY1 */ +#define _EBI_POLARITY1_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY1 */ +#define _EBI_POLARITY1_MASK 0x0000003FUL /**< Mask for EBI_POLARITY1 */ +#define EBI_POLARITY1_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ +#define _EBI_POLARITY1_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ +#define _EBI_POLARITY1_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ +#define _EBI_POLARITY1_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ +#define _EBI_POLARITY1_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ +#define _EBI_POLARITY1_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ +#define EBI_POLARITY1_CSPOL_DEFAULT (_EBI_POLARITY1_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ +#define EBI_POLARITY1_CSPOL_ACTIVELOW (_EBI_POLARITY1_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ +#define EBI_POLARITY1_CSPOL_ACTIVEHIGH (_EBI_POLARITY1_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ +#define EBI_POLARITY1_REPOL (0x1UL << 1) /**< Read Enable Polarity */ +#define _EBI_POLARITY1_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ +#define _EBI_POLARITY1_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ +#define _EBI_POLARITY1_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ +#define _EBI_POLARITY1_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ +#define _EBI_POLARITY1_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ +#define EBI_POLARITY1_REPOL_DEFAULT (_EBI_POLARITY1_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ +#define EBI_POLARITY1_REPOL_ACTIVELOW (_EBI_POLARITY1_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ +#define EBI_POLARITY1_REPOL_ACTIVEHIGH (_EBI_POLARITY1_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ +#define EBI_POLARITY1_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ +#define _EBI_POLARITY1_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ +#define _EBI_POLARITY1_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ +#define _EBI_POLARITY1_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ +#define _EBI_POLARITY1_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ +#define _EBI_POLARITY1_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ +#define EBI_POLARITY1_WEPOL_DEFAULT (_EBI_POLARITY1_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ +#define EBI_POLARITY1_WEPOL_ACTIVELOW (_EBI_POLARITY1_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ +#define EBI_POLARITY1_WEPOL_ACTIVEHIGH (_EBI_POLARITY1_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ +#define EBI_POLARITY1_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ +#define _EBI_POLARITY1_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ +#define _EBI_POLARITY1_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ +#define _EBI_POLARITY1_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ +#define _EBI_POLARITY1_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ +#define _EBI_POLARITY1_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ +#define EBI_POLARITY1_ALEPOL_DEFAULT (_EBI_POLARITY1_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ +#define EBI_POLARITY1_ALEPOL_ACTIVELOW (_EBI_POLARITY1_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ +#define EBI_POLARITY1_ALEPOL_ACTIVEHIGH (_EBI_POLARITY1_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ +#define EBI_POLARITY1_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ +#define _EBI_POLARITY1_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ +#define _EBI_POLARITY1_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ +#define _EBI_POLARITY1_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ +#define _EBI_POLARITY1_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ +#define _EBI_POLARITY1_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ +#define EBI_POLARITY1_ARDYPOL_DEFAULT (_EBI_POLARITY1_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ +#define EBI_POLARITY1_ARDYPOL_ACTIVELOW (_EBI_POLARITY1_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ +#define EBI_POLARITY1_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY1_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ +#define EBI_POLARITY1_BLPOL (0x1UL << 5) /**< BL Polarity */ +#define _EBI_POLARITY1_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ +#define _EBI_POLARITY1_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ +#define _EBI_POLARITY1_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ +#define _EBI_POLARITY1_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ +#define _EBI_POLARITY1_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ +#define EBI_POLARITY1_BLPOL_DEFAULT (_EBI_POLARITY1_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ +#define EBI_POLARITY1_BLPOL_ACTIVELOW (_EBI_POLARITY1_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ +#define EBI_POLARITY1_BLPOL_ACTIVEHIGH (_EBI_POLARITY1_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ + +/* Bit fields for EBI ADDRTIMING2 */ +#define _EBI_ADDRTIMING2_RESETVALUE 0x00000707UL /**< Default value for EBI_ADDRTIMING2 */ +#define _EBI_ADDRTIMING2_MASK 0x10000707UL /**< Mask for EBI_ADDRTIMING2 */ +#define _EBI_ADDRTIMING2_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ +#define _EBI_ADDRTIMING2_ADDRSETUP_MASK 0x7UL /**< Bit mask for EBI_ADDRSETUP */ +#define _EBI_ADDRTIMING2_ADDRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */ +#define EBI_ADDRTIMING2_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING2_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */ +#define _EBI_ADDRTIMING2_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ +#define _EBI_ADDRTIMING2_ADDRHOLD_MASK 0x700UL /**< Bit mask for EBI_ADDRHOLD */ +#define _EBI_ADDRTIMING2_ADDRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */ +#define EBI_ADDRTIMING2_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING2_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */ +#define EBI_ADDRTIMING2_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ +#define _EBI_ADDRTIMING2_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ +#define _EBI_ADDRTIMING2_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ +#define _EBI_ADDRTIMING2_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */ +#define EBI_ADDRTIMING2_HALFALE_DEFAULT (_EBI_ADDRTIMING2_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */ + +/* Bit fields for EBI RDTIMING2 */ +#define _EBI_RDTIMING2_RESETVALUE 0x00077F07UL /**< Default value for EBI_RDTIMING2 */ +#define _EBI_RDTIMING2_MASK 0x70077F07UL /**< Mask for EBI_RDTIMING2 */ +#define _EBI_RDTIMING2_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ +#define _EBI_RDTIMING2_RDSETUP_MASK 0x7UL /**< Bit mask for EBI_RDSETUP */ +#define _EBI_RDTIMING2_RDSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING2 */ +#define EBI_RDTIMING2_RDSETUP_DEFAULT (_EBI_RDTIMING2_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ +#define _EBI_RDTIMING2_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ +#define _EBI_RDTIMING2_RDSTRB_MASK 0x7F00UL /**< Bit mask for EBI_RDSTRB */ +#define _EBI_RDTIMING2_RDSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_RDTIMING2 */ +#define EBI_RDTIMING2_RDSTRB_DEFAULT (_EBI_RDTIMING2_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ +#define _EBI_RDTIMING2_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ +#define _EBI_RDTIMING2_RDHOLD_MASK 0x70000UL /**< Bit mask for EBI_RDHOLD */ +#define _EBI_RDTIMING2_RDHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING2 */ +#define EBI_RDTIMING2_RDHOLD_DEFAULT (_EBI_RDTIMING2_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ +#define EBI_RDTIMING2_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ +#define _EBI_RDTIMING2_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ +#define _EBI_RDTIMING2_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ +#define _EBI_RDTIMING2_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */ +#define EBI_RDTIMING2_HALFRE_DEFAULT (_EBI_RDTIMING2_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ +#define EBI_RDTIMING2_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ +#define _EBI_RDTIMING2_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ +#define _EBI_RDTIMING2_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ +#define _EBI_RDTIMING2_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */ +#define EBI_RDTIMING2_PREFETCH_DEFAULT (_EBI_RDTIMING2_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ +#define EBI_RDTIMING2_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ +#define _EBI_RDTIMING2_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ +#define _EBI_RDTIMING2_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ +#define _EBI_RDTIMING2_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */ +#define EBI_RDTIMING2_PAGEMODE_DEFAULT (_EBI_RDTIMING2_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ + +/* Bit fields for EBI WRTIMING2 */ +#define _EBI_WRTIMING2_RESETVALUE 0x00077F07UL /**< Default value for EBI_WRTIMING2 */ +#define _EBI_WRTIMING2_MASK 0x30077F07UL /**< Mask for EBI_WRTIMING2 */ +#define _EBI_WRTIMING2_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ +#define _EBI_WRTIMING2_WRSETUP_MASK 0x7UL /**< Bit mask for EBI_WRSETUP */ +#define _EBI_WRTIMING2_WRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING2 */ +#define EBI_WRTIMING2_WRSETUP_DEFAULT (_EBI_WRTIMING2_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ +#define _EBI_WRTIMING2_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ +#define _EBI_WRTIMING2_WRSTRB_MASK 0x7F00UL /**< Bit mask for EBI_WRSTRB */ +#define _EBI_WRTIMING2_WRSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_WRTIMING2 */ +#define EBI_WRTIMING2_WRSTRB_DEFAULT (_EBI_WRTIMING2_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ +#define _EBI_WRTIMING2_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ +#define _EBI_WRTIMING2_WRHOLD_MASK 0x70000UL /**< Bit mask for EBI_WRHOLD */ +#define _EBI_WRTIMING2_WRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING2 */ +#define EBI_WRTIMING2_WRHOLD_DEFAULT (_EBI_WRTIMING2_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ +#define EBI_WRTIMING2_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ +#define _EBI_WRTIMING2_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ +#define _EBI_WRTIMING2_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ +#define _EBI_WRTIMING2_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING2 */ +#define EBI_WRTIMING2_HALFWE_DEFAULT (_EBI_WRTIMING2_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ +#define EBI_WRTIMING2_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ +#define _EBI_WRTIMING2_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ +#define _EBI_WRTIMING2_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ +#define _EBI_WRTIMING2_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING2 */ +#define EBI_WRTIMING2_WBUFDIS_DEFAULT (_EBI_WRTIMING2_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ + +/* Bit fields for EBI POLARITY2 */ +#define _EBI_POLARITY2_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY2 */ +#define _EBI_POLARITY2_MASK 0x0000003FUL /**< Mask for EBI_POLARITY2 */ +#define EBI_POLARITY2_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ +#define _EBI_POLARITY2_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ +#define _EBI_POLARITY2_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ +#define _EBI_POLARITY2_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ +#define _EBI_POLARITY2_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ +#define _EBI_POLARITY2_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ +#define EBI_POLARITY2_CSPOL_DEFAULT (_EBI_POLARITY2_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ +#define EBI_POLARITY2_CSPOL_ACTIVELOW (_EBI_POLARITY2_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ +#define EBI_POLARITY2_CSPOL_ACTIVEHIGH (_EBI_POLARITY2_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ +#define EBI_POLARITY2_REPOL (0x1UL << 1) /**< Read Enable Polarity */ +#define _EBI_POLARITY2_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ +#define _EBI_POLARITY2_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ +#define _EBI_POLARITY2_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ +#define _EBI_POLARITY2_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ +#define _EBI_POLARITY2_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ +#define EBI_POLARITY2_REPOL_DEFAULT (_EBI_POLARITY2_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ +#define EBI_POLARITY2_REPOL_ACTIVELOW (_EBI_POLARITY2_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ +#define EBI_POLARITY2_REPOL_ACTIVEHIGH (_EBI_POLARITY2_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ +#define EBI_POLARITY2_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ +#define _EBI_POLARITY2_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ +#define _EBI_POLARITY2_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ +#define _EBI_POLARITY2_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ +#define _EBI_POLARITY2_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ +#define _EBI_POLARITY2_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ +#define EBI_POLARITY2_WEPOL_DEFAULT (_EBI_POLARITY2_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ +#define EBI_POLARITY2_WEPOL_ACTIVELOW (_EBI_POLARITY2_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ +#define EBI_POLARITY2_WEPOL_ACTIVEHIGH (_EBI_POLARITY2_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ +#define EBI_POLARITY2_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ +#define _EBI_POLARITY2_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ +#define _EBI_POLARITY2_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ +#define _EBI_POLARITY2_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ +#define _EBI_POLARITY2_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ +#define _EBI_POLARITY2_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ +#define EBI_POLARITY2_ALEPOL_DEFAULT (_EBI_POLARITY2_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ +#define EBI_POLARITY2_ALEPOL_ACTIVELOW (_EBI_POLARITY2_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ +#define EBI_POLARITY2_ALEPOL_ACTIVEHIGH (_EBI_POLARITY2_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ +#define EBI_POLARITY2_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ +#define _EBI_POLARITY2_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ +#define _EBI_POLARITY2_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ +#define _EBI_POLARITY2_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ +#define _EBI_POLARITY2_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ +#define _EBI_POLARITY2_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ +#define EBI_POLARITY2_ARDYPOL_DEFAULT (_EBI_POLARITY2_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ +#define EBI_POLARITY2_ARDYPOL_ACTIVELOW (_EBI_POLARITY2_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ +#define EBI_POLARITY2_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY2_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ +#define EBI_POLARITY2_BLPOL (0x1UL << 5) /**< BL Polarity */ +#define _EBI_POLARITY2_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ +#define _EBI_POLARITY2_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ +#define _EBI_POLARITY2_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ +#define _EBI_POLARITY2_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ +#define _EBI_POLARITY2_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ +#define EBI_POLARITY2_BLPOL_DEFAULT (_EBI_POLARITY2_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ +#define EBI_POLARITY2_BLPOL_ACTIVELOW (_EBI_POLARITY2_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ +#define EBI_POLARITY2_BLPOL_ACTIVEHIGH (_EBI_POLARITY2_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ + +/* Bit fields for EBI ADDRTIMING3 */ +#define _EBI_ADDRTIMING3_RESETVALUE 0x00000707UL /**< Default value for EBI_ADDRTIMING3 */ +#define _EBI_ADDRTIMING3_MASK 0x10000707UL /**< Mask for EBI_ADDRTIMING3 */ +#define _EBI_ADDRTIMING3_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ +#define _EBI_ADDRTIMING3_ADDRSETUP_MASK 0x7UL /**< Bit mask for EBI_ADDRSETUP */ +#define _EBI_ADDRTIMING3_ADDRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */ +#define EBI_ADDRTIMING3_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING3_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */ +#define _EBI_ADDRTIMING3_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ +#define _EBI_ADDRTIMING3_ADDRHOLD_MASK 0x700UL /**< Bit mask for EBI_ADDRHOLD */ +#define _EBI_ADDRTIMING3_ADDRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */ +#define EBI_ADDRTIMING3_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING3_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */ +#define EBI_ADDRTIMING3_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ +#define _EBI_ADDRTIMING3_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ +#define _EBI_ADDRTIMING3_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ +#define _EBI_ADDRTIMING3_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */ +#define EBI_ADDRTIMING3_HALFALE_DEFAULT (_EBI_ADDRTIMING3_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */ + +/* Bit fields for EBI RDTIMING3 */ +#define _EBI_RDTIMING3_RESETVALUE 0x00077F07UL /**< Default value for EBI_RDTIMING3 */ +#define _EBI_RDTIMING3_MASK 0x70077F07UL /**< Mask for EBI_RDTIMING3 */ +#define _EBI_RDTIMING3_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ +#define _EBI_RDTIMING3_RDSETUP_MASK 0x7UL /**< Bit mask for EBI_RDSETUP */ +#define _EBI_RDTIMING3_RDSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING3 */ +#define EBI_RDTIMING3_RDSETUP_DEFAULT (_EBI_RDTIMING3_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ +#define _EBI_RDTIMING3_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ +#define _EBI_RDTIMING3_RDSTRB_MASK 0x7F00UL /**< Bit mask for EBI_RDSTRB */ +#define _EBI_RDTIMING3_RDSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_RDTIMING3 */ +#define EBI_RDTIMING3_RDSTRB_DEFAULT (_EBI_RDTIMING3_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ +#define _EBI_RDTIMING3_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ +#define _EBI_RDTIMING3_RDHOLD_MASK 0x70000UL /**< Bit mask for EBI_RDHOLD */ +#define _EBI_RDTIMING3_RDHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING3 */ +#define EBI_RDTIMING3_RDHOLD_DEFAULT (_EBI_RDTIMING3_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ +#define EBI_RDTIMING3_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ +#define _EBI_RDTIMING3_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ +#define _EBI_RDTIMING3_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ +#define _EBI_RDTIMING3_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */ +#define EBI_RDTIMING3_HALFRE_DEFAULT (_EBI_RDTIMING3_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ +#define EBI_RDTIMING3_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ +#define _EBI_RDTIMING3_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ +#define _EBI_RDTIMING3_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ +#define _EBI_RDTIMING3_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */ +#define EBI_RDTIMING3_PREFETCH_DEFAULT (_EBI_RDTIMING3_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ +#define EBI_RDTIMING3_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ +#define _EBI_RDTIMING3_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ +#define _EBI_RDTIMING3_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ +#define _EBI_RDTIMING3_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */ +#define EBI_RDTIMING3_PAGEMODE_DEFAULT (_EBI_RDTIMING3_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ + +/* Bit fields for EBI WRTIMING3 */ +#define _EBI_WRTIMING3_RESETVALUE 0x00077F07UL /**< Default value for EBI_WRTIMING3 */ +#define _EBI_WRTIMING3_MASK 0x30077F07UL /**< Mask for EBI_WRTIMING3 */ +#define _EBI_WRTIMING3_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ +#define _EBI_WRTIMING3_WRSETUP_MASK 0x7UL /**< Bit mask for EBI_WRSETUP */ +#define _EBI_WRTIMING3_WRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING3 */ +#define EBI_WRTIMING3_WRSETUP_DEFAULT (_EBI_WRTIMING3_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ +#define _EBI_WRTIMING3_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ +#define _EBI_WRTIMING3_WRSTRB_MASK 0x7F00UL /**< Bit mask for EBI_WRSTRB */ +#define _EBI_WRTIMING3_WRSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_WRTIMING3 */ +#define EBI_WRTIMING3_WRSTRB_DEFAULT (_EBI_WRTIMING3_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ +#define _EBI_WRTIMING3_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ +#define _EBI_WRTIMING3_WRHOLD_MASK 0x70000UL /**< Bit mask for EBI_WRHOLD */ +#define _EBI_WRTIMING3_WRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING3 */ +#define EBI_WRTIMING3_WRHOLD_DEFAULT (_EBI_WRTIMING3_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ +#define EBI_WRTIMING3_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ +#define _EBI_WRTIMING3_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ +#define _EBI_WRTIMING3_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ +#define _EBI_WRTIMING3_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING3 */ +#define EBI_WRTIMING3_HALFWE_DEFAULT (_EBI_WRTIMING3_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ +#define EBI_WRTIMING3_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ +#define _EBI_WRTIMING3_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ +#define _EBI_WRTIMING3_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ +#define _EBI_WRTIMING3_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING3 */ +#define EBI_WRTIMING3_WBUFDIS_DEFAULT (_EBI_WRTIMING3_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ + +/* Bit fields for EBI POLARITY3 */ +#define _EBI_POLARITY3_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY3 */ +#define _EBI_POLARITY3_MASK 0x0000003FUL /**< Mask for EBI_POLARITY3 */ +#define EBI_POLARITY3_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ +#define _EBI_POLARITY3_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ +#define _EBI_POLARITY3_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ +#define _EBI_POLARITY3_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ +#define _EBI_POLARITY3_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ +#define _EBI_POLARITY3_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ +#define EBI_POLARITY3_CSPOL_DEFAULT (_EBI_POLARITY3_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ +#define EBI_POLARITY3_CSPOL_ACTIVELOW (_EBI_POLARITY3_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ +#define EBI_POLARITY3_CSPOL_ACTIVEHIGH (_EBI_POLARITY3_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ +#define EBI_POLARITY3_REPOL (0x1UL << 1) /**< Read Enable Polarity */ +#define _EBI_POLARITY3_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ +#define _EBI_POLARITY3_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ +#define _EBI_POLARITY3_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ +#define _EBI_POLARITY3_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ +#define _EBI_POLARITY3_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ +#define EBI_POLARITY3_REPOL_DEFAULT (_EBI_POLARITY3_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ +#define EBI_POLARITY3_REPOL_ACTIVELOW (_EBI_POLARITY3_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ +#define EBI_POLARITY3_REPOL_ACTIVEHIGH (_EBI_POLARITY3_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ +#define EBI_POLARITY3_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ +#define _EBI_POLARITY3_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ +#define _EBI_POLARITY3_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ +#define _EBI_POLARITY3_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ +#define _EBI_POLARITY3_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ +#define _EBI_POLARITY3_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ +#define EBI_POLARITY3_WEPOL_DEFAULT (_EBI_POLARITY3_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ +#define EBI_POLARITY3_WEPOL_ACTIVELOW (_EBI_POLARITY3_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ +#define EBI_POLARITY3_WEPOL_ACTIVEHIGH (_EBI_POLARITY3_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ +#define EBI_POLARITY3_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ +#define _EBI_POLARITY3_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ +#define _EBI_POLARITY3_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ +#define _EBI_POLARITY3_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ +#define _EBI_POLARITY3_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ +#define _EBI_POLARITY3_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ +#define EBI_POLARITY3_ALEPOL_DEFAULT (_EBI_POLARITY3_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ +#define EBI_POLARITY3_ALEPOL_ACTIVELOW (_EBI_POLARITY3_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ +#define EBI_POLARITY3_ALEPOL_ACTIVEHIGH (_EBI_POLARITY3_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ +#define EBI_POLARITY3_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ +#define _EBI_POLARITY3_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ +#define _EBI_POLARITY3_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ +#define _EBI_POLARITY3_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ +#define _EBI_POLARITY3_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ +#define _EBI_POLARITY3_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ +#define EBI_POLARITY3_ARDYPOL_DEFAULT (_EBI_POLARITY3_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ +#define EBI_POLARITY3_ARDYPOL_ACTIVELOW (_EBI_POLARITY3_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ +#define EBI_POLARITY3_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY3_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ +#define EBI_POLARITY3_BLPOL (0x1UL << 5) /**< BL Polarity */ +#define _EBI_POLARITY3_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ +#define _EBI_POLARITY3_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ +#define _EBI_POLARITY3_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ +#define _EBI_POLARITY3_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ +#define _EBI_POLARITY3_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ +#define EBI_POLARITY3_BLPOL_DEFAULT (_EBI_POLARITY3_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ +#define EBI_POLARITY3_BLPOL_ACTIVELOW (_EBI_POLARITY3_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ +#define EBI_POLARITY3_BLPOL_ACTIVEHIGH (_EBI_POLARITY3_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ + +/* Bit fields for EBI PAGECTRL */ +#define _EBI_PAGECTRL_RESETVALUE 0x00000F00UL /**< Default value for EBI_PAGECTRL */ +#define _EBI_PAGECTRL_MASK 0x07F00F13UL /**< Mask for EBI_PAGECTRL */ +#define _EBI_PAGECTRL_PAGELEN_SHIFT 0 /**< Shift value for EBI_PAGELEN */ +#define _EBI_PAGECTRL_PAGELEN_MASK 0x3UL /**< Bit mask for EBI_PAGELEN */ +#define _EBI_PAGECTRL_PAGELEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */ +#define _EBI_PAGECTRL_PAGELEN_MEMBER4 0x00000000UL /**< Mode MEMBER4 for EBI_PAGECTRL */ +#define _EBI_PAGECTRL_PAGELEN_MEMBER8 0x00000001UL /**< Mode MEMBER8 for EBI_PAGECTRL */ +#define _EBI_PAGECTRL_PAGELEN_MEMBER16 0x00000002UL /**< Mode MEMBER16 for EBI_PAGECTRL */ +#define _EBI_PAGECTRL_PAGELEN_MEMBER32 0x00000003UL /**< Mode MEMBER32 for EBI_PAGECTRL */ +#define EBI_PAGECTRL_PAGELEN_DEFAULT (_EBI_PAGECTRL_PAGELEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ +#define EBI_PAGECTRL_PAGELEN_MEMBER4 (_EBI_PAGECTRL_PAGELEN_MEMBER4 << 0) /**< Shifted mode MEMBER4 for EBI_PAGECTRL */ +#define EBI_PAGECTRL_PAGELEN_MEMBER8 (_EBI_PAGECTRL_PAGELEN_MEMBER8 << 0) /**< Shifted mode MEMBER8 for EBI_PAGECTRL */ +#define EBI_PAGECTRL_PAGELEN_MEMBER16 (_EBI_PAGECTRL_PAGELEN_MEMBER16 << 0) /**< Shifted mode MEMBER16 for EBI_PAGECTRL */ +#define EBI_PAGECTRL_PAGELEN_MEMBER32 (_EBI_PAGECTRL_PAGELEN_MEMBER32 << 0) /**< Shifted mode MEMBER32 for EBI_PAGECTRL */ +#define EBI_PAGECTRL_INCHIT (0x1UL << 4) /**< Intrapage Hit Only on Incremental Addresses */ +#define _EBI_PAGECTRL_INCHIT_SHIFT 4 /**< Shift value for EBI_INCHIT */ +#define _EBI_PAGECTRL_INCHIT_MASK 0x10UL /**< Bit mask for EBI_INCHIT */ +#define _EBI_PAGECTRL_INCHIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */ +#define EBI_PAGECTRL_INCHIT_DEFAULT (_EBI_PAGECTRL_INCHIT_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ +#define _EBI_PAGECTRL_RDPA_SHIFT 8 /**< Shift value for EBI_RDPA */ +#define _EBI_PAGECTRL_RDPA_MASK 0xF00UL /**< Bit mask for EBI_RDPA */ +#define _EBI_PAGECTRL_RDPA_DEFAULT 0x0000000FUL /**< Mode DEFAULT for EBI_PAGECTRL */ +#define EBI_PAGECTRL_RDPA_DEFAULT (_EBI_PAGECTRL_RDPA_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ +#define _EBI_PAGECTRL_KEEPOPEN_SHIFT 20 /**< Shift value for EBI_KEEPOPEN */ +#define _EBI_PAGECTRL_KEEPOPEN_MASK 0x7F00000UL /**< Bit mask for EBI_KEEPOPEN */ +#define _EBI_PAGECTRL_KEEPOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */ +#define EBI_PAGECTRL_KEEPOPEN_DEFAULT (_EBI_PAGECTRL_KEEPOPEN_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ + +/* Bit fields for EBI NANDCTRL */ +#define _EBI_NANDCTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_NANDCTRL */ +#define _EBI_NANDCTRL_MASK 0x00000031UL /**< Mask for EBI_NANDCTRL */ +#define EBI_NANDCTRL_EN (0x1UL << 0) /**< NAND Flash Control Enable */ +#define _EBI_NANDCTRL_EN_SHIFT 0 /**< Shift value for EBI_EN */ +#define _EBI_NANDCTRL_EN_MASK 0x1UL /**< Bit mask for EBI_EN */ +#define _EBI_NANDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_NANDCTRL */ +#define EBI_NANDCTRL_EN_DEFAULT (_EBI_NANDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_NANDCTRL */ +#define _EBI_NANDCTRL_BANKSEL_SHIFT 4 /**< Shift value for EBI_BANKSEL */ +#define _EBI_NANDCTRL_BANKSEL_MASK 0x30UL /**< Bit mask for EBI_BANKSEL */ +#define _EBI_NANDCTRL_BANKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_NANDCTRL */ +#define _EBI_NANDCTRL_BANKSEL_BANK0 0x00000000UL /**< Mode BANK0 for EBI_NANDCTRL */ +#define _EBI_NANDCTRL_BANKSEL_BANK1 0x00000001UL /**< Mode BANK1 for EBI_NANDCTRL */ +#define _EBI_NANDCTRL_BANKSEL_BANK2 0x00000002UL /**< Mode BANK2 for EBI_NANDCTRL */ +#define _EBI_NANDCTRL_BANKSEL_BANK3 0x00000003UL /**< Mode BANK3 for EBI_NANDCTRL */ +#define EBI_NANDCTRL_BANKSEL_DEFAULT (_EBI_NANDCTRL_BANKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_NANDCTRL */ +#define EBI_NANDCTRL_BANKSEL_BANK0 (_EBI_NANDCTRL_BANKSEL_BANK0 << 4) /**< Shifted mode BANK0 for EBI_NANDCTRL */ +#define EBI_NANDCTRL_BANKSEL_BANK1 (_EBI_NANDCTRL_BANKSEL_BANK1 << 4) /**< Shifted mode BANK1 for EBI_NANDCTRL */ +#define EBI_NANDCTRL_BANKSEL_BANK2 (_EBI_NANDCTRL_BANKSEL_BANK2 << 4) /**< Shifted mode BANK2 for EBI_NANDCTRL */ +#define EBI_NANDCTRL_BANKSEL_BANK3 (_EBI_NANDCTRL_BANKSEL_BANK3 << 4) /**< Shifted mode BANK3 for EBI_NANDCTRL */ + +/* Bit fields for EBI CMD */ +#define _EBI_CMD_RESETVALUE 0x00000000UL /**< Default value for EBI_CMD */ +#define _EBI_CMD_MASK 0x00000007UL /**< Mask for EBI_CMD */ +#define EBI_CMD_ECCSTART (0x1UL << 0) /**< Error Correction Code Generation Start */ +#define _EBI_CMD_ECCSTART_SHIFT 0 /**< Shift value for EBI_ECCSTART */ +#define _EBI_CMD_ECCSTART_MASK 0x1UL /**< Bit mask for EBI_ECCSTART */ +#define _EBI_CMD_ECCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */ +#define EBI_CMD_ECCSTART_DEFAULT (_EBI_CMD_ECCSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CMD */ +#define EBI_CMD_ECCSTOP (0x1UL << 1) /**< Error Correction Code Generation Stop */ +#define _EBI_CMD_ECCSTOP_SHIFT 1 /**< Shift value for EBI_ECCSTOP */ +#define _EBI_CMD_ECCSTOP_MASK 0x2UL /**< Bit mask for EBI_ECCSTOP */ +#define _EBI_CMD_ECCSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */ +#define EBI_CMD_ECCSTOP_DEFAULT (_EBI_CMD_ECCSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_CMD */ +#define EBI_CMD_ECCCLEAR (0x1UL << 2) /**< Error Correction Code Clear */ +#define _EBI_CMD_ECCCLEAR_SHIFT 2 /**< Shift value for EBI_ECCCLEAR */ +#define _EBI_CMD_ECCCLEAR_MASK 0x4UL /**< Bit mask for EBI_ECCCLEAR */ +#define _EBI_CMD_ECCCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */ +#define EBI_CMD_ECCCLEAR_DEFAULT (_EBI_CMD_ECCCLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_CMD */ + +/* Bit fields for EBI STATUS */ +#define _EBI_STATUS_RESETVALUE 0x00000000UL /**< Default value for EBI_STATUS */ +#define _EBI_STATUS_MASK 0x00003711UL /**< Mask for EBI_STATUS */ +#define EBI_STATUS_AHBACT (0x1UL << 0) /**< EBI Busy With AHB Transaction */ +#define _EBI_STATUS_AHBACT_SHIFT 0 /**< Shift value for EBI_AHBACT */ +#define _EBI_STATUS_AHBACT_MASK 0x1UL /**< Bit mask for EBI_AHBACT */ +#define _EBI_STATUS_AHBACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_AHBACT_DEFAULT (_EBI_STATUS_AHBACT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_ECCACT (0x1UL << 4) /**< EBI ECC Generation Active */ +#define _EBI_STATUS_ECCACT_SHIFT 4 /**< Shift value for EBI_ECCACT */ +#define _EBI_STATUS_ECCACT_MASK 0x10UL /**< Bit mask for EBI_ECCACT */ +#define _EBI_STATUS_ECCACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_ECCACT_DEFAULT (_EBI_STATUS_ECCACT_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_TFTPIXEL0EMPTY (0x1UL << 8) /**< EBI_TFTPIXEL0 is Empty */ +#define _EBI_STATUS_TFTPIXEL0EMPTY_SHIFT 8 /**< Shift value for EBI_TFTPIXEL0EMPTY */ +#define _EBI_STATUS_TFTPIXEL0EMPTY_MASK 0x100UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */ +#define _EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_TFTPIXEL1EMPTY (0x1UL << 9) /**< EBI_TFTPIXEL1 is Empty */ +#define _EBI_STATUS_TFTPIXEL1EMPTY_SHIFT 9 /**< Shift value for EBI_TFTPIXEL1EMPTY */ +#define _EBI_STATUS_TFTPIXEL1EMPTY_MASK 0x200UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */ +#define _EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_TFTPIXELFULL (0x1UL << 10) /**< EBI_TFTPIXEL0 is Full */ +#define _EBI_STATUS_TFTPIXELFULL_SHIFT 10 /**< Shift value for EBI_TFTPIXELFULL */ +#define _EBI_STATUS_TFTPIXELFULL_MASK 0x400UL /**< Bit mask for EBI_TFTPIXELFULL */ +#define _EBI_STATUS_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_TFTPIXELFULL_DEFAULT (_EBI_STATUS_TFTPIXELFULL_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_DDACT (0x1UL << 12) /**< EBI Busy With Direct Drive Transactions */ +#define _EBI_STATUS_DDACT_SHIFT 12 /**< Shift value for EBI_DDACT */ +#define _EBI_STATUS_DDACT_MASK 0x1000UL /**< Bit mask for EBI_DDACT */ +#define _EBI_STATUS_DDACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_DDACT_DEFAULT (_EBI_STATUS_DDACT_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_TFTDDEMPTY (0x1UL << 13) /**< EBI_TFTDD Register is Empty */ +#define _EBI_STATUS_TFTDDEMPTY_SHIFT 13 /**< Shift value for EBI_TFTDDEMPTY */ +#define _EBI_STATUS_TFTDDEMPTY_MASK 0x2000UL /**< Bit mask for EBI_TFTDDEMPTY */ +#define _EBI_STATUS_TFTDDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ +#define EBI_STATUS_TFTDDEMPTY_DEFAULT (_EBI_STATUS_TFTDDEMPTY_DEFAULT << 13) /**< Shifted mode DEFAULT for EBI_STATUS */ + +/* Bit fields for EBI ECCPARITY */ +#define _EBI_ECCPARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_ECCPARITY */ +#define _EBI_ECCPARITY_MASK 0xFFFFFFFFUL /**< Mask for EBI_ECCPARITY */ +#define _EBI_ECCPARITY_ECCPARITY_SHIFT 0 /**< Shift value for EBI_ECCPARITY */ +#define _EBI_ECCPARITY_ECCPARITY_MASK 0xFFFFFFFFUL /**< Bit mask for EBI_ECCPARITY */ +#define _EBI_ECCPARITY_ECCPARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ECCPARITY */ +#define EBI_ECCPARITY_ECCPARITY_DEFAULT (_EBI_ECCPARITY_ECCPARITY_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ECCPARITY */ + +/* Bit fields for EBI TFTCTRL */ +#define _EBI_TFTCTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASK 0x00FB1F3FUL /**< Mask for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_DD_SHIFT 0 /**< Shift value for EBI_DD */ +#define _EBI_TFTCTRL_DD_MASK 0x3UL /**< Bit mask for EBI_DD */ +#define _EBI_TFTCTRL_DD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_DD_DISABLED 0x00000000UL /**< Mode DISABLED for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_DD_INTERNAL 0x00000001UL /**< Mode INTERNAL for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_DD_EXTERNAL 0x00000002UL /**< Mode EXTERNAL for EBI_TFTCTRL */ +#define EBI_TFTCTRL_DD_DEFAULT (_EBI_TFTCTRL_DD_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ +#define EBI_TFTCTRL_DD_DISABLED (_EBI_TFTCTRL_DD_DISABLED << 0) /**< Shifted mode DISABLED for EBI_TFTCTRL */ +#define EBI_TFTCTRL_DD_INTERNAL (_EBI_TFTCTRL_DD_INTERNAL << 0) /**< Shifted mode INTERNAL for EBI_TFTCTRL */ +#define EBI_TFTCTRL_DD_EXTERNAL (_EBI_TFTCTRL_DD_EXTERNAL << 0) /**< Shifted mode EXTERNAL for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASKBLEND_SHIFT 2 /**< Shift value for EBI_MASKBLEND */ +#define _EBI_TFTCTRL_MASKBLEND_MASK 0x3CUL /**< Bit mask for EBI_MASKBLEND */ +#define _EBI_TFTCTRL_MASKBLEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASKBLEND_DISABLED 0x00000000UL /**< Mode DISABLED for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASKBLEND_IMASK 0x00000001UL /**< Mode IMASK for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASKBLEND_IALPHA 0x00000002UL /**< Mode IALPHA for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASKBLEND_IMASKALPHA 0x00000003UL /**< Mode IMASKALPHA for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASKBLEND_EFBMASK 0x00000004UL /**< Mode EFBMASK for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASKBLEND_EFBALPHA 0x00000005UL /**< Mode EFBALPHA for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASKBLEND_EFBMASKALPHA 0x00000006UL /**< Mode EFBMASKALPHA for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASKBLEND_IFBMASK 0x00000007UL /**< Mode IFBMASK for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASKBLEND_IFBALPHA 0x00000008UL /**< Mode IFBALPHA for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_MASKBLEND_IFBMASKALPHA 0x00000009UL /**< Mode IFBMASKALPHA for EBI_TFTCTRL */ +#define EBI_TFTCTRL_MASKBLEND_DEFAULT (_EBI_TFTCTRL_MASKBLEND_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ +#define EBI_TFTCTRL_MASKBLEND_DISABLED (_EBI_TFTCTRL_MASKBLEND_DISABLED << 2) /**< Shifted mode DISABLED for EBI_TFTCTRL */ +#define EBI_TFTCTRL_MASKBLEND_IMASK (_EBI_TFTCTRL_MASKBLEND_IMASK << 2) /**< Shifted mode IMASK for EBI_TFTCTRL */ +#define EBI_TFTCTRL_MASKBLEND_IALPHA (_EBI_TFTCTRL_MASKBLEND_IALPHA << 2) /**< Shifted mode IALPHA for EBI_TFTCTRL */ +#define EBI_TFTCTRL_MASKBLEND_IMASKALPHA (_EBI_TFTCTRL_MASKBLEND_IMASKALPHA << 2) /**< Shifted mode IMASKALPHA for EBI_TFTCTRL */ +#define EBI_TFTCTRL_MASKBLEND_EFBMASK (_EBI_TFTCTRL_MASKBLEND_EFBMASK << 2) /**< Shifted mode EFBMASK for EBI_TFTCTRL */ +#define EBI_TFTCTRL_MASKBLEND_EFBALPHA (_EBI_TFTCTRL_MASKBLEND_EFBALPHA << 2) /**< Shifted mode EFBALPHA for EBI_TFTCTRL */ +#define EBI_TFTCTRL_MASKBLEND_EFBMASKALPHA (_EBI_TFTCTRL_MASKBLEND_EFBMASKALPHA << 2) /**< Shifted mode EFBMASKALPHA for EBI_TFTCTRL */ +#define EBI_TFTCTRL_MASKBLEND_IFBMASK (_EBI_TFTCTRL_MASKBLEND_IFBMASK << 2) /**< Shifted mode IFBMASK for EBI_TFTCTRL */ +#define EBI_TFTCTRL_MASKBLEND_IFBALPHA (_EBI_TFTCTRL_MASKBLEND_IFBALPHA << 2) /**< Shifted mode IFBALPHA for EBI_TFTCTRL */ +#define EBI_TFTCTRL_MASKBLEND_IFBMASKALPHA (_EBI_TFTCTRL_MASKBLEND_IFBMASKALPHA << 2) /**< Shifted mode IFBMASKALPHA for EBI_TFTCTRL */ +#define EBI_TFTCTRL_SHIFTDCLKEN (0x1UL << 8) /**< TFT EBI_DCLK Shift Enable */ +#define _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT 8 /**< Shift value for EBI_SHIFTDCLKEN */ +#define _EBI_TFTCTRL_SHIFTDCLKEN_MASK 0x100UL /**< Bit mask for EBI_SHIFTDCLKEN */ +#define _EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ +#define EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT (_EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ +#define EBI_TFTCTRL_FBCTRIG (0x1UL << 9) /**< TFT Frame Base Copy Trigger */ +#define _EBI_TFTCTRL_FBCTRIG_SHIFT 9 /**< Shift value for EBI_FBCTRIG */ +#define _EBI_TFTCTRL_FBCTRIG_MASK 0x200UL /**< Bit mask for EBI_FBCTRIG */ +#define _EBI_TFTCTRL_FBCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_FBCTRIG_VSYNC 0x00000000UL /**< Mode VSYNC for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_FBCTRIG_HSYNC 0x00000001UL /**< Mode HSYNC for EBI_TFTCTRL */ +#define EBI_TFTCTRL_FBCTRIG_DEFAULT (_EBI_TFTCTRL_FBCTRIG_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ +#define EBI_TFTCTRL_FBCTRIG_VSYNC (_EBI_TFTCTRL_FBCTRIG_VSYNC << 9) /**< Shifted mode VSYNC for EBI_TFTCTRL */ +#define EBI_TFTCTRL_FBCTRIG_HSYNC (_EBI_TFTCTRL_FBCTRIG_HSYNC << 9) /**< Shifted mode HSYNC for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_INTERLEAVE_SHIFT 10 /**< Shift value for EBI_INTERLEAVE */ +#define _EBI_TFTCTRL_INTERLEAVE_MASK 0xC00UL /**< Bit mask for EBI_INTERLEAVE */ +#define _EBI_TFTCTRL_INTERLEAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_INTERLEAVE_UNLIMITED 0x00000000UL /**< Mode UNLIMITED for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK 0x00000001UL /**< Mode ONEPERDCLK for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_INTERLEAVE_PORCH 0x00000002UL /**< Mode PORCH for EBI_TFTCTRL */ +#define EBI_TFTCTRL_INTERLEAVE_DEFAULT (_EBI_TFTCTRL_INTERLEAVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ +#define EBI_TFTCTRL_INTERLEAVE_UNLIMITED (_EBI_TFTCTRL_INTERLEAVE_UNLIMITED << 10) /**< Shifted mode UNLIMITED for EBI_TFTCTRL */ +#define EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK (_EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK << 10) /**< Shifted mode ONEPERDCLK for EBI_TFTCTRL */ +#define EBI_TFTCTRL_INTERLEAVE_PORCH (_EBI_TFTCTRL_INTERLEAVE_PORCH << 10) /**< Shifted mode PORCH for EBI_TFTCTRL */ +#define EBI_TFTCTRL_COLOR1SRC (0x1UL << 12) /**< Masking/Alpha Blending Color1 Source */ +#define _EBI_TFTCTRL_COLOR1SRC_SHIFT 12 /**< Shift value for EBI_COLOR1SRC */ +#define _EBI_TFTCTRL_COLOR1SRC_MASK 0x1000UL /**< Bit mask for EBI_COLOR1SRC */ +#define _EBI_TFTCTRL_COLOR1SRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_COLOR1SRC_MEM 0x00000000UL /**< Mode MEM for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_COLOR1SRC_PIXEL1 0x00000001UL /**< Mode PIXEL1 for EBI_TFTCTRL */ +#define EBI_TFTCTRL_COLOR1SRC_DEFAULT (_EBI_TFTCTRL_COLOR1SRC_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ +#define EBI_TFTCTRL_COLOR1SRC_MEM (_EBI_TFTCTRL_COLOR1SRC_MEM << 12) /**< Shifted mode MEM for EBI_TFTCTRL */ +#define EBI_TFTCTRL_COLOR1SRC_PIXEL1 (_EBI_TFTCTRL_COLOR1SRC_PIXEL1 << 12) /**< Shifted mode PIXEL1 for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_WIDTH_SHIFT 16 /**< Shift value for EBI_WIDTH */ +#define _EBI_TFTCTRL_WIDTH_MASK 0x30000UL /**< Bit mask for EBI_WIDTH */ +#define _EBI_TFTCTRL_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_WIDTH_BYTE 0x00000000UL /**< Mode BYTE for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_WIDTH_HALFWORD 0x00000001UL /**< Mode HALFWORD for EBI_TFTCTRL */ +#define EBI_TFTCTRL_WIDTH_DEFAULT (_EBI_TFTCTRL_WIDTH_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ +#define EBI_TFTCTRL_WIDTH_BYTE (_EBI_TFTCTRL_WIDTH_BYTE << 16) /**< Shifted mode BYTE for EBI_TFTCTRL */ +#define EBI_TFTCTRL_WIDTH_HALFWORD (_EBI_TFTCTRL_WIDTH_HALFWORD << 16) /**< Shifted mode HALFWORD for EBI_TFTCTRL */ +#define EBI_TFTCTRL_ALIASBANKEN (0x1UL << 19) /**< Alias to Graphics Bank Enable */ +#define _EBI_TFTCTRL_ALIASBANKEN_SHIFT 19 /**< Shift value for EBI_ALIASBANKEN */ +#define _EBI_TFTCTRL_ALIASBANKEN_MASK 0x80000UL /**< Bit mask for EBI_ALIASBANKEN */ +#define _EBI_TFTCTRL_ALIASBANKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_ALIASBANKEN_DISABLE 0x00000000UL /**< Mode DISABLE for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_ALIASBANKEN_ENABLE 0x00000001UL /**< Mode ENABLE for EBI_TFTCTRL */ +#define EBI_TFTCTRL_ALIASBANKEN_DEFAULT (_EBI_TFTCTRL_ALIASBANKEN_DEFAULT << 19) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ +#define EBI_TFTCTRL_ALIASBANKEN_DISABLE (_EBI_TFTCTRL_ALIASBANKEN_DISABLE << 19) /**< Shifted mode DISABLE for EBI_TFTCTRL */ +#define EBI_TFTCTRL_ALIASBANKEN_ENABLE (_EBI_TFTCTRL_ALIASBANKEN_ENABLE << 19) /**< Shifted mode ENABLE for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_BANKSEL_SHIFT 20 /**< Shift value for EBI_BANKSEL */ +#define _EBI_TFTCTRL_BANKSEL_MASK 0x300000UL /**< Bit mask for EBI_BANKSEL */ +#define _EBI_TFTCTRL_BANKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_BANKSEL_BANK0 0x00000000UL /**< Mode BANK0 for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_BANKSEL_BANK1 0x00000001UL /**< Mode BANK1 for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_BANKSEL_BANK2 0x00000002UL /**< Mode BANK2 for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_BANKSEL_BANK3 0x00000003UL /**< Mode BANK3 for EBI_TFTCTRL */ +#define EBI_TFTCTRL_BANKSEL_DEFAULT (_EBI_TFTCTRL_BANKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ +#define EBI_TFTCTRL_BANKSEL_BANK0 (_EBI_TFTCTRL_BANKSEL_BANK0 << 20) /**< Shifted mode BANK0 for EBI_TFTCTRL */ +#define EBI_TFTCTRL_BANKSEL_BANK1 (_EBI_TFTCTRL_BANKSEL_BANK1 << 20) /**< Shifted mode BANK1 for EBI_TFTCTRL */ +#define EBI_TFTCTRL_BANKSEL_BANK2 (_EBI_TFTCTRL_BANKSEL_BANK2 << 20) /**< Shifted mode BANK2 for EBI_TFTCTRL */ +#define EBI_TFTCTRL_BANKSEL_BANK3 (_EBI_TFTCTRL_BANKSEL_BANK3 << 20) /**< Shifted mode BANK3 for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_ALIASBANK_SHIFT 22 /**< Shift value for EBI_ALIASBANK */ +#define _EBI_TFTCTRL_ALIASBANK_MASK 0xC00000UL /**< Bit mask for EBI_ALIASBANK */ +#define _EBI_TFTCTRL_ALIASBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_ALIASBANK_ALIASBANK0 0x00000000UL /**< Mode ALIASBANK0 for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_ALIASBANK_ALIASBANK1 0x00000001UL /**< Mode ALIASBANK1 for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_ALIASBANK_ALIASBANK2 0x00000002UL /**< Mode ALIASBANK2 for EBI_TFTCTRL */ +#define _EBI_TFTCTRL_ALIASBANK_ALIASBANK3 0x00000003UL /**< Mode ALIASBANK3 for EBI_TFTCTRL */ +#define EBI_TFTCTRL_ALIASBANK_DEFAULT (_EBI_TFTCTRL_ALIASBANK_DEFAULT << 22) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ +#define EBI_TFTCTRL_ALIASBANK_ALIASBANK0 (_EBI_TFTCTRL_ALIASBANK_ALIASBANK0 << 22) /**< Shifted mode ALIASBANK0 for EBI_TFTCTRL */ +#define EBI_TFTCTRL_ALIASBANK_ALIASBANK1 (_EBI_TFTCTRL_ALIASBANK_ALIASBANK1 << 22) /**< Shifted mode ALIASBANK1 for EBI_TFTCTRL */ +#define EBI_TFTCTRL_ALIASBANK_ALIASBANK2 (_EBI_TFTCTRL_ALIASBANK_ALIASBANK2 << 22) /**< Shifted mode ALIASBANK2 for EBI_TFTCTRL */ +#define EBI_TFTCTRL_ALIASBANK_ALIASBANK3 (_EBI_TFTCTRL_ALIASBANK_ALIASBANK3 << 22) /**< Shifted mode ALIASBANK3 for EBI_TFTCTRL */ + +/* Bit fields for EBI TFTSTATUS */ +#define _EBI_TFTSTATUS_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSTATUS */ +#define _EBI_TFTSTATUS_MASK 0x7FFF07FFUL /**< Mask for EBI_TFTSTATUS */ +#define _EBI_TFTSTATUS_HCNT_SHIFT 0 /**< Shift value for EBI_HCNT */ +#define _EBI_TFTSTATUS_HCNT_MASK 0x7FFUL /**< Bit mask for EBI_HCNT */ +#define _EBI_TFTSTATUS_HCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTATUS */ +#define EBI_TFTSTATUS_HCNT_DEFAULT (_EBI_TFTSTATUS_HCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSTATUS */ +#define _EBI_TFTSTATUS_VCNT_SHIFT 16 /**< Shift value for EBI_VCNT */ +#define _EBI_TFTSTATUS_VCNT_MASK 0x7FFF0000UL /**< Bit mask for EBI_VCNT */ +#define _EBI_TFTSTATUS_VCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTATUS */ +#define EBI_TFTSTATUS_VCNT_DEFAULT (_EBI_TFTSTATUS_VCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSTATUS */ + +/* Bit fields for EBI TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_MASK 0x00000307UL /**< Mask for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_SHIFT 0 /**< Shift value for EBI_PIXEL0FORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_MASK 0x7UL /**< Bit mask for EBI_PIXEL0FORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0555 0x00000000UL /**< Mode ARGB0555 for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0565 0x00000001UL /**< Mode ARGB0565 for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0666 0x00000002UL /**< Mode ARGB0666 for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0888 0x00000003UL /**< Mode ARGB0888 for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB5555 0x00000004UL /**< Mode ARGB5555 for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6565 0x00000005UL /**< Mode ARGB6565 for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6666 0x00000006UL /**< Mode ARGB6666 for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB8888 0x00000007UL /**< Mode ARGB8888 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_DEFAULT (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0555 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0555 << 0) /**< Shifted mode ARGB0555 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0565 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0565 << 0) /**< Shifted mode ARGB0565 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0666 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0666 << 0) /**< Shifted mode ARGB0666 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0888 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0888 << 0) /**< Shifted mode ARGB0888 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB5555 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB5555 << 0) /**< Shifted mode ARGB5555 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6565 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6565 << 0) /**< Shifted mode ARGB6565 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6666 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6666 << 0) /**< Shifted mode ARGB6666 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB8888 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB8888 << 0) /**< Shifted mode ARGB8888 for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_SHIFT 8 /**< Shift value for EBI_PIXEL1FORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_MASK 0x300UL /**< Bit mask for EBI_PIXEL1FORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB555 0x00000000UL /**< Mode RGB555 for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB565 0x00000001UL /**< Mode RGB565 for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB666 0x00000002UL /**< Mode RGB666 for EBI_TFTCOLORFORMAT */ +#define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB888 0x00000003UL /**< Mode RGB888 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL1FORMAT_DEFAULT (_EBI_TFTCOLORFORMAT_PIXEL1FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB555 (_EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB555 << 8) /**< Shifted mode RGB555 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB565 (_EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB565 << 8) /**< Shifted mode RGB565 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB666 (_EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB666 << 8) /**< Shifted mode RGB666 for EBI_TFTCOLORFORMAT */ +#define EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB888 (_EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB888 << 8) /**< Shifted mode RGB888 for EBI_TFTCOLORFORMAT */ + +/* Bit fields for EBI TFTFRAMEBASE */ +#define _EBI_TFTFRAMEBASE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTFRAMEBASE */ +#define _EBI_TFTFRAMEBASE_MASK 0x0FFFFFFFUL /**< Mask for EBI_TFTFRAMEBASE */ +#define _EBI_TFTFRAMEBASE_FRAMEBASE_SHIFT 0 /**< Shift value for EBI_FRAMEBASE */ +#define _EBI_TFTFRAMEBASE_FRAMEBASE_MASK 0xFFFFFFFUL /**< Bit mask for EBI_FRAMEBASE */ +#define _EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTFRAMEBASE */ +#define EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT (_EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTFRAMEBASE */ + +/* Bit fields for EBI TFTSTRIDE */ +#define _EBI_TFTSTRIDE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSTRIDE */ +#define _EBI_TFTSTRIDE_MASK 0x00000FFFUL /**< Mask for EBI_TFTSTRIDE */ +#define _EBI_TFTSTRIDE_HSTRIDE_SHIFT 0 /**< Shift value for EBI_HSTRIDE */ +#define _EBI_TFTSTRIDE_HSTRIDE_MASK 0xFFFUL /**< Bit mask for EBI_HSTRIDE */ +#define _EBI_TFTSTRIDE_HSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTRIDE */ +#define EBI_TFTSTRIDE_HSTRIDE_DEFAULT (_EBI_TFTSTRIDE_HSTRIDE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSTRIDE */ + +/* Bit fields for EBI TFTSIZE */ +#define _EBI_TFTSIZE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSIZE */ +#define _EBI_TFTSIZE_MASK 0x03FF03FFUL /**< Mask for EBI_TFTSIZE */ +#define _EBI_TFTSIZE_HSZ_SHIFT 0 /**< Shift value for EBI_HSZ */ +#define _EBI_TFTSIZE_HSZ_MASK 0x3FFUL /**< Bit mask for EBI_HSZ */ +#define _EBI_TFTSIZE_HSZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSIZE */ +#define EBI_TFTSIZE_HSZ_DEFAULT (_EBI_TFTSIZE_HSZ_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSIZE */ +#define _EBI_TFTSIZE_VSZ_SHIFT 16 /**< Shift value for EBI_VSZ */ +#define _EBI_TFTSIZE_VSZ_MASK 0x3FF0000UL /**< Bit mask for EBI_VSZ */ +#define _EBI_TFTSIZE_VSZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSIZE */ +#define EBI_TFTSIZE_VSZ_DEFAULT (_EBI_TFTSIZE_VSZ_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSIZE */ + +/* Bit fields for EBI TFTHPORCH */ +#define _EBI_TFTHPORCH_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTHPORCH */ +#define _EBI_TFTHPORCH_MASK 0x33FCFF7FUL /**< Mask for EBI_TFTHPORCH */ +#define _EBI_TFTHPORCH_HSYNC_SHIFT 0 /**< Shift value for EBI_HSYNC */ +#define _EBI_TFTHPORCH_HSYNC_MASK 0x7FUL /**< Bit mask for EBI_HSYNC */ +#define _EBI_TFTHPORCH_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ +#define EBI_TFTHPORCH_HSYNC_DEFAULT (_EBI_TFTHPORCH_HSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ +#define _EBI_TFTHPORCH_HFPORCH_SHIFT 8 /**< Shift value for EBI_HFPORCH */ +#define _EBI_TFTHPORCH_HFPORCH_MASK 0xFF00UL /**< Bit mask for EBI_HFPORCH */ +#define _EBI_TFTHPORCH_HFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ +#define EBI_TFTHPORCH_HFPORCH_DEFAULT (_EBI_TFTHPORCH_HFPORCH_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ +#define _EBI_TFTHPORCH_HBPORCH_SHIFT 18 /**< Shift value for EBI_HBPORCH */ +#define _EBI_TFTHPORCH_HBPORCH_MASK 0x3FC0000UL /**< Bit mask for EBI_HBPORCH */ +#define _EBI_TFTHPORCH_HBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ +#define EBI_TFTHPORCH_HBPORCH_DEFAULT (_EBI_TFTHPORCH_HBPORCH_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ +#define _EBI_TFTHPORCH_HSYNCSTART_SHIFT 28 /**< Shift value for EBI_HSYNCSTART */ +#define _EBI_TFTHPORCH_HSYNCSTART_MASK 0x30000000UL /**< Bit mask for EBI_HSYNCSTART */ +#define _EBI_TFTHPORCH_HSYNCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ +#define EBI_TFTHPORCH_HSYNCSTART_DEFAULT (_EBI_TFTHPORCH_HSYNCSTART_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ + +/* Bit fields for EBI TFTVPORCH */ +#define _EBI_TFTVPORCH_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTVPORCH */ +#define _EBI_TFTVPORCH_MASK 0xFFFFFF7FUL /**< Mask for EBI_TFTVPORCH */ +#define _EBI_TFTVPORCH_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ +#define _EBI_TFTVPORCH_VSYNC_MASK 0x7FUL /**< Bit mask for EBI_VSYNC */ +#define _EBI_TFTVPORCH_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */ +#define EBI_TFTVPORCH_VSYNC_DEFAULT (_EBI_TFTVPORCH_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */ +#define _EBI_TFTVPORCH_VFPORCH_SHIFT 8 /**< Shift value for EBI_VFPORCH */ +#define _EBI_TFTVPORCH_VFPORCH_MASK 0xFFF00UL /**< Bit mask for EBI_VFPORCH */ +#define _EBI_TFTVPORCH_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */ +#define EBI_TFTVPORCH_VFPORCH_DEFAULT (_EBI_TFTVPORCH_VFPORCH_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */ +#define _EBI_TFTVPORCH_VBPORCH_SHIFT 20 /**< Shift value for EBI_VBPORCH */ +#define _EBI_TFTVPORCH_VBPORCH_MASK 0xFFF00000UL /**< Bit mask for EBI_VBPORCH */ +#define _EBI_TFTVPORCH_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */ +#define EBI_TFTVPORCH_VBPORCH_DEFAULT (_EBI_TFTVPORCH_VBPORCH_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */ + +/* Bit fields for EBI TFTTIMING */ +#define _EBI_TFTTIMING_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTTIMING */ +#define _EBI_TFTTIMING_MASK 0x77FFFFFFUL /**< Mask for EBI_TFTTIMING */ +#define _EBI_TFTTIMING_DCLKPERIOD_SHIFT 0 /**< Shift value for EBI_DCLKPERIOD */ +#define _EBI_TFTTIMING_DCLKPERIOD_MASK 0xFFFUL /**< Bit mask for EBI_DCLKPERIOD */ +#define _EBI_TFTTIMING_DCLKPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ +#define EBI_TFTTIMING_DCLKPERIOD_DEFAULT (_EBI_TFTTIMING_DCLKPERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ +#define _EBI_TFTTIMING_TFTSTART_SHIFT 12 /**< Shift value for EBI_TFTSTART */ +#define _EBI_TFTTIMING_TFTSTART_MASK 0xFFF000UL /**< Bit mask for EBI_TFTSTART */ +#define _EBI_TFTTIMING_TFTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ +#define EBI_TFTTIMING_TFTSTART_DEFAULT (_EBI_TFTTIMING_TFTSTART_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ +#define _EBI_TFTTIMING_TFTSETUP_SHIFT 24 /**< Shift value for EBI_TFTSETUP */ +#define _EBI_TFTTIMING_TFTSETUP_MASK 0x7000000UL /**< Bit mask for EBI_TFTSETUP */ +#define _EBI_TFTTIMING_TFTSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ +#define EBI_TFTTIMING_TFTSETUP_DEFAULT (_EBI_TFTTIMING_TFTSETUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ +#define _EBI_TFTTIMING_TFTHOLD_SHIFT 28 /**< Shift value for EBI_TFTHOLD */ +#define _EBI_TFTTIMING_TFTHOLD_MASK 0x70000000UL /**< Bit mask for EBI_TFTHOLD */ +#define _EBI_TFTTIMING_TFTHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ +#define EBI_TFTTIMING_TFTHOLD_DEFAULT (_EBI_TFTTIMING_TFTHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ + +/* Bit fields for EBI TFTPOLARITY */ +#define _EBI_TFTPOLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPOLARITY */ +#define _EBI_TFTPOLARITY_MASK 0x0000001FUL /**< Mask for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_CSPOL (0x1UL << 0) /**< TFT Chip Select Polarity */ +#define _EBI_TFTPOLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ +#define _EBI_TFTPOLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ +#define _EBI_TFTPOLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ +#define _EBI_TFTPOLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ +#define _EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_CSPOL_DEFAULT (_EBI_TFTPOLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_CSPOL_ACTIVELOW (_EBI_TFTPOLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_DCLKPOL (0x1UL << 1) /**< TFT DCLK Polarity */ +#define _EBI_TFTPOLARITY_DCLKPOL_SHIFT 1 /**< Shift value for EBI_DCLKPOL */ +#define _EBI_TFTPOLARITY_DCLKPOL_MASK 0x2UL /**< Bit mask for EBI_DCLKPOL */ +#define _EBI_TFTPOLARITY_DCLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ +#define _EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING 0x00000000UL /**< Mode ACTIVEFALLING for EBI_TFTPOLARITY */ +#define _EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING 0x00000001UL /**< Mode ACTIVERISING for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_DCLKPOL_DEFAULT (_EBI_TFTPOLARITY_DCLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING << 1) /**< Shifted mode ACTIVEFALLING for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING << 1) /**< Shifted mode ACTIVERISING for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_DATAENPOL (0x1UL << 2) /**< TFT DATAEN Polarity */ +#define _EBI_TFTPOLARITY_DATAENPOL_SHIFT 2 /**< Shift value for EBI_DATAENPOL */ +#define _EBI_TFTPOLARITY_DATAENPOL_MASK 0x4UL /**< Bit mask for EBI_DATAENPOL */ +#define _EBI_TFTPOLARITY_DATAENPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ +#define _EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ +#define _EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_DATAENPOL_DEFAULT (_EBI_TFTPOLARITY_DATAENPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW (_EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_HSYNCPOL (0x1UL << 3) /**< Address Latch Polarity */ +#define _EBI_TFTPOLARITY_HSYNCPOL_SHIFT 3 /**< Shift value for EBI_HSYNCPOL */ +#define _EBI_TFTPOLARITY_HSYNCPOL_MASK 0x8UL /**< Bit mask for EBI_HSYNCPOL */ +#define _EBI_TFTPOLARITY_HSYNCPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ +#define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ +#define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_HSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_HSYNCPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_VSYNCPOL (0x1UL << 4) /**< VSYNC Polarity */ +#define _EBI_TFTPOLARITY_VSYNCPOL_SHIFT 4 /**< Shift value for EBI_VSYNCPOL */ +#define _EBI_TFTPOLARITY_VSYNCPOL_MASK 0x10UL /**< Bit mask for EBI_VSYNCPOL */ +#define _EBI_TFTPOLARITY_VSYNCPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ +#define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ +#define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_VSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_VSYNCPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ +#define EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ + +/* Bit fields for EBI TFTDD */ +#define _EBI_TFTDD_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTDD */ +#define _EBI_TFTDD_MASK 0x00FFFFFFUL /**< Mask for EBI_TFTDD */ +#define _EBI_TFTDD_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ +#define _EBI_TFTDD_DATA_MASK 0xFFFFFFUL /**< Bit mask for EBI_DATA */ +#define _EBI_TFTDD_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTDD */ +#define EBI_TFTDD_DATA_DEFAULT (_EBI_TFTDD_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTDD */ + +/* Bit fields for EBI TFTALPHA */ +#define _EBI_TFTALPHA_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTALPHA */ +#define _EBI_TFTALPHA_MASK 0x000001FFUL /**< Mask for EBI_TFTALPHA */ +#define _EBI_TFTALPHA_ALPHA_SHIFT 0 /**< Shift value for EBI_ALPHA */ +#define _EBI_TFTALPHA_ALPHA_MASK 0x1FFUL /**< Bit mask for EBI_ALPHA */ +#define _EBI_TFTALPHA_ALPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTALPHA */ +#define EBI_TFTALPHA_ALPHA_DEFAULT (_EBI_TFTALPHA_ALPHA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTALPHA */ + +/* Bit fields for EBI TFTPIXEL0 */ +#define _EBI_TFTPIXEL0_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL0 */ +#define _EBI_TFTPIXEL0_MASK 0x00FFFFFFUL /**< Mask for EBI_TFTPIXEL0 */ +#define _EBI_TFTPIXEL0_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ +#define _EBI_TFTPIXEL0_DATA_MASK 0xFFFFFFUL /**< Bit mask for EBI_DATA */ +#define _EBI_TFTPIXEL0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL0 */ +#define EBI_TFTPIXEL0_DATA_DEFAULT (_EBI_TFTPIXEL0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL0 */ + +/* Bit fields for EBI TFTPIXEL1 */ +#define _EBI_TFTPIXEL1_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL1 */ +#define _EBI_TFTPIXEL1_MASK 0x00FFFFFFUL /**< Mask for EBI_TFTPIXEL1 */ +#define _EBI_TFTPIXEL1_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ +#define _EBI_TFTPIXEL1_DATA_MASK 0xFFFFFFUL /**< Bit mask for EBI_DATA */ +#define _EBI_TFTPIXEL1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL1 */ +#define EBI_TFTPIXEL1_DATA_DEFAULT (_EBI_TFTPIXEL1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL1 */ + +/* Bit fields for EBI TFTPIXEL */ +#define _EBI_TFTPIXEL_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL */ +#define _EBI_TFTPIXEL_MASK 0x00FFFFFFUL /**< Mask for EBI_TFTPIXEL */ +#define _EBI_TFTPIXEL_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ +#define _EBI_TFTPIXEL_DATA_MASK 0xFFFFFFUL /**< Bit mask for EBI_DATA */ +#define _EBI_TFTPIXEL_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL */ +#define EBI_TFTPIXEL_DATA_DEFAULT (_EBI_TFTPIXEL_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL */ + +/* Bit fields for EBI TFTMASK */ +#define _EBI_TFTMASK_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTMASK */ +#define _EBI_TFTMASK_MASK 0x00FFFFFFUL /**< Mask for EBI_TFTMASK */ +#define _EBI_TFTMASK_TFTMASK_SHIFT 0 /**< Shift value for EBI_TFTMASK */ +#define _EBI_TFTMASK_TFTMASK_MASK 0xFFFFFFUL /**< Bit mask for EBI_TFTMASK */ +#define _EBI_TFTMASK_TFTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTMASK */ +#define EBI_TFTMASK_TFTMASK_DEFAULT (_EBI_TFTMASK_TFTMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTMASK */ + +/* Bit fields for EBI IF */ +#define _EBI_IF_RESETVALUE 0x00000000UL /**< Default value for EBI_IF */ +#define _EBI_IF_MASK 0x000003FFUL /**< Mask for EBI_IF */ +#define EBI_IF_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag */ +#define _EBI_IF_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ +#define _EBI_IF_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ +#define _EBI_IF_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ +#define EBI_IF_VSYNC_DEFAULT (_EBI_IF_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IF */ +#define EBI_IF_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag */ +#define _EBI_IF_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ +#define _EBI_IF_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ +#define _EBI_IF_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ +#define EBI_IF_HSYNC_DEFAULT (_EBI_IF_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IF */ +#define EBI_IF_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag */ +#define _EBI_IF_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ +#define _EBI_IF_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ +#define _EBI_IF_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ +#define EBI_IF_VBPORCH_DEFAULT (_EBI_IF_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IF */ +#define EBI_IF_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag */ +#define _EBI_IF_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ +#define _EBI_IF_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ +#define _EBI_IF_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ +#define EBI_IF_VFPORCH_DEFAULT (_EBI_IF_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IF */ +#define EBI_IF_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag */ +#define _EBI_IF_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ +#define _EBI_IF_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ +#define _EBI_IF_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ +#define EBI_IF_DDEMPTY_DEFAULT (_EBI_IF_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IF */ +#define EBI_IF_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag */ +#define _EBI_IF_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ +#define _EBI_IF_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ +#define _EBI_IF_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ +#define EBI_IF_DDJIT_DEFAULT (_EBI_IF_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IF */ +#define EBI_IF_TFTPIXEL0EMPTY (0x1UL << 6) /**< EBI_TFTPIXEL0 is Empty Interrupt Flag */ +#define _EBI_IF_TFTPIXEL0EMPTY_SHIFT 6 /**< Shift value for EBI_TFTPIXEL0EMPTY */ +#define _EBI_IF_TFTPIXEL0EMPTY_MASK 0x40UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */ +#define _EBI_IF_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ +#define EBI_IF_TFTPIXEL0EMPTY_DEFAULT (_EBI_IF_TFTPIXEL0EMPTY_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_IF */ +#define EBI_IF_TFTPIXEL1EMPTY (0x1UL << 7) /**< EBI_TFTPIXEL1 is Empty Interrupt Flag */ +#define _EBI_IF_TFTPIXEL1EMPTY_SHIFT 7 /**< Shift value for EBI_TFTPIXEL1EMPTY */ +#define _EBI_IF_TFTPIXEL1EMPTY_MASK 0x80UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */ +#define _EBI_IF_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ +#define EBI_IF_TFTPIXEL1EMPTY_DEFAULT (_EBI_IF_TFTPIXEL1EMPTY_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_IF */ +#define EBI_IF_TFTPIXELFULL (0x1UL << 8) /**< EBI_TFTPIXEL is Full Interrupt Flag */ +#define _EBI_IF_TFTPIXELFULL_SHIFT 8 /**< Shift value for EBI_TFTPIXELFULL */ +#define _EBI_IF_TFTPIXELFULL_MASK 0x100UL /**< Bit mask for EBI_TFTPIXELFULL */ +#define _EBI_IF_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ +#define EBI_IF_TFTPIXELFULL_DEFAULT (_EBI_IF_TFTPIXELFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_IF */ +#define EBI_IF_TFTPIXELOF (0x1UL << 9) /**< EBI_TFTPIXEL Register Overflow Interrupt Flag */ +#define _EBI_IF_TFTPIXELOF_SHIFT 9 /**< Shift value for EBI_TFTPIXELOF */ +#define _EBI_IF_TFTPIXELOF_MASK 0x200UL /**< Bit mask for EBI_TFTPIXELOF */ +#define _EBI_IF_TFTPIXELOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ +#define EBI_IF_TFTPIXELOF_DEFAULT (_EBI_IF_TFTPIXELOF_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_IF */ + +/* Bit fields for EBI IFS */ +#define _EBI_IFS_RESETVALUE 0x00000000UL /**< Default value for EBI_IFS */ +#define _EBI_IFS_MASK 0x000003FFUL /**< Mask for EBI_IFS */ +#define EBI_IFS_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag Set */ +#define _EBI_IFS_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ +#define _EBI_IFS_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ +#define _EBI_IFS_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ +#define EBI_IFS_VSYNC_DEFAULT (_EBI_IFS_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IFS */ +#define EBI_IFS_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag Set */ +#define _EBI_IFS_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ +#define _EBI_IFS_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ +#define _EBI_IFS_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ +#define EBI_IFS_HSYNC_DEFAULT (_EBI_IFS_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IFS */ +#define EBI_IFS_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag Set */ +#define _EBI_IFS_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ +#define _EBI_IFS_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ +#define _EBI_IFS_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ +#define EBI_IFS_VBPORCH_DEFAULT (_EBI_IFS_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFS */ +#define EBI_IFS_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag Set */ +#define _EBI_IFS_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ +#define _EBI_IFS_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ +#define _EBI_IFS_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ +#define EBI_IFS_VFPORCH_DEFAULT (_EBI_IFS_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFS */ +#define EBI_IFS_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag Set */ +#define _EBI_IFS_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ +#define _EBI_IFS_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ +#define _EBI_IFS_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ +#define EBI_IFS_DDEMPTY_DEFAULT (_EBI_IFS_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFS */ +#define EBI_IFS_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag Set */ +#define _EBI_IFS_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ +#define _EBI_IFS_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ +#define _EBI_IFS_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ +#define EBI_IFS_DDJIT_DEFAULT (_EBI_IFS_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IFS */ +#define EBI_IFS_TFTPIXEL0EMPTY (0x1UL << 6) /**< EBI_TFTPIXEL0 Empty Interrupt Flag Set */ +#define _EBI_IFS_TFTPIXEL0EMPTY_SHIFT 6 /**< Shift value for EBI_TFTPIXEL0EMPTY */ +#define _EBI_IFS_TFTPIXEL0EMPTY_MASK 0x40UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */ +#define _EBI_IFS_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ +#define EBI_IFS_TFTPIXEL0EMPTY_DEFAULT (_EBI_IFS_TFTPIXEL0EMPTY_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_IFS */ +#define EBI_IFS_TFTPIXEL1EMPTY (0x1UL << 7) /**< EBI_TFTPIXEL1 Empty Interrupt Flag Set */ +#define _EBI_IFS_TFTPIXEL1EMPTY_SHIFT 7 /**< Shift value for EBI_TFTPIXEL1EMPTY */ +#define _EBI_IFS_TFTPIXEL1EMPTY_MASK 0x80UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */ +#define _EBI_IFS_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ +#define EBI_IFS_TFTPIXEL1EMPTY_DEFAULT (_EBI_IFS_TFTPIXEL1EMPTY_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_IFS */ +#define EBI_IFS_TFTPIXELFULL (0x1UL << 8) /**< EBI_TFTPIXEL Full Interrupt Flag Set */ +#define _EBI_IFS_TFTPIXELFULL_SHIFT 8 /**< Shift value for EBI_TFTPIXELFULL */ +#define _EBI_IFS_TFTPIXELFULL_MASK 0x100UL /**< Bit mask for EBI_TFTPIXELFULL */ +#define _EBI_IFS_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ +#define EBI_IFS_TFTPIXELFULL_DEFAULT (_EBI_IFS_TFTPIXELFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_IFS */ +#define EBI_IFS_TFTPIXELOF (0x1UL << 9) /**< EBI_TFTPIXEL Overflow Interrupt Flag Set */ +#define _EBI_IFS_TFTPIXELOF_SHIFT 9 /**< Shift value for EBI_TFTPIXELOF */ +#define _EBI_IFS_TFTPIXELOF_MASK 0x200UL /**< Bit mask for EBI_TFTPIXELOF */ +#define _EBI_IFS_TFTPIXELOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ +#define EBI_IFS_TFTPIXELOF_DEFAULT (_EBI_IFS_TFTPIXELOF_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_IFS */ + +/* Bit fields for EBI IFC */ +#define _EBI_IFC_RESETVALUE 0x00000000UL /**< Default value for EBI_IFC */ +#define _EBI_IFC_MASK 0x000003FFUL /**< Mask for EBI_IFC */ +#define EBI_IFC_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag Clear */ +#define _EBI_IFC_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ +#define _EBI_IFC_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ +#define _EBI_IFC_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ +#define EBI_IFC_VSYNC_DEFAULT (_EBI_IFC_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IFC */ +#define EBI_IFC_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag Clear */ +#define _EBI_IFC_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ +#define _EBI_IFC_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ +#define _EBI_IFC_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ +#define EBI_IFC_HSYNC_DEFAULT (_EBI_IFC_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IFC */ +#define EBI_IFC_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag Clear */ +#define _EBI_IFC_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ +#define _EBI_IFC_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ +#define _EBI_IFC_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ +#define EBI_IFC_VBPORCH_DEFAULT (_EBI_IFC_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFC */ +#define EBI_IFC_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag Clear */ +#define _EBI_IFC_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ +#define _EBI_IFC_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ +#define _EBI_IFC_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ +#define EBI_IFC_VFPORCH_DEFAULT (_EBI_IFC_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFC */ +#define EBI_IFC_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag Clear */ +#define _EBI_IFC_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ +#define _EBI_IFC_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ +#define _EBI_IFC_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ +#define EBI_IFC_DDEMPTY_DEFAULT (_EBI_IFC_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFC */ +#define EBI_IFC_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag Clear */ +#define _EBI_IFC_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ +#define _EBI_IFC_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ +#define _EBI_IFC_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ +#define EBI_IFC_DDJIT_DEFAULT (_EBI_IFC_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IFC */ +#define EBI_IFC_TFTPIXEL0EMPTY (0x1UL << 6) /**< EBI_TFTPIXEL0 Empty Interrupt Flag Clear */ +#define _EBI_IFC_TFTPIXEL0EMPTY_SHIFT 6 /**< Shift value for EBI_TFTPIXEL0EMPTY */ +#define _EBI_IFC_TFTPIXEL0EMPTY_MASK 0x40UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */ +#define _EBI_IFC_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ +#define EBI_IFC_TFTPIXEL0EMPTY_DEFAULT (_EBI_IFC_TFTPIXEL0EMPTY_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_IFC */ +#define EBI_IFC_TFTPIXEL1EMPTY (0x1UL << 7) /**< EBI_TFTPIXEL1 Empty Interrupt Flag Clear */ +#define _EBI_IFC_TFTPIXEL1EMPTY_SHIFT 7 /**< Shift value for EBI_TFTPIXEL1EMPTY */ +#define _EBI_IFC_TFTPIXEL1EMPTY_MASK 0x80UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */ +#define _EBI_IFC_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ +#define EBI_IFC_TFTPIXEL1EMPTY_DEFAULT (_EBI_IFC_TFTPIXEL1EMPTY_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_IFC */ +#define EBI_IFC_TFTPIXELFULL (0x1UL << 8) /**< EBI_TFTPIXEL Full Interrupt Flag Clear */ +#define _EBI_IFC_TFTPIXELFULL_SHIFT 8 /**< Shift value for EBI_TFTPIXELFULL */ +#define _EBI_IFC_TFTPIXELFULL_MASK 0x100UL /**< Bit mask for EBI_TFTPIXELFULL */ +#define _EBI_IFC_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ +#define EBI_IFC_TFTPIXELFULL_DEFAULT (_EBI_IFC_TFTPIXELFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_IFC */ +#define EBI_IFC_TFTPIXELOF (0x1UL << 9) /**< EBI_TFTPIXEL Overflow Interrupt Flag Clear */ +#define _EBI_IFC_TFTPIXELOF_SHIFT 9 /**< Shift value for EBI_TFTPIXELOF */ +#define _EBI_IFC_TFTPIXELOF_MASK 0x200UL /**< Bit mask for EBI_TFTPIXELOF */ +#define _EBI_IFC_TFTPIXELOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ +#define EBI_IFC_TFTPIXELOF_DEFAULT (_EBI_IFC_TFTPIXELOF_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_IFC */ + +/* Bit fields for EBI IEN */ +#define _EBI_IEN_RESETVALUE 0x00000000UL /**< Default value for EBI_IEN */ +#define _EBI_IEN_MASK 0x000003FFUL /**< Mask for EBI_IEN */ +#define EBI_IEN_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Enable */ +#define _EBI_IEN_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ +#define _EBI_IEN_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ +#define _EBI_IEN_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ +#define EBI_IEN_VSYNC_DEFAULT (_EBI_IEN_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IEN */ +#define EBI_IEN_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Enable */ +#define _EBI_IEN_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ +#define _EBI_IEN_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ +#define _EBI_IEN_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ +#define EBI_IEN_HSYNC_DEFAULT (_EBI_IEN_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IEN */ +#define EBI_IEN_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Enable */ +#define _EBI_IEN_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ +#define _EBI_IEN_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ +#define _EBI_IEN_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ +#define EBI_IEN_VBPORCH_DEFAULT (_EBI_IEN_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IEN */ +#define EBI_IEN_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Enable */ +#define _EBI_IEN_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ +#define _EBI_IEN_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ +#define _EBI_IEN_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ +#define EBI_IEN_VFPORCH_DEFAULT (_EBI_IEN_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IEN */ +#define EBI_IEN_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Enable */ +#define _EBI_IEN_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ +#define _EBI_IEN_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ +#define _EBI_IEN_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ +#define EBI_IEN_DDEMPTY_DEFAULT (_EBI_IEN_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IEN */ +#define EBI_IEN_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Enable */ +#define _EBI_IEN_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ +#define _EBI_IEN_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ +#define _EBI_IEN_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ +#define EBI_IEN_DDJIT_DEFAULT (_EBI_IEN_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IEN */ +#define EBI_IEN_TFTPIXEL0EMPTY (0x1UL << 6) /**< EBI_TFTPIXEL0 Empty Interrupt Enable */ +#define _EBI_IEN_TFTPIXEL0EMPTY_SHIFT 6 /**< Shift value for EBI_TFTPIXEL0EMPTY */ +#define _EBI_IEN_TFTPIXEL0EMPTY_MASK 0x40UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */ +#define _EBI_IEN_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ +#define EBI_IEN_TFTPIXEL0EMPTY_DEFAULT (_EBI_IEN_TFTPIXEL0EMPTY_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_IEN */ +#define EBI_IEN_TFTPIXEL1EMPTY (0x1UL << 7) /**< EBI_TFTPIXEL1 Empty Interrupt Enable */ +#define _EBI_IEN_TFTPIXEL1EMPTY_SHIFT 7 /**< Shift value for EBI_TFTPIXEL1EMPTY */ +#define _EBI_IEN_TFTPIXEL1EMPTY_MASK 0x80UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */ +#define _EBI_IEN_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ +#define EBI_IEN_TFTPIXEL1EMPTY_DEFAULT (_EBI_IEN_TFTPIXEL1EMPTY_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_IEN */ +#define EBI_IEN_TFTPIXELFULL (0x1UL << 8) /**< EBI_TFTPIXEL Full Interrupt Enable */ +#define _EBI_IEN_TFTPIXELFULL_SHIFT 8 /**< Shift value for EBI_TFTPIXELFULL */ +#define _EBI_IEN_TFTPIXELFULL_MASK 0x100UL /**< Bit mask for EBI_TFTPIXELFULL */ +#define _EBI_IEN_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ +#define EBI_IEN_TFTPIXELFULL_DEFAULT (_EBI_IEN_TFTPIXELFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_IEN */ +#define EBI_IEN_TFTPIXELOF (0x1UL << 9) /**< EBI_TFTPIXEL Overflow Interrupt Enable */ +#define _EBI_IEN_TFTPIXELOF_SHIFT 9 /**< Shift value for EBI_TFTPIXELOF */ +#define _EBI_IEN_TFTPIXELOF_MASK 0x200UL /**< Bit mask for EBI_TFTPIXELOF */ +#define _EBI_IEN_TFTPIXELOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ +#define EBI_IEN_TFTPIXELOF_DEFAULT (_EBI_IEN_TFTPIXELOF_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_IEN */ + +/* Bit fields for EBI ROUTEPEN */ +#define _EBI_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_MASK 0x077F10FFUL /**< Mask for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_EBIPEN (0x1UL << 0) /**< EBI Pin Enable */ +#define _EBI_ROUTEPEN_EBIPEN_SHIFT 0 /**< Shift value for EBI_EBIPEN */ +#define _EBI_ROUTEPEN_EBIPEN_MASK 0x1UL /**< Bit mask for EBI_EBIPEN */ +#define _EBI_ROUTEPEN_EBIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_EBIPEN_DEFAULT (_EBI_ROUTEPEN_EBIPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_CS0PEN (0x1UL << 1) /**< EBI_CS0 Pin Enable */ +#define _EBI_ROUTEPEN_CS0PEN_SHIFT 1 /**< Shift value for EBI_CS0PEN */ +#define _EBI_ROUTEPEN_CS0PEN_MASK 0x2UL /**< Bit mask for EBI_CS0PEN */ +#define _EBI_ROUTEPEN_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_CS0PEN_DEFAULT (_EBI_ROUTEPEN_CS0PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_CS1PEN (0x1UL << 2) /**< EBI_CS1 Pin Enable */ +#define _EBI_ROUTEPEN_CS1PEN_SHIFT 2 /**< Shift value for EBI_CS1PEN */ +#define _EBI_ROUTEPEN_CS1PEN_MASK 0x4UL /**< Bit mask for EBI_CS1PEN */ +#define _EBI_ROUTEPEN_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_CS1PEN_DEFAULT (_EBI_ROUTEPEN_CS1PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_CS2PEN (0x1UL << 3) /**< EBI_CS2 Pin Enable */ +#define _EBI_ROUTEPEN_CS2PEN_SHIFT 3 /**< Shift value for EBI_CS2PEN */ +#define _EBI_ROUTEPEN_CS2PEN_MASK 0x8UL /**< Bit mask for EBI_CS2PEN */ +#define _EBI_ROUTEPEN_CS2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_CS2PEN_DEFAULT (_EBI_ROUTEPEN_CS2PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_CS3PEN (0x1UL << 4) /**< EBI_CS3 Pin Enable */ +#define _EBI_ROUTEPEN_CS3PEN_SHIFT 4 /**< Shift value for EBI_CS3PEN */ +#define _EBI_ROUTEPEN_CS3PEN_MASK 0x10UL /**< Bit mask for EBI_CS3PEN */ +#define _EBI_ROUTEPEN_CS3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_CS3PEN_DEFAULT (_EBI_ROUTEPEN_CS3PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_ALEPEN (0x1UL << 5) /**< EBI_ALE Pin Enable */ +#define _EBI_ROUTEPEN_ALEPEN_SHIFT 5 /**< Shift value for EBI_ALEPEN */ +#define _EBI_ROUTEPEN_ALEPEN_MASK 0x20UL /**< Bit mask for EBI_ALEPEN */ +#define _EBI_ROUTEPEN_ALEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_ALEPEN_DEFAULT (_EBI_ROUTEPEN_ALEPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_ARDYPEN (0x1UL << 6) /**< EBI_ARDY Pin Enable */ +#define _EBI_ROUTEPEN_ARDYPEN_SHIFT 6 /**< Shift value for EBI_ARDYPEN */ +#define _EBI_ROUTEPEN_ARDYPEN_MASK 0x40UL /**< Bit mask for EBI_ARDYPEN */ +#define _EBI_ROUTEPEN_ARDYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_ARDYPEN_DEFAULT (_EBI_ROUTEPEN_ARDYPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_BLPEN (0x1UL << 7) /**< EBI_BL[1:0] Pin Enable */ +#define _EBI_ROUTEPEN_BLPEN_SHIFT 7 /**< Shift value for EBI_BLPEN */ +#define _EBI_ROUTEPEN_BLPEN_MASK 0x80UL /**< Bit mask for EBI_BLPEN */ +#define _EBI_ROUTEPEN_BLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_BLPEN_DEFAULT (_EBI_ROUTEPEN_BLPEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_NANDPEN (0x1UL << 12) /**< NANDRE and NANDWE Pin Enable */ +#define _EBI_ROUTEPEN_NANDPEN_SHIFT 12 /**< Shift value for EBI_NANDPEN */ +#define _EBI_ROUTEPEN_NANDPEN_MASK 0x1000UL /**< Bit mask for EBI_NANDPEN */ +#define _EBI_ROUTEPEN_NANDPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_NANDPEN_DEFAULT (_EBI_ROUTEPEN_NANDPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_ALB_SHIFT 16 /**< Shift value for EBI_ALB */ +#define _EBI_ROUTEPEN_ALB_MASK 0x30000UL /**< Bit mask for EBI_ALB */ +#define _EBI_ROUTEPEN_ALB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_ALB_A0 0x00000000UL /**< Mode A0 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_ALB_A8 0x00000001UL /**< Mode A8 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_ALB_A16 0x00000002UL /**< Mode A16 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_ALB_A24 0x00000003UL /**< Mode A24 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_ALB_DEFAULT (_EBI_ROUTEPEN_ALB_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_ALB_A0 (_EBI_ROUTEPEN_ALB_A0 << 16) /**< Shifted mode A0 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_ALB_A8 (_EBI_ROUTEPEN_ALB_A8 << 16) /**< Shifted mode A8 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_ALB_A16 (_EBI_ROUTEPEN_ALB_A16 << 16) /**< Shifted mode A16 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_ALB_A24 (_EBI_ROUTEPEN_ALB_A24 << 16) /**< Shifted mode A24 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_SHIFT 18 /**< Shift value for EBI_APEN */ +#define _EBI_ROUTEPEN_APEN_MASK 0x7C0000UL /**< Bit mask for EBI_APEN */ +#define _EBI_ROUTEPEN_APEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A0 0x00000000UL /**< Mode A0 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A5 0x00000005UL /**< Mode A5 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A6 0x00000006UL /**< Mode A6 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A7 0x00000007UL /**< Mode A7 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A8 0x00000008UL /**< Mode A8 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A9 0x00000009UL /**< Mode A9 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A10 0x0000000AUL /**< Mode A10 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A11 0x0000000BUL /**< Mode A11 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A12 0x0000000CUL /**< Mode A12 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A13 0x0000000DUL /**< Mode A13 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A14 0x0000000EUL /**< Mode A14 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A15 0x0000000FUL /**< Mode A15 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A16 0x00000010UL /**< Mode A16 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A17 0x00000011UL /**< Mode A17 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A18 0x00000012UL /**< Mode A18 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A19 0x00000013UL /**< Mode A19 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A20 0x00000014UL /**< Mode A20 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A21 0x00000015UL /**< Mode A21 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A22 0x00000016UL /**< Mode A22 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A23 0x00000017UL /**< Mode A23 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A24 0x00000018UL /**< Mode A24 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A25 0x00000019UL /**< Mode A25 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A26 0x0000001AUL /**< Mode A26 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A27 0x0000001BUL /**< Mode A27 for EBI_ROUTEPEN */ +#define _EBI_ROUTEPEN_APEN_A28 0x0000001CUL /**< Mode A28 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_DEFAULT (_EBI_ROUTEPEN_APEN_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A0 (_EBI_ROUTEPEN_APEN_A0 << 18) /**< Shifted mode A0 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A5 (_EBI_ROUTEPEN_APEN_A5 << 18) /**< Shifted mode A5 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A6 (_EBI_ROUTEPEN_APEN_A6 << 18) /**< Shifted mode A6 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A7 (_EBI_ROUTEPEN_APEN_A7 << 18) /**< Shifted mode A7 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A8 (_EBI_ROUTEPEN_APEN_A8 << 18) /**< Shifted mode A8 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A9 (_EBI_ROUTEPEN_APEN_A9 << 18) /**< Shifted mode A9 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A10 (_EBI_ROUTEPEN_APEN_A10 << 18) /**< Shifted mode A10 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A11 (_EBI_ROUTEPEN_APEN_A11 << 18) /**< Shifted mode A11 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A12 (_EBI_ROUTEPEN_APEN_A12 << 18) /**< Shifted mode A12 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A13 (_EBI_ROUTEPEN_APEN_A13 << 18) /**< Shifted mode A13 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A14 (_EBI_ROUTEPEN_APEN_A14 << 18) /**< Shifted mode A14 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A15 (_EBI_ROUTEPEN_APEN_A15 << 18) /**< Shifted mode A15 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A16 (_EBI_ROUTEPEN_APEN_A16 << 18) /**< Shifted mode A16 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A17 (_EBI_ROUTEPEN_APEN_A17 << 18) /**< Shifted mode A17 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A18 (_EBI_ROUTEPEN_APEN_A18 << 18) /**< Shifted mode A18 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A19 (_EBI_ROUTEPEN_APEN_A19 << 18) /**< Shifted mode A19 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A20 (_EBI_ROUTEPEN_APEN_A20 << 18) /**< Shifted mode A20 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A21 (_EBI_ROUTEPEN_APEN_A21 << 18) /**< Shifted mode A21 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A22 (_EBI_ROUTEPEN_APEN_A22 << 18) /**< Shifted mode A22 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A23 (_EBI_ROUTEPEN_APEN_A23 << 18) /**< Shifted mode A23 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A24 (_EBI_ROUTEPEN_APEN_A24 << 18) /**< Shifted mode A24 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A25 (_EBI_ROUTEPEN_APEN_A25 << 18) /**< Shifted mode A25 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A26 (_EBI_ROUTEPEN_APEN_A26 << 18) /**< Shifted mode A26 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A27 (_EBI_ROUTEPEN_APEN_A27 << 18) /**< Shifted mode A27 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_APEN_A28 (_EBI_ROUTEPEN_APEN_A28 << 18) /**< Shifted mode A28 for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_TFTPEN (0x1UL << 24) /**< EBI_TFT Pin Enable */ +#define _EBI_ROUTEPEN_TFTPEN_SHIFT 24 /**< Shift value for EBI_TFTPEN */ +#define _EBI_ROUTEPEN_TFTPEN_MASK 0x1000000UL /**< Bit mask for EBI_TFTPEN */ +#define _EBI_ROUTEPEN_TFTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_TFTPEN_DEFAULT (_EBI_ROUTEPEN_TFTPEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_DATAENPEN (0x1UL << 25) /**< EBI_DATA Pin Enable */ +#define _EBI_ROUTEPEN_DATAENPEN_SHIFT 25 /**< Shift value for EBI_DATAENPEN */ +#define _EBI_ROUTEPEN_DATAENPEN_MASK 0x2000000UL /**< Bit mask for EBI_DATAENPEN */ +#define _EBI_ROUTEPEN_DATAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_DATAENPEN_DEFAULT (_EBI_ROUTEPEN_DATAENPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_CSTFTPEN (0x1UL << 26) /**< EBI_CSTFT Pin Enable */ +#define _EBI_ROUTEPEN_CSTFTPEN_SHIFT 26 /**< Shift value for EBI_CSTFTPEN */ +#define _EBI_ROUTEPEN_CSTFTPEN_MASK 0x4000000UL /**< Bit mask for EBI_CSTFTPEN */ +#define _EBI_ROUTEPEN_CSTFTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ +#define EBI_ROUTEPEN_CSTFTPEN_DEFAULT (_EBI_ROUTEPEN_CSTFTPEN_DEFAULT << 26) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ + +/* Bit fields for EBI ROUTELOC0 */ +#define _EBI_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_MASK 0x03070707UL /**< Mask for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_EBILOC_SHIFT 0 /**< Shift value for EBI_EBILOC */ +#define _EBI_ROUTELOC0_EBILOC_MASK 0x7UL /**< Bit mask for EBI_EBILOC */ +#define _EBI_ROUTELOC0_EBILOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_EBILOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_EBILOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_EBILOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_EBILOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_EBILOC_LOC4 0x00000004UL /**< Mode LOC4 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_EBILOC_LOC5 0x00000005UL /**< Mode LOC5 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_EBILOC_LOC0 (_EBI_ROUTELOC0_EBILOC_LOC0 << 0) /**< Shifted mode LOC0 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_EBILOC_DEFAULT (_EBI_ROUTELOC0_EBILOC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_EBILOC_LOC1 (_EBI_ROUTELOC0_EBILOC_LOC1 << 0) /**< Shifted mode LOC1 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_EBILOC_LOC2 (_EBI_ROUTELOC0_EBILOC_LOC2 << 0) /**< Shifted mode LOC2 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_EBILOC_LOC3 (_EBI_ROUTELOC0_EBILOC_LOC3 << 0) /**< Shifted mode LOC3 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_EBILOC_LOC4 (_EBI_ROUTELOC0_EBILOC_LOC4 << 0) /**< Shifted mode LOC4 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_EBILOC_LOC5 (_EBI_ROUTELOC0_EBILOC_LOC5 << 0) /**< Shifted mode LOC5 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_CSLOC_SHIFT 8 /**< Shift value for EBI_CSLOC */ +#define _EBI_ROUTELOC0_CSLOC_MASK 0x700UL /**< Bit mask for EBI_CSLOC */ +#define _EBI_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_CSLOC_LOC0 (_EBI_ROUTELOC0_CSLOC_LOC0 << 8) /**< Shifted mode LOC0 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_CSLOC_DEFAULT (_EBI_ROUTELOC0_CSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_CSLOC_LOC1 (_EBI_ROUTELOC0_CSLOC_LOC1 << 8) /**< Shifted mode LOC1 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_CSLOC_LOC2 (_EBI_ROUTELOC0_CSLOC_LOC2 << 8) /**< Shifted mode LOC2 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_CSLOC_LOC3 (_EBI_ROUTELOC0_CSLOC_LOC3 << 8) /**< Shifted mode LOC3 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_CSLOC_LOC4 (_EBI_ROUTELOC0_CSLOC_LOC4 << 8) /**< Shifted mode LOC4 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_NANDLOC_SHIFT 16 /**< Shift value for EBI_NANDLOC */ +#define _EBI_ROUTELOC0_NANDLOC_MASK 0x70000UL /**< Bit mask for EBI_NANDLOC */ +#define _EBI_ROUTELOC0_NANDLOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_NANDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_NANDLOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_NANDLOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_NANDLOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_NANDLOC_LOC4 0x00000004UL /**< Mode LOC4 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_NANDLOC_LOC5 0x00000005UL /**< Mode LOC5 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_NANDLOC_LOC0 (_EBI_ROUTELOC0_NANDLOC_LOC0 << 16) /**< Shifted mode LOC0 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_NANDLOC_DEFAULT (_EBI_ROUTELOC0_NANDLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_NANDLOC_LOC1 (_EBI_ROUTELOC0_NANDLOC_LOC1 << 16) /**< Shifted mode LOC1 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_NANDLOC_LOC2 (_EBI_ROUTELOC0_NANDLOC_LOC2 << 16) /**< Shifted mode LOC2 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_NANDLOC_LOC3 (_EBI_ROUTELOC0_NANDLOC_LOC3 << 16) /**< Shifted mode LOC3 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_NANDLOC_LOC4 (_EBI_ROUTELOC0_NANDLOC_LOC4 << 16) /**< Shifted mode LOC4 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_NANDLOC_LOC5 (_EBI_ROUTELOC0_NANDLOC_LOC5 << 16) /**< Shifted mode LOC5 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_TFTLOC_SHIFT 24 /**< Shift value for EBI_TFTLOC */ +#define _EBI_ROUTELOC0_TFTLOC_MASK 0x3000000UL /**< Bit mask for EBI_TFTLOC */ +#define _EBI_ROUTELOC0_TFTLOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_TFTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_TFTLOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_TFTLOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC0 */ +#define _EBI_ROUTELOC0_TFTLOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_TFTLOC_LOC0 (_EBI_ROUTELOC0_TFTLOC_LOC0 << 24) /**< Shifted mode LOC0 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_TFTLOC_DEFAULT (_EBI_ROUTELOC0_TFTLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_TFTLOC_LOC1 (_EBI_ROUTELOC0_TFTLOC_LOC1 << 24) /**< Shifted mode LOC1 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_TFTLOC_LOC2 (_EBI_ROUTELOC0_TFTLOC_LOC2 << 24) /**< Shifted mode LOC2 for EBI_ROUTELOC0 */ +#define EBI_ROUTELOC0_TFTLOC_LOC3 (_EBI_ROUTELOC0_TFTLOC_LOC3 << 24) /**< Shifted mode LOC3 for EBI_ROUTELOC0 */ + +/* Bit fields for EBI ROUTELOC1 */ +#define _EBI_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_MASK 0x00070303UL /**< Mask for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_ADLOC_SHIFT 0 /**< Shift value for EBI_ADLOC */ +#define _EBI_ROUTELOC1_ADLOC_MASK 0x3UL /**< Bit mask for EBI_ADLOC */ +#define _EBI_ROUTELOC1_ADLOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_ADLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_ADLOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_ADLOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_ADLOC_LOC0 (_EBI_ROUTELOC1_ADLOC_LOC0 << 0) /**< Shifted mode LOC0 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_ADLOC_DEFAULT (_EBI_ROUTELOC1_ADLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_ADLOC_LOC1 (_EBI_ROUTELOC1_ADLOC_LOC1 << 0) /**< Shifted mode LOC1 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_ADLOC_LOC2 (_EBI_ROUTELOC1_ADLOC_LOC2 << 0) /**< Shifted mode LOC2 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_ALOC_SHIFT 8 /**< Shift value for EBI_ALOC */ +#define _EBI_ROUTELOC1_ALOC_MASK 0x300UL /**< Bit mask for EBI_ALOC */ +#define _EBI_ROUTELOC1_ALOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_ALOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_ALOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_ALOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_ALOC_LOC0 (_EBI_ROUTELOC1_ALOC_LOC0 << 8) /**< Shifted mode LOC0 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_ALOC_DEFAULT (_EBI_ROUTELOC1_ALOC_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_ALOC_LOC1 (_EBI_ROUTELOC1_ALOC_LOC1 << 8) /**< Shifted mode LOC1 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_ALOC_LOC2 (_EBI_ROUTELOC1_ALOC_LOC2 << 8) /**< Shifted mode LOC2 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_ALOC_LOC3 (_EBI_ROUTELOC1_ALOC_LOC3 << 8) /**< Shifted mode LOC3 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_RDYLOC_SHIFT 16 /**< Shift value for EBI_RDYLOC */ +#define _EBI_ROUTELOC1_RDYLOC_MASK 0x70000UL /**< Bit mask for EBI_RDYLOC */ +#define _EBI_ROUTELOC1_RDYLOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_RDYLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_RDYLOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_RDYLOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_RDYLOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_RDYLOC_LOC4 0x00000004UL /**< Mode LOC4 for EBI_ROUTELOC1 */ +#define _EBI_ROUTELOC1_RDYLOC_LOC5 0x00000005UL /**< Mode LOC5 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_RDYLOC_LOC0 (_EBI_ROUTELOC1_RDYLOC_LOC0 << 16) /**< Shifted mode LOC0 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_RDYLOC_DEFAULT (_EBI_ROUTELOC1_RDYLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_RDYLOC_LOC1 (_EBI_ROUTELOC1_RDYLOC_LOC1 << 16) /**< Shifted mode LOC1 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_RDYLOC_LOC2 (_EBI_ROUTELOC1_RDYLOC_LOC2 << 16) /**< Shifted mode LOC2 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_RDYLOC_LOC3 (_EBI_ROUTELOC1_RDYLOC_LOC3 << 16) /**< Shifted mode LOC3 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_RDYLOC_LOC4 (_EBI_ROUTELOC1_RDYLOC_LOC4 << 16) /**< Shifted mode LOC4 for EBI_ROUTELOC1 */ +#define EBI_ROUTELOC1_RDYLOC_LOC5 (_EBI_ROUTELOC1_RDYLOC_LOC5 << 16) /**< Shifted mode LOC5 for EBI_ROUTELOC1 */ + +/** @} */ +/** @} End of group EFM32GG11B_EBI */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_emu.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_emu.h new file mode 100644 index 0000000000000..80199af3f7628 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_emu.h @@ -0,0 +1,1978 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_EMU register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_EMU EMU + * @{ + * @brief EFM32GG11B_EMU Register Declaration + ******************************************************************************/ +/** EMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ + __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t PWRCTRL; /**< Power Control Register */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED4[1U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ + __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ + + uint32_t RESERVED7[3U]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ + __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ + + uint32_t RESERVED9[2U]; /**< Reserved for future use **/ + __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ + + uint32_t RESERVED10[3U]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ + __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ + + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ + + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ +} EMU_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_EMU + * @{ + * @defgroup EFM32GG11B_EMU_BitFields EMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ +#define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ +#define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ +#define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ +#define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ +#define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ +#define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ +#define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ +#define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ +#define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ +#define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ +#define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ +#define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ +#define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ +#define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ +#define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ +#define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ +#define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ +#define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ +#define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ +#define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ +#define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ +#define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ +#define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ +#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ +#define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ +#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ + +/* Bit fields for EMU VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ +#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ + +/* Bit fields for EMU BUCTRL */ +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ +#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ +#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ +#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ +#define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ +#define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ +#define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ +#define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ +#define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ +#define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ +#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ +#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ +#define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ +#define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ +#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ + +/* Bit fields for EMU R5VCTRL */ +#define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ +#define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ +#define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ +#define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ +#define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ +#define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ +#define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ +#define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ +#define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ + +/* Bit fields for EMU R5VADCCTRL */ +#define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ +#define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ +#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ +#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ +#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ +#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ + +/* Bit fields for EMU R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ +#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ +#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ + +/* Bit fields for EMU R5VDETCTRL */ +#define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ +#define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ +#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ +#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ +#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ +#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ +#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU R5VSTATUS */ +#define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ +#define _EMU_R5VSTATUS_MASK 0x0000003FUL /**< Mask for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ +#define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ +#define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSDET (0x1UL << 1) /**< USB VBUS Detected */ +#define _EMU_R5VSTATUS_VBUSDET_SHIFT 1 /**< Shift value for EMU_VBUSDET */ +#define _EMU_R5VSTATUS_VBUSDET_MASK 0x2UL /**< Bit mask for EMU_VBUSDET */ +#define _EMU_R5VSTATUS_VBUSDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSDET_DEFAULT (_EMU_R5VSTATUS_VBUSDET_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ +#define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ +#define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ +#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ +#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ +#define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ +#define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ +#define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ + +/* Bit fields for EMU R5VSYNC */ +#define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ +#define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ +#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ +#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x01FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_USBUNLOCK (0x1UL << 24) /**< Clears Status Bit of USB and Unlocks Access to It */ +#define _EMU_EM23PERNORETAINCMD_USBUNLOCK_SHIFT 24 /**< Shift value for EMU_USBUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_USBUNLOCK_MASK 0x1000000UL /**< Bit mask for EMU_USBUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x01FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_USBLOCKED (0x1UL << 24) /**< Indicates If USB Powered Down During EM23 */ +#define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_SHIFT 24 /**< Shift value for EMU_USBLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_MASK 0x1000000UL /**< Bit mask for EMU_USBLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x01FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ +#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ +#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_USBDIS (0x1UL << 24) /**< Allow Power Down of USB During EM23 */ +#define _EMU_EM23PERNORETAINCTRL_USBDIS_SHIFT 24 /**< Shift value for EMU_USBDIS */ +#define _EMU_EM23PERNORETAINCTRL_USBDIS_MASK 0x1000000UL /**< Bit mask for EMU_USBDIS */ +#define _EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} */ +/** @} End of group EFM32GG11B_EMU */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_eth.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_eth.h new file mode 100644 index 0000000000000..adba320f957a5 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_eth.h @@ -0,0 +1,2365 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_ETH register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_ETH ETH + * @{ + * @brief EFM32GG11B_ETH Register Declaration + ******************************************************************************/ +/** ETH Register Declaration */ +typedef struct { + __IOM uint32_t NETWORKCTRL; /**< Network control register */ + __IOM uint32_t NETWORKCFG; /**< Network configuration register */ + __IM uint32_t NETWORKSTATUS; /**< Network status register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t DMACFG; /**< DMA Configuration Register */ + __IOM uint32_t TXSTATUS; /**< Transmit status register */ + __IOM uint32_t RXQPTR; /**< Start address of the receive buffer queue */ + __IOM uint32_t TXQPTR; /**< Start address of the transmit buffer queue */ + __IOM uint32_t RXSTATUS; /**< Receive status register */ + __IOM uint32_t IFCR; /**< Interrupt status register */ + __IOM uint32_t IENS; /**< Interrupt Enable Register */ + __IOM uint32_t IENC; /**< Interrupt Disable Register */ + __IOM uint32_t IENRO; /**< Interrupt mask register */ + __IOM uint32_t PHYMNGMNT; /**< PHY management register */ + __IM uint32_t RXPAUSEQUANT; /**< Received Pause Quantum Register */ + __IOM uint32_t TXPAUSEQUANT; /**< Transmit Pause Quantum Register */ + __IOM uint32_t PBUFTXCUTTHRU; /**< TX Partial Store and Forward */ + __IOM uint32_t PBUFRXCUTTHRU; /**< RX Partial Store and Forward */ + __IOM uint32_t JUMBOMAXLEN; /**< Maximum Jumbo Frame Size. */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IOM uint32_t IMOD; /**< Interrupt moderation register */ + __IOM uint32_t SYSWAKETIME; /**< System wake time */ + uint32_t RESERVED2[7U]; /**< Reserved for future use **/ + __IOM uint32_t HASHBOTTOM; /**< Hash Register Bottom [31:0] */ + __IOM uint32_t HASHTOP; /**< Hash Register Top [63:32] */ + __IOM uint32_t SPECADDR1BOTTOM; /**< Specific Address 1 Bottom */ + __IOM uint32_t SPECADDR1TOP; /**< Specific Address 1 Top */ + __IOM uint32_t SPECADDR2BOTTOM; /**< Specific Address 2 Bottom */ + __IOM uint32_t SPECADDR2TOP; /**< Specific Address 2 Top */ + __IOM uint32_t SPECADDR3BOTTOM; /**< Specific Address 3 Bottom */ + __IOM uint32_t SPECADDR3TOP; /**< Specific Address 3 Top */ + __IOM uint32_t SPECADDR4BOTTOM; /**< Specific Address 4 Bottom */ + __IOM uint32_t SPECADDR4TOP; /**< Specific Address 4 Top */ + __IOM uint32_t SPECTYPE1; /**< Type ID Match 1 */ + __IOM uint32_t SPECTYPE2; /**< Type ID Match 2 */ + __IOM uint32_t SPECTYPE3; /**< Type ID Match 3 */ + __IOM uint32_t SPECTYPE4; /**< Type ID Match 4 */ + __IOM uint32_t WOLREG; /**< Wake on LAN Register */ + __IOM uint32_t STRETCHRATIO; /**< IPG stretch register */ + __IOM uint32_t STACKEDVLAN; /**< Stacked VLAN Register */ + __IOM uint32_t TXPFCPAUSE; /**< Transmit PFC Pause Register */ + __IOM uint32_t MASKADD1BOTTOM; /**< Specific Address Mask 1 Bottom 31:0 */ + __IOM uint32_t MASKADD1TOP; /**< Specific Address Mask 1 Top 47:32 */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t RXPTPUNICAST; /**< PTP RX unicast IP destination address */ + __IOM uint32_t TXPTPUNICAST; /**< PTP TX unicast IP destination address */ + __IOM uint32_t TSUNSECCMP; /**< TSU timer comparison value nanoseconds */ + __IOM uint32_t TSUSECCMP; /**< TSU timer comparison value seconds [31:0] */ + __IOM uint32_t TSUMSBSECCMP; /**< TSU timer comparison value seconds [47:32] */ + __IM uint32_t TSUPTPTXMSBSEC; /**< PTP Event Frame Transmitted Seconds Register 47:32 */ + __IM uint32_t TSUPTPRXMSBSEC; /**< PTP Event Frame Received Seconds Register 47:32 */ + __IM uint32_t TSUPEERTXMSBSEC; /**< PTP Peer Event Frame Transmitted Seconds Register 47:32 */ + __IM uint32_t TSUPEERRXMSBSEC; /**< PTP Peer Event Frame Received Seconds Register 47:32 */ + + uint32_t RESERVED4[2U]; /**< Reserved for future use **/ + __IOM uint32_t OCTETSTXEDBOTTOM; /**< Octets transmitted 31:0 */ + __IOM uint32_t OCTETSTXEDTOP; /**< Octets Transmitted 47:32 */ + __IOM uint32_t FRAMESTXEDOK; /**< Frames Transmitted */ + __IOM uint32_t BROADCASTTXED; /**< Broadcast Frames Transmitted */ + __IOM uint32_t MULTICASTTXED; /**< Multicast Frames Transmitted */ + __IOM uint32_t PFRAMESTXED; /**< Pause Frames Transmitted */ + __IOM uint32_t FRAMESTXED64; /**< 64 Byte Frames Transmitted */ + __IOM uint32_t FRAMESTXED65; /**< 65 to 127 Byte Frames Transmitted */ + __IOM uint32_t FRAMESTXED128; /**< 128 to 255 Byte Frames Transmitted */ + __IOM uint32_t FRAMESTXED256; /**< 256 to 511 Byte Frames Transmitted */ + __IOM uint32_t FRAMESTXED512; /**< 512 to 1023 Byte Frames Transmitted */ + __IOM uint32_t FRAMESTXED1024; /**< 1024 to 1518 Byte Frames Transmitted */ + __IOM uint32_t FRAMESTXED1519; /**< Greater Than 1518 Byte Frames Transmitted */ + __IOM uint32_t TXUNDERRUNS; /**< Transmit Under Runs */ + __IOM uint32_t SINGLECOLS; /**< Single Collision Frames */ + __IOM uint32_t MULTICOLS; /**< Multiple Collision Frames */ + __IOM uint32_t EXCESSCOLS; /**< Excessive Collisions */ + __IOM uint32_t LATECOLS; /**< Late Collisions */ + __IOM uint32_t DEFERREDFRAMES; /**< Deferred Transmission Frames */ + __IOM uint32_t CRSERRS; /**< Carrier Sense Errors */ + __IOM uint32_t OCTETSRXEDBOTTOM; /**< Octets Received 31:0 */ + __IOM uint32_t OCTETSRXEDTOP; /**< Octets Received 47:32 */ + __IOM uint32_t FRAMESRXEDOK; /**< Frames Received */ + __IOM uint32_t BROADCASTRXED; /**< Broadcast Frames Received */ + __IOM uint32_t MULTICASTRXED; /**< Multicast Frames Received */ + __IOM uint32_t PFRAMESRXED; /**< Pause Frames Received */ + __IOM uint32_t FRAMESRXED64; /**< 64 Byte Frames Received */ + __IOM uint32_t FRAMESRXED65; /**< 65 to 127 Byte Frames Received */ + __IOM uint32_t FRAMESRXED128; /**< 128 to 255 Byte Frames Received */ + __IOM uint32_t FRAMESRXED256; /**< 256 to 511 Byte Frames Received */ + __IOM uint32_t FRAMESRXED512; /**< 512 to 1023 Byte Frames Received */ + __IOM uint32_t FRAMESRXED1024; /**< 1024 to 1518 Byte Frames Received */ + __IOM uint32_t FRAMESRXED1519; /**< 1519 to maximum Byte Frames Received */ + __IOM uint32_t UNDERSIZEFRAMES; /**< Undersized Frames Received */ + __IOM uint32_t EXCESSIVERXLEN; /**< Oversize Frames Received */ + __IOM uint32_t RXJABBERS; /**< Jabbers Received */ + __IOM uint32_t FCSERRS; /**< Frame Check Sequence Errors */ + __IOM uint32_t RXLENERRS; /**< Length Field Frame Errors */ + __IOM uint32_t RXSYMBOLERRS; /**< Receive Symbol Errors */ + __IOM uint32_t ALIGNERRS; /**< Alignment Errors */ + __IOM uint32_t RXRESOURCEERRS; /**< Receive Resource Errors */ + __IOM uint32_t RXOVERRUNS; /**< Receive Overruns */ + __IOM uint32_t RXIPCKERRS; /**< IP Header Checksum Errors */ + __IOM uint32_t RXTCPCKERRS; /**< TCP Checksum Errors */ + __IOM uint32_t RXUDPCKERRS; /**< UDP Checksum Errors */ + __IOM uint32_t AUTOFLUSHEDPKTS; /**< Receive DMA Flushed Packets */ + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IOM uint32_t TSUTIMERINCRSUBNSEC; /**< 1588 Timer Increment Register subscript nsec */ + __IOM uint32_t TSUTIMERMSBSEC; /**< 1588 Timer Seconds Register 47:32 */ + + uint32_t RESERVED6[3U]; /**< Reserved for future use **/ + __IOM uint32_t TSUTIMERSEC; /**< 1588 Timer Seconds Register 31:0 */ + __IOM uint32_t TSUTIMERNSEC; /**< 1588 Timer Nanoseconds Register */ + __IOM uint32_t TSUTIMERADJUST; /**< This register returns all zeroes when read. */ + __IOM uint32_t TSUTIMERINCR; /**< 1588 Timer Increment Register */ + __IM uint32_t TSUPTPTXSEC; /**< PTP Event Frame Transmitted Seconds Register 31:0 */ + __IM uint32_t TSUPTPTXNSEC; /**< PTP Event Frame Transmitted Nanoseconds Register */ + __IM uint32_t TSUPTPRXSEC; /**< PTP Event Frame Received Seconds Register 31:0 */ + __IM uint32_t TSUPTPRXNSEC; /**< PTP Event Frame Received Nanoseconds Register */ + __IM uint32_t TSUPEERTXSEC; /**< PTP Peer Event Frame Transmitted Seconds Register 31:0 */ + __IM uint32_t TSUPEERTXNSEC; /**< PTP Peer Event Frame Transmitted Nanoseconds Register */ + __IM uint32_t TSUPEERRXSEC; /**< PTP Peer Event Frame Received Seconds Register 31:0 */ + __IM uint32_t TSUPEERRXNSEC; /**< PTP Peer Event Frame Received Nanoseconds Register */ + + uint32_t RESERVED7[24U]; /**< Reserved for future use **/ + __IOM uint32_t TXPAUSEQUANT1; /**< Transmit Pause Quantum Register 1 */ + __IOM uint32_t TXPAUSEQUANT2; /**< Transmit Pause Quantum Register 2 */ + __IOM uint32_t TXPAUSEQUANT3; /**< Transmit Pause Quantum Register 3 */ + uint32_t RESERVED8[1U]; /**< Reserved for future use **/ + __IOM uint32_t RXLPI; /**< Received LPI transitions */ + __IOM uint32_t RXLPITIME; /**< Received LPI time */ + __IOM uint32_t TXLPI; /**< Transmit LPI transitions */ + __IOM uint32_t TXLPITIME; /**< Transmit LPI time */ + + uint32_t RESERVED9[147U]; /**< Reserved for future use **/ + __IOM uint32_t TXBDCTRL; /**< TX BD control register */ + __IOM uint32_t RXBDCTRL; /**< RX BD control register */ + + uint32_t RESERVED10[459U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Route Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Route Location Register 0 */ + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC1; /**< I/O Route Location Register 1 */ + __IOM uint32_t CTRL; /**< Ethernet control register */ +} ETH_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_ETH + * @{ + * @defgroup EFM32GG11B_ETH_BitFields ETH Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for ETH NETWORKCTRL */ +#define _ETH_NETWORKCTRL_RESETVALUE 0x00000000UL /**< Default value for ETH_NETWORKCTRL */ +#define _ETH_NETWORKCTRL_MASK 0x035F9FFEUL /**< Mask for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_LOOPBACKLOCAL (0x1UL << 1) /**< Loopback local */ +#define _ETH_NETWORKCTRL_LOOPBACKLOCAL_SHIFT 1 /**< Shift value for ETH_LOOPBACKLOCAL */ +#define _ETH_NETWORKCTRL_LOOPBACKLOCAL_MASK 0x2UL /**< Bit mask for ETH_LOOPBACKLOCAL */ +#define _ETH_NETWORKCTRL_LOOPBACKLOCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_LOOPBACKLOCAL_DEFAULT (_ETH_NETWORKCTRL_LOOPBACKLOCAL_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_ENBRX (0x1UL << 2) /**< Receive enable */ +#define _ETH_NETWORKCTRL_ENBRX_SHIFT 2 /**< Shift value for ETH_ENBRX */ +#define _ETH_NETWORKCTRL_ENBRX_MASK 0x4UL /**< Bit mask for ETH_ENBRX */ +#define _ETH_NETWORKCTRL_ENBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_ENBRX_DEFAULT (_ETH_NETWORKCTRL_ENBRX_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_ENBTX (0x1UL << 3) /**< Transmit enable */ +#define _ETH_NETWORKCTRL_ENBTX_SHIFT 3 /**< Shift value for ETH_ENBTX */ +#define _ETH_NETWORKCTRL_ENBTX_MASK 0x8UL /**< Bit mask for ETH_ENBTX */ +#define _ETH_NETWORKCTRL_ENBTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_ENBTX_DEFAULT (_ETH_NETWORKCTRL_ENBTX_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_MANPORTEN (0x1UL << 4) /**< Management port enable */ +#define _ETH_NETWORKCTRL_MANPORTEN_SHIFT 4 /**< Shift value for ETH_MANPORTEN */ +#define _ETH_NETWORKCTRL_MANPORTEN_MASK 0x10UL /**< Bit mask for ETH_MANPORTEN */ +#define _ETH_NETWORKCTRL_MANPORTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_MANPORTEN_DEFAULT (_ETH_NETWORKCTRL_MANPORTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_CLRALLSTATSREGS (0x1UL << 5) /**< Clear statistics registers */ +#define _ETH_NETWORKCTRL_CLRALLSTATSREGS_SHIFT 5 /**< Shift value for ETH_CLRALLSTATSREGS */ +#define _ETH_NETWORKCTRL_CLRALLSTATSREGS_MASK 0x20UL /**< Bit mask for ETH_CLRALLSTATSREGS */ +#define _ETH_NETWORKCTRL_CLRALLSTATSREGS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_CLRALLSTATSREGS_DEFAULT (_ETH_NETWORKCTRL_CLRALLSTATSREGS_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_INCALLSTATSREGS (0x1UL << 6) /**< Incremental statistics registers */ +#define _ETH_NETWORKCTRL_INCALLSTATSREGS_SHIFT 6 /**< Shift value for ETH_INCALLSTATSREGS */ +#define _ETH_NETWORKCTRL_INCALLSTATSREGS_MASK 0x40UL /**< Bit mask for ETH_INCALLSTATSREGS */ +#define _ETH_NETWORKCTRL_INCALLSTATSREGS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_INCALLSTATSREGS_DEFAULT (_ETH_NETWORKCTRL_INCALLSTATSREGS_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_STATSWREN (0x1UL << 7) /**< Write enable for statistics registers */ +#define _ETH_NETWORKCTRL_STATSWREN_SHIFT 7 /**< Shift value for ETH_STATSWREN */ +#define _ETH_NETWORKCTRL_STATSWREN_MASK 0x80UL /**< Bit mask for ETH_STATSWREN */ +#define _ETH_NETWORKCTRL_STATSWREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_STATSWREN_DEFAULT (_ETH_NETWORKCTRL_STATSWREN_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_BACKPRESSURE (0x1UL << 8) /**< Back pressure will force collisions on all received frames */ +#define _ETH_NETWORKCTRL_BACKPRESSURE_SHIFT 8 /**< Shift value for ETH_BACKPRESSURE */ +#define _ETH_NETWORKCTRL_BACKPRESSURE_MASK 0x100UL /**< Bit mask for ETH_BACKPRESSURE */ +#define _ETH_NETWORKCTRL_BACKPRESSURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_BACKPRESSURE_DEFAULT (_ETH_NETWORKCTRL_BACKPRESSURE_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXSTRT (0x1UL << 9) /**< Start transmission */ +#define _ETH_NETWORKCTRL_TXSTRT_SHIFT 9 /**< Shift value for ETH_TXSTRT */ +#define _ETH_NETWORKCTRL_TXSTRT_MASK 0x200UL /**< Bit mask for ETH_TXSTRT */ +#define _ETH_NETWORKCTRL_TXSTRT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXSTRT_DEFAULT (_ETH_NETWORKCTRL_TXSTRT_DEFAULT << 9) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXHALT (0x1UL << 10) /**< Transmit halt */ +#define _ETH_NETWORKCTRL_TXHALT_SHIFT 10 /**< Shift value for ETH_TXHALT */ +#define _ETH_NETWORKCTRL_TXHALT_MASK 0x400UL /**< Bit mask for ETH_TXHALT */ +#define _ETH_NETWORKCTRL_TXHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXHALT_DEFAULT (_ETH_NETWORKCTRL_TXHALT_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXPFRMREQ (0x1UL << 11) /**< Transmit pause frame */ +#define _ETH_NETWORKCTRL_TXPFRMREQ_SHIFT 11 /**< Shift value for ETH_TXPFRMREQ */ +#define _ETH_NETWORKCTRL_TXPFRMREQ_MASK 0x800UL /**< Bit mask for ETH_TXPFRMREQ */ +#define _ETH_NETWORKCTRL_TXPFRMREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXPFRMREQ_DEFAULT (_ETH_NETWORKCTRL_TXPFRMREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXPFRMZERO (0x1UL << 12) /**< Transmit zero quantum pause frame */ +#define _ETH_NETWORKCTRL_TXPFRMZERO_SHIFT 12 /**< Shift value for ETH_TXPFRMZERO */ +#define _ETH_NETWORKCTRL_TXPFRMZERO_MASK 0x1000UL /**< Bit mask for ETH_TXPFRMZERO */ +#define _ETH_NETWORKCTRL_TXPFRMZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXPFRMZERO_DEFAULT (_ETH_NETWORKCTRL_TXPFRMZERO_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_STORERXTS (0x1UL << 15) /**< Store receive time stamp to memory. */ +#define _ETH_NETWORKCTRL_STORERXTS_SHIFT 15 /**< Shift value for ETH_STORERXTS */ +#define _ETH_NETWORKCTRL_STORERXTS_MASK 0x8000UL /**< Bit mask for ETH_STORERXTS */ +#define _ETH_NETWORKCTRL_STORERXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_STORERXTS_DEFAULT (_ETH_NETWORKCTRL_STORERXTS_DEFAULT << 15) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_PFCENB (0x1UL << 16) /**< Enable PFC Priority Based Pause Reception capabilities. */ +#define _ETH_NETWORKCTRL_PFCENB_SHIFT 16 /**< Shift value for ETH_PFCENB */ +#define _ETH_NETWORKCTRL_PFCENB_MASK 0x10000UL /**< Bit mask for ETH_PFCENB */ +#define _ETH_NETWORKCTRL_PFCENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_PFCENB_DEFAULT (_ETH_NETWORKCTRL_PFCENB_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXPFCPRIORPFRM (0x1UL << 17) /**< Write a one to transmit PFC priority based pause frame. */ +#define _ETH_NETWORKCTRL_TXPFCPRIORPFRM_SHIFT 17 /**< Shift value for ETH_TXPFCPRIORPFRM */ +#define _ETH_NETWORKCTRL_TXPFCPRIORPFRM_MASK 0x20000UL /**< Bit mask for ETH_TXPFCPRIORPFRM */ +#define _ETH_NETWORKCTRL_TXPFCPRIORPFRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXPFCPRIORPFRM_DEFAULT (_ETH_NETWORKCTRL_TXPFCPRIORPFRM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_FLUSHRXPKT (0x1UL << 18) /**< Flush the next packet from the external RX DPRAM. */ +#define _ETH_NETWORKCTRL_FLUSHRXPKT_SHIFT 18 /**< Shift value for ETH_FLUSHRXPKT */ +#define _ETH_NETWORKCTRL_FLUSHRXPKT_MASK 0x40000UL /**< Bit mask for ETH_FLUSHRXPKT */ +#define _ETH_NETWORKCTRL_FLUSHRXPKT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_FLUSHRXPKT_DEFAULT (_ETH_NETWORKCTRL_FLUSHRXPKT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXLPIEN (0x1UL << 19) /**< Enable LPI transmission when set LPI (low power idle) is immediately transmitted. */ +#define _ETH_NETWORKCTRL_TXLPIEN_SHIFT 19 /**< Shift value for ETH_TXLPIEN */ +#define _ETH_NETWORKCTRL_TXLPIEN_MASK 0x80000UL /**< Bit mask for ETH_TXLPIEN */ +#define _ETH_NETWORKCTRL_TXLPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_TXLPIEN_DEFAULT (_ETH_NETWORKCTRL_TXLPIEN_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_PTPUNICASTEN (0x1UL << 20) /**< Enable detection of unicast PTP unicast frames. */ +#define _ETH_NETWORKCTRL_PTPUNICASTEN_SHIFT 20 /**< Shift value for ETH_PTPUNICASTEN */ +#define _ETH_NETWORKCTRL_PTPUNICASTEN_MASK 0x100000UL /**< Bit mask for ETH_PTPUNICASTEN */ +#define _ETH_NETWORKCTRL_PTPUNICASTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_PTPUNICASTEN_DEFAULT (_ETH_NETWORKCTRL_PTPUNICASTEN_DEFAULT << 20) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_STOREUDPOFFSET (0x1UL << 22) /**< Store UDP / TCP offset to memory. */ +#define _ETH_NETWORKCTRL_STOREUDPOFFSET_SHIFT 22 /**< Shift value for ETH_STOREUDPOFFSET */ +#define _ETH_NETWORKCTRL_STOREUDPOFFSET_MASK 0x400000UL /**< Bit mask for ETH_STOREUDPOFFSET */ +#define _ETH_NETWORKCTRL_STOREUDPOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_STOREUDPOFFSET_DEFAULT (_ETH_NETWORKCTRL_STOREUDPOFFSET_DEFAULT << 22) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_ONESTEPSYNCMODE (0x1UL << 24) /**< 1588 One Step Sync Mode. */ +#define _ETH_NETWORKCTRL_ONESTEPSYNCMODE_SHIFT 24 /**< Shift value for ETH_ONESTEPSYNCMODE */ +#define _ETH_NETWORKCTRL_ONESTEPSYNCMODE_MASK 0x1000000UL /**< Bit mask for ETH_ONESTEPSYNCMODE */ +#define _ETH_NETWORKCTRL_ONESTEPSYNCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_ONESTEPSYNCMODE_DEFAULT (_ETH_NETWORKCTRL_ONESTEPSYNCMODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_PFCCTRL (0x1UL << 25) /**< Enable multiple PFC pause quantums, one per pause priority */ +#define _ETH_NETWORKCTRL_PFCCTRL_SHIFT 25 /**< Shift value for ETH_PFCCTRL */ +#define _ETH_NETWORKCTRL_PFCCTRL_MASK 0x2000000UL /**< Bit mask for ETH_PFCCTRL */ +#define _ETH_NETWORKCTRL_PFCCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ +#define ETH_NETWORKCTRL_PFCCTRL_DEFAULT (_ETH_NETWORKCTRL_PFCCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ + +/* Bit fields for ETH NETWORKCFG */ +#define _ETH_NETWORKCFG_RESETVALUE 0x00080000UL /**< Default value for ETH_NETWORKCFG */ +#define _ETH_NETWORKCFG_MASK 0x779FF1FFUL /**< Mask for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_SPEED (0x1UL << 0) /**< Speed */ +#define _ETH_NETWORKCFG_SPEED_SHIFT 0 /**< Shift value for ETH_SPEED */ +#define _ETH_NETWORKCFG_SPEED_MASK 0x1UL /**< Bit mask for ETH_SPEED */ +#define _ETH_NETWORKCFG_SPEED_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_SPEED_DEFAULT (_ETH_NETWORKCFG_SPEED_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_FULLDUPLEX (0x1UL << 1) /**< Full duplex */ +#define _ETH_NETWORKCFG_FULLDUPLEX_SHIFT 1 /**< Shift value for ETH_FULLDUPLEX */ +#define _ETH_NETWORKCFG_FULLDUPLEX_MASK 0x2UL /**< Bit mask for ETH_FULLDUPLEX */ +#define _ETH_NETWORKCFG_FULLDUPLEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_FULLDUPLEX_DEFAULT (_ETH_NETWORKCFG_FULLDUPLEX_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_DISCRDNONVLANFRAMES (0x1UL << 2) /**< Discard non-VLAN frames */ +#define _ETH_NETWORKCFG_DISCRDNONVLANFRAMES_SHIFT 2 /**< Shift value for ETH_DISCRDNONVLANFRAMES */ +#define _ETH_NETWORKCFG_DISCRDNONVLANFRAMES_MASK 0x4UL /**< Bit mask for ETH_DISCRDNONVLANFRAMES */ +#define _ETH_NETWORKCFG_DISCRDNONVLANFRAMES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_DISCRDNONVLANFRAMES_DEFAULT (_ETH_NETWORKCFG_DISCRDNONVLANFRAMES_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_JUMBOFRAMES (0x1UL << 3) /**< Jumbo frames enable */ +#define _ETH_NETWORKCFG_JUMBOFRAMES_SHIFT 3 /**< Shift value for ETH_JUMBOFRAMES */ +#define _ETH_NETWORKCFG_JUMBOFRAMES_MASK 0x8UL /**< Bit mask for ETH_JUMBOFRAMES */ +#define _ETH_NETWORKCFG_JUMBOFRAMES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_JUMBOFRAMES_DEFAULT (_ETH_NETWORKCFG_JUMBOFRAMES_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_COPYALLFRAMES (0x1UL << 4) /**< Copy all frames */ +#define _ETH_NETWORKCFG_COPYALLFRAMES_SHIFT 4 /**< Shift value for ETH_COPYALLFRAMES */ +#define _ETH_NETWORKCFG_COPYALLFRAMES_MASK 0x10UL /**< Bit mask for ETH_COPYALLFRAMES */ +#define _ETH_NETWORKCFG_COPYALLFRAMES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_COPYALLFRAMES_DEFAULT (_ETH_NETWORKCFG_COPYALLFRAMES_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_NOBROADCAST (0x1UL << 5) /**< No broadcast */ +#define _ETH_NETWORKCFG_NOBROADCAST_SHIFT 5 /**< Shift value for ETH_NOBROADCAST */ +#define _ETH_NETWORKCFG_NOBROADCAST_MASK 0x20UL /**< Bit mask for ETH_NOBROADCAST */ +#define _ETH_NETWORKCFG_NOBROADCAST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_NOBROADCAST_DEFAULT (_ETH_NETWORKCFG_NOBROADCAST_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_MULTICASTHASHEN (0x1UL << 6) /**< Multicast hash enable */ +#define _ETH_NETWORKCFG_MULTICASTHASHEN_SHIFT 6 /**< Shift value for ETH_MULTICASTHASHEN */ +#define _ETH_NETWORKCFG_MULTICASTHASHEN_MASK 0x40UL /**< Bit mask for ETH_MULTICASTHASHEN */ +#define _ETH_NETWORKCFG_MULTICASTHASHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_MULTICASTHASHEN_DEFAULT (_ETH_NETWORKCFG_MULTICASTHASHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_UNICASTHASHEN (0x1UL << 7) /**< Unicast hash enable */ +#define _ETH_NETWORKCFG_UNICASTHASHEN_SHIFT 7 /**< Shift value for ETH_UNICASTHASHEN */ +#define _ETH_NETWORKCFG_UNICASTHASHEN_MASK 0x80UL /**< Bit mask for ETH_UNICASTHASHEN */ +#define _ETH_NETWORKCFG_UNICASTHASHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_UNICASTHASHEN_DEFAULT (_ETH_NETWORKCFG_UNICASTHASHEN_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_RX1536BYTEFRAMES (0x1UL << 8) /**< Receive 1536 byte frames */ +#define _ETH_NETWORKCFG_RX1536BYTEFRAMES_SHIFT 8 /**< Shift value for ETH_RX1536BYTEFRAMES */ +#define _ETH_NETWORKCFG_RX1536BYTEFRAMES_MASK 0x100UL /**< Bit mask for ETH_RX1536BYTEFRAMES */ +#define _ETH_NETWORKCFG_RX1536BYTEFRAMES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_RX1536BYTEFRAMES_DEFAULT (_ETH_NETWORKCFG_RX1536BYTEFRAMES_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_RETRYTEST (0x1UL << 12) /**< Retry test */ +#define _ETH_NETWORKCFG_RETRYTEST_SHIFT 12 /**< Shift value for ETH_RETRYTEST */ +#define _ETH_NETWORKCFG_RETRYTEST_MASK 0x1000UL /**< Bit mask for ETH_RETRYTEST */ +#define _ETH_NETWORKCFG_RETRYTEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_RETRYTEST_DEFAULT (_ETH_NETWORKCFG_RETRYTEST_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_PAUSEEN (0x1UL << 13) /**< Pause enable */ +#define _ETH_NETWORKCFG_PAUSEEN_SHIFT 13 /**< Shift value for ETH_PAUSEEN */ +#define _ETH_NETWORKCFG_PAUSEEN_MASK 0x2000UL /**< Bit mask for ETH_PAUSEEN */ +#define _ETH_NETWORKCFG_PAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_PAUSEEN_DEFAULT (_ETH_NETWORKCFG_PAUSEEN_DEFAULT << 13) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define _ETH_NETWORKCFG_RXBUFFOFFSET_SHIFT 14 /**< Shift value for ETH_RXBUFFOFFSET */ +#define _ETH_NETWORKCFG_RXBUFFOFFSET_MASK 0xC000UL /**< Bit mask for ETH_RXBUFFOFFSET */ +#define _ETH_NETWORKCFG_RXBUFFOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_RXBUFFOFFSET_DEFAULT (_ETH_NETWORKCFG_RXBUFFOFFSET_DEFAULT << 14) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_LENFIELDERRFRMDISCRD (0x1UL << 16) /**< Length field error frame discard */ +#define _ETH_NETWORKCFG_LENFIELDERRFRMDISCRD_SHIFT 16 /**< Shift value for ETH_LENFIELDERRFRMDISCRD */ +#define _ETH_NETWORKCFG_LENFIELDERRFRMDISCRD_MASK 0x10000UL /**< Bit mask for ETH_LENFIELDERRFRMDISCRD */ +#define _ETH_NETWORKCFG_LENFIELDERRFRMDISCRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_LENFIELDERRFRMDISCRD_DEFAULT (_ETH_NETWORKCFG_LENFIELDERRFRMDISCRD_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_FCSREMOVE (0x1UL << 17) /**< FCS remove */ +#define _ETH_NETWORKCFG_FCSREMOVE_SHIFT 17 /**< Shift value for ETH_FCSREMOVE */ +#define _ETH_NETWORKCFG_FCSREMOVE_MASK 0x20000UL /**< Bit mask for ETH_FCSREMOVE */ +#define _ETH_NETWORKCFG_FCSREMOVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_FCSREMOVE_DEFAULT (_ETH_NETWORKCFG_FCSREMOVE_DEFAULT << 17) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define _ETH_NETWORKCFG_MDCCLKDIV_SHIFT 18 /**< Shift value for ETH_MDCCLKDIV */ +#define _ETH_NETWORKCFG_MDCCLKDIV_MASK 0x1C0000UL /**< Bit mask for ETH_MDCCLKDIV */ +#define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY8 0x00000000UL /**< Mode DIVBY8 for ETH_NETWORKCFG */ +#define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY16 0x00000001UL /**< Mode DIVBY16 for ETH_NETWORKCFG */ +#define _ETH_NETWORKCFG_MDCCLKDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY32 0x00000002UL /**< Mode DIVBY32 for ETH_NETWORKCFG */ +#define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY48 0x00000003UL /**< Mode DIVBY48 for ETH_NETWORKCFG */ +#define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY64 0x00000004UL /**< Mode DIVBY64 for ETH_NETWORKCFG */ +#define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY96 0x00000005UL /**< Mode DIVBY96 for ETH_NETWORKCFG */ +#define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY128 0x00000006UL /**< Mode DIVBY128 for ETH_NETWORKCFG */ +#define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY224 0x00000007UL /**< Mode DIVBY224 for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_MDCCLKDIV_DIVBY8 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY8 << 18) /**< Shifted mode DIVBY8 for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_MDCCLKDIV_DIVBY16 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY16 << 18) /**< Shifted mode DIVBY16 for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_MDCCLKDIV_DEFAULT (_ETH_NETWORKCFG_MDCCLKDIV_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_MDCCLKDIV_DIVBY32 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY32 << 18) /**< Shifted mode DIVBY32 for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_MDCCLKDIV_DIVBY48 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY48 << 18) /**< Shifted mode DIVBY48 for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_MDCCLKDIV_DIVBY64 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY64 << 18) /**< Shifted mode DIVBY64 for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_MDCCLKDIV_DIVBY96 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY96 << 18) /**< Shifted mode DIVBY96 for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_MDCCLKDIV_DIVBY128 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY128 << 18) /**< Shifted mode DIVBY128 for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_MDCCLKDIV_DIVBY224 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY224 << 18) /**< Shifted mode DIVBY224 for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_DISCOPYOFPFRAMES (0x1UL << 23) /**< Disable copy of pause frames */ +#define _ETH_NETWORKCFG_DISCOPYOFPFRAMES_SHIFT 23 /**< Shift value for ETH_DISCOPYOFPFRAMES */ +#define _ETH_NETWORKCFG_DISCOPYOFPFRAMES_MASK 0x800000UL /**< Bit mask for ETH_DISCOPYOFPFRAMES */ +#define _ETH_NETWORKCFG_DISCOPYOFPFRAMES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_DISCOPYOFPFRAMES_DEFAULT (_ETH_NETWORKCFG_DISCOPYOFPFRAMES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_RXCHKSUMOFFLOADEN (0x1UL << 24) /**< Receive checksum offload enable */ +#define _ETH_NETWORKCFG_RXCHKSUMOFFLOADEN_SHIFT 24 /**< Shift value for ETH_RXCHKSUMOFFLOADEN */ +#define _ETH_NETWORKCFG_RXCHKSUMOFFLOADEN_MASK 0x1000000UL /**< Bit mask for ETH_RXCHKSUMOFFLOADEN */ +#define _ETH_NETWORKCFG_RXCHKSUMOFFLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_RXCHKSUMOFFLOADEN_DEFAULT (_ETH_NETWORKCFG_RXCHKSUMOFFLOADEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_ENHALFDUPLEXRX (0x1UL << 25) /**< Enable frames to be received in half-duplex mode while transmitting. */ +#define _ETH_NETWORKCFG_ENHALFDUPLEXRX_SHIFT 25 /**< Shift value for ETH_ENHALFDUPLEXRX */ +#define _ETH_NETWORKCFG_ENHALFDUPLEXRX_MASK 0x2000000UL /**< Bit mask for ETH_ENHALFDUPLEXRX */ +#define _ETH_NETWORKCFG_ENHALFDUPLEXRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_ENHALFDUPLEXRX_DEFAULT (_ETH_NETWORKCFG_ENHALFDUPLEXRX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_IGNORERXFCS (0x1UL << 26) /**< Ignore RX FCS */ +#define _ETH_NETWORKCFG_IGNORERXFCS_SHIFT 26 /**< Shift value for ETH_IGNORERXFCS */ +#define _ETH_NETWORKCFG_IGNORERXFCS_MASK 0x4000000UL /**< Bit mask for ETH_IGNORERXFCS */ +#define _ETH_NETWORKCFG_IGNORERXFCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_IGNORERXFCS_DEFAULT (_ETH_NETWORKCFG_IGNORERXFCS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_IPGSTRTCHEN (0x1UL << 28) /**< IPG stretch enable */ +#define _ETH_NETWORKCFG_IPGSTRTCHEN_SHIFT 28 /**< Shift value for ETH_IPGSTRTCHEN */ +#define _ETH_NETWORKCFG_IPGSTRTCHEN_MASK 0x10000000UL /**< Bit mask for ETH_IPGSTRTCHEN */ +#define _ETH_NETWORKCFG_IPGSTRTCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_IPGSTRTCHEN_DEFAULT (_ETH_NETWORKCFG_IPGSTRTCHEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_NSPCHANGE (0x1UL << 29) /**< Receive bad preamble. */ +#define _ETH_NETWORKCFG_NSPCHANGE_SHIFT 29 /**< Shift value for ETH_NSPCHANGE */ +#define _ETH_NETWORKCFG_NSPCHANGE_MASK 0x20000000UL /**< Bit mask for ETH_NSPCHANGE */ +#define _ETH_NETWORKCFG_NSPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_NSPCHANGE_DEFAULT (_ETH_NETWORKCFG_NSPCHANGE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_IGNOREIPGRXER (0x1UL << 30) /**< Ignore IPG rx_er. */ +#define _ETH_NETWORKCFG_IGNOREIPGRXER_SHIFT 30 /**< Shift value for ETH_IGNOREIPGRXER */ +#define _ETH_NETWORKCFG_IGNOREIPGRXER_MASK 0x40000000UL /**< Bit mask for ETH_IGNOREIPGRXER */ +#define _ETH_NETWORKCFG_IGNOREIPGRXER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ +#define ETH_NETWORKCFG_IGNOREIPGRXER_DEFAULT (_ETH_NETWORKCFG_IGNOREIPGRXER_DEFAULT << 30) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ + +/* Bit fields for ETH NETWORKSTATUS */ +#define _ETH_NETWORKSTATUS_RESETVALUE 0x00000004UL /**< Default value for ETH_NETWORKSTATUS */ +#define _ETH_NETWORKSTATUS_MASK 0x000000C6UL /**< Mask for ETH_NETWORKSTATUS */ +#define ETH_NETWORKSTATUS_MDIOIN (0x1UL << 1) /**< Returns status of the mdio_in pin. */ +#define _ETH_NETWORKSTATUS_MDIOIN_SHIFT 1 /**< Shift value for ETH_MDIOIN */ +#define _ETH_NETWORKSTATUS_MDIOIN_MASK 0x2UL /**< Bit mask for ETH_MDIOIN */ +#define _ETH_NETWORKSTATUS_MDIOIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKSTATUS */ +#define ETH_NETWORKSTATUS_MDIOIN_DEFAULT (_ETH_NETWORKSTATUS_MDIOIN_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_NETWORKSTATUS */ +#define ETH_NETWORKSTATUS_MANDONE (0x1UL << 2) /**< The PHY management logic is idle (i.e. has completed). */ +#define _ETH_NETWORKSTATUS_MANDONE_SHIFT 2 /**< Shift value for ETH_MANDONE */ +#define _ETH_NETWORKSTATUS_MANDONE_MASK 0x4UL /**< Bit mask for ETH_MANDONE */ +#define _ETH_NETWORKSTATUS_MANDONE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_NETWORKSTATUS */ +#define ETH_NETWORKSTATUS_MANDONE_DEFAULT (_ETH_NETWORKSTATUS_MANDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_NETWORKSTATUS */ +#define ETH_NETWORKSTATUS_PFCNEGOTIATE (0x1UL << 6) /**< Set when PFC Priority Based Pause has been negotiated. */ +#define _ETH_NETWORKSTATUS_PFCNEGOTIATE_SHIFT 6 /**< Shift value for ETH_PFCNEGOTIATE */ +#define _ETH_NETWORKSTATUS_PFCNEGOTIATE_MASK 0x40UL /**< Bit mask for ETH_PFCNEGOTIATE */ +#define _ETH_NETWORKSTATUS_PFCNEGOTIATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKSTATUS */ +#define ETH_NETWORKSTATUS_PFCNEGOTIATE_DEFAULT (_ETH_NETWORKSTATUS_PFCNEGOTIATE_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_NETWORKSTATUS */ +#define ETH_NETWORKSTATUS_LPIINDICATE (0x1UL << 7) /**< LPI Indication */ +#define _ETH_NETWORKSTATUS_LPIINDICATE_SHIFT 7 /**< Shift value for ETH_LPIINDICATE */ +#define _ETH_NETWORKSTATUS_LPIINDICATE_MASK 0x80UL /**< Bit mask for ETH_LPIINDICATE */ +#define _ETH_NETWORKSTATUS_LPIINDICATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKSTATUS */ +#define ETH_NETWORKSTATUS_LPIINDICATE_DEFAULT (_ETH_NETWORKSTATUS_LPIINDICATE_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_NETWORKSTATUS */ + +/* Bit fields for ETH DMACFG */ +#define _ETH_DMACFG_RESETVALUE 0x00020704UL /**< Default value for ETH_DMACFG */ +#define _ETH_DMACFG_MASK 0x37FF1F3FUL /**< Mask for ETH_DMACFG */ +#define _ETH_DMACFG_AMBABRSTLEN_SHIFT 0 /**< Shift value for ETH_AMBABRSTLEN */ +#define _ETH_DMACFG_AMBABRSTLEN_MASK 0x1FUL /**< Bit mask for ETH_AMBABRSTLEN */ +#define _ETH_DMACFG_AMBABRSTLEN_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_AMBABRSTLEN_DEFAULT (_ETH_DMACFG_AMBABRSTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_HDRDATASPLITEN (0x1UL << 5) /**< Enable header data Splitting. */ +#define _ETH_DMACFG_HDRDATASPLITEN_SHIFT 5 /**< Shift value for ETH_HDRDATASPLITEN */ +#define _ETH_DMACFG_HDRDATASPLITEN_MASK 0x20UL /**< Bit mask for ETH_HDRDATASPLITEN */ +#define _ETH_DMACFG_HDRDATASPLITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_HDRDATASPLITEN_DEFAULT (_ETH_DMACFG_HDRDATASPLITEN_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_DMACFG */ +#define _ETH_DMACFG_RXPBUFSIZE_SHIFT 8 /**< Shift value for ETH_RXPBUFSIZE */ +#define _ETH_DMACFG_RXPBUFSIZE_MASK 0x300UL /**< Bit mask for ETH_RXPBUFSIZE */ +#define _ETH_DMACFG_RXPBUFSIZE_SIZE0 0x00000000UL /**< Mode SIZE0 for ETH_DMACFG */ +#define _ETH_DMACFG_RXPBUFSIZE_SIZE1 0x00000001UL /**< Mode SIZE1 for ETH_DMACFG */ +#define _ETH_DMACFG_RXPBUFSIZE_SIZE2 0x00000002UL /**< Mode SIZE2 for ETH_DMACFG */ +#define _ETH_DMACFG_RXPBUFSIZE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETH_DMACFG */ +#define _ETH_DMACFG_RXPBUFSIZE_SIZE3 0x00000003UL /**< Mode SIZE3 for ETH_DMACFG */ +#define ETH_DMACFG_RXPBUFSIZE_SIZE0 (_ETH_DMACFG_RXPBUFSIZE_SIZE0 << 8) /**< Shifted mode SIZE0 for ETH_DMACFG */ +#define ETH_DMACFG_RXPBUFSIZE_SIZE1 (_ETH_DMACFG_RXPBUFSIZE_SIZE1 << 8) /**< Shifted mode SIZE1 for ETH_DMACFG */ +#define ETH_DMACFG_RXPBUFSIZE_SIZE2 (_ETH_DMACFG_RXPBUFSIZE_SIZE2 << 8) /**< Shifted mode SIZE2 for ETH_DMACFG */ +#define ETH_DMACFG_RXPBUFSIZE_DEFAULT (_ETH_DMACFG_RXPBUFSIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_RXPBUFSIZE_SIZE3 (_ETH_DMACFG_RXPBUFSIZE_SIZE3 << 8) /**< Shifted mode SIZE3 for ETH_DMACFG */ +#define ETH_DMACFG_TXPBUFSIZE (0x1UL << 10) /**< Transmitter packet buffer memory size select. */ +#define _ETH_DMACFG_TXPBUFSIZE_SHIFT 10 /**< Shift value for ETH_TXPBUFSIZE */ +#define _ETH_DMACFG_TXPBUFSIZE_MASK 0x400UL /**< Bit mask for ETH_TXPBUFSIZE */ +#define _ETH_DMACFG_TXPBUFSIZE_SIZE0 0x00000000UL /**< Mode SIZE0 for ETH_DMACFG */ +#define _ETH_DMACFG_TXPBUFSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_DMACFG */ +#define _ETH_DMACFG_TXPBUFSIZE_SIZE1 0x00000001UL /**< Mode SIZE1 for ETH_DMACFG */ +#define ETH_DMACFG_TXPBUFSIZE_SIZE0 (_ETH_DMACFG_TXPBUFSIZE_SIZE0 << 10) /**< Shifted mode SIZE0 for ETH_DMACFG */ +#define ETH_DMACFG_TXPBUFSIZE_DEFAULT (_ETH_DMACFG_TXPBUFSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_TXPBUFSIZE_SIZE1 (_ETH_DMACFG_TXPBUFSIZE_SIZE1 << 10) /**< Shifted mode SIZE1 for ETH_DMACFG */ +#define ETH_DMACFG_TXPBUFTCPEN (0x1UL << 11) /**< Transmitter IP, TCP and UDP checksum generation offload enable */ +#define _ETH_DMACFG_TXPBUFTCPEN_SHIFT 11 /**< Shift value for ETH_TXPBUFTCPEN */ +#define _ETH_DMACFG_TXPBUFTCPEN_MASK 0x800UL /**< Bit mask for ETH_TXPBUFTCPEN */ +#define _ETH_DMACFG_TXPBUFTCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_TXPBUFTCPEN_DEFAULT (_ETH_DMACFG_TXPBUFTCPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_INFLASTDBUFSIZEEN (0x1UL << 12) /**< Forces the DMA */ +#define _ETH_DMACFG_INFLASTDBUFSIZEEN_SHIFT 12 /**< Shift value for ETH_INFLASTDBUFSIZEEN */ +#define _ETH_DMACFG_INFLASTDBUFSIZEEN_MASK 0x1000UL /**< Bit mask for ETH_INFLASTDBUFSIZEEN */ +#define _ETH_DMACFG_INFLASTDBUFSIZEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_INFLASTDBUFSIZEEN_DEFAULT (_ETH_DMACFG_INFLASTDBUFSIZEEN_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_DMACFG */ +#define _ETH_DMACFG_RXBUFSIZE_SHIFT 16 /**< Shift value for ETH_RXBUFSIZE */ +#define _ETH_DMACFG_RXBUFSIZE_MASK 0xFF0000UL /**< Bit mask for ETH_RXBUFSIZE */ +#define _ETH_DMACFG_RXBUFSIZE_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_RXBUFSIZE_DEFAULT (_ETH_DMACFG_RXBUFSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_FRCDISCARDONERR (0x1UL << 24) /**< Auto Discard RX pkts during lack of resource. */ +#define _ETH_DMACFG_FRCDISCARDONERR_SHIFT 24 /**< Shift value for ETH_FRCDISCARDONERR */ +#define _ETH_DMACFG_FRCDISCARDONERR_MASK 0x1000000UL /**< Bit mask for ETH_FRCDISCARDONERR */ +#define _ETH_DMACFG_FRCDISCARDONERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_FRCDISCARDONERR_DEFAULT (_ETH_DMACFG_FRCDISCARDONERR_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_FRCMAXAMBABRSTRX (0x1UL << 25) /**< Force max length bursts on RX. */ +#define _ETH_DMACFG_FRCMAXAMBABRSTRX_SHIFT 25 /**< Shift value for ETH_FRCMAXAMBABRSTRX */ +#define _ETH_DMACFG_FRCMAXAMBABRSTRX_MASK 0x2000000UL /**< Bit mask for ETH_FRCMAXAMBABRSTRX */ +#define _ETH_DMACFG_FRCMAXAMBABRSTRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_FRCMAXAMBABRSTRX_DEFAULT (_ETH_DMACFG_FRCMAXAMBABRSTRX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_FRCMAXAMBABRSTTX (0x1UL << 26) /**< Force max length bursts on TX. */ +#define _ETH_DMACFG_FRCMAXAMBABRSTTX_SHIFT 26 /**< Shift value for ETH_FRCMAXAMBABRSTTX */ +#define _ETH_DMACFG_FRCMAXAMBABRSTTX_MASK 0x4000000UL /**< Bit mask for ETH_FRCMAXAMBABRSTTX */ +#define _ETH_DMACFG_FRCMAXAMBABRSTTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_FRCMAXAMBABRSTTX_DEFAULT (_ETH_DMACFG_FRCMAXAMBABRSTTX_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_RXBDEXTNDMODEEN (0x1UL << 28) /**< Enable RX extended BD mode. */ +#define _ETH_DMACFG_RXBDEXTNDMODEEN_SHIFT 28 /**< Shift value for ETH_RXBDEXTNDMODEEN */ +#define _ETH_DMACFG_RXBDEXTNDMODEEN_MASK 0x10000000UL /**< Bit mask for ETH_RXBDEXTNDMODEEN */ +#define _ETH_DMACFG_RXBDEXTNDMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_RXBDEXTNDMODEEN_DEFAULT (_ETH_DMACFG_RXBDEXTNDMODEEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_TXBDEXTENDMODEEN (0x1UL << 29) /**< Enable TX extended BD mode. */ +#define _ETH_DMACFG_TXBDEXTENDMODEEN_SHIFT 29 /**< Shift value for ETH_TXBDEXTENDMODEEN */ +#define _ETH_DMACFG_TXBDEXTENDMODEEN_MASK 0x20000000UL /**< Bit mask for ETH_TXBDEXTENDMODEEN */ +#define _ETH_DMACFG_TXBDEXTENDMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ +#define ETH_DMACFG_TXBDEXTENDMODEEN_DEFAULT (_ETH_DMACFG_TXBDEXTENDMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_DMACFG */ + +/* Bit fields for ETH TXSTATUS */ +#define _ETH_TXSTATUS_RESETVALUE 0x00000000UL /**< Default value for ETH_TXSTATUS */ +#define _ETH_TXSTATUS_MASK 0x000001FFUL /**< Mask for ETH_TXSTATUS */ +#define ETH_TXSTATUS_USEDBITREAD (0x1UL << 0) /**< Used bit read */ +#define _ETH_TXSTATUS_USEDBITREAD_SHIFT 0 /**< Shift value for ETH_USEDBITREAD */ +#define _ETH_TXSTATUS_USEDBITREAD_MASK 0x1UL /**< Bit mask for ETH_USEDBITREAD */ +#define _ETH_TXSTATUS_USEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_USEDBITREAD_DEFAULT (_ETH_TXSTATUS_USEDBITREAD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_COLOCCRD (0x1UL << 1) /**< Collision occurred */ +#define _ETH_TXSTATUS_COLOCCRD_SHIFT 1 /**< Shift value for ETH_COLOCCRD */ +#define _ETH_TXSTATUS_COLOCCRD_MASK 0x2UL /**< Bit mask for ETH_COLOCCRD */ +#define _ETH_TXSTATUS_COLOCCRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_COLOCCRD_DEFAULT (_ETH_TXSTATUS_COLOCCRD_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_RETRYLMTEXCD (0x1UL << 2) /**< Retry limit exceeded */ +#define _ETH_TXSTATUS_RETRYLMTEXCD_SHIFT 2 /**< Shift value for ETH_RETRYLMTEXCD */ +#define _ETH_TXSTATUS_RETRYLMTEXCD_MASK 0x4UL /**< Bit mask for ETH_RETRYLMTEXCD */ +#define _ETH_TXSTATUS_RETRYLMTEXCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_RETRYLMTEXCD_DEFAULT (_ETH_TXSTATUS_RETRYLMTEXCD_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_TXGO (0x1UL << 3) /**< Transmit go */ +#define _ETH_TXSTATUS_TXGO_SHIFT 3 /**< Shift value for ETH_TXGO */ +#define _ETH_TXSTATUS_TXGO_MASK 0x8UL /**< Bit mask for ETH_TXGO */ +#define _ETH_TXSTATUS_TXGO_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_TXGO_DEFAULT (_ETH_TXSTATUS_TXGO_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_AMBAERR (0x1UL << 4) /**< Transmit frame corruption due to AMBA (AHB) errors. */ +#define _ETH_TXSTATUS_AMBAERR_SHIFT 4 /**< Shift value for ETH_AMBAERR */ +#define _ETH_TXSTATUS_AMBAERR_MASK 0x10UL /**< Bit mask for ETH_AMBAERR */ +#define _ETH_TXSTATUS_AMBAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_AMBAERR_DEFAULT (_ETH_TXSTATUS_AMBAERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_TXCMPLT (0x1UL << 5) /**< Transmit complete */ +#define _ETH_TXSTATUS_TXCMPLT_SHIFT 5 /**< Shift value for ETH_TXCMPLT */ +#define _ETH_TXSTATUS_TXCMPLT_MASK 0x20UL /**< Bit mask for ETH_TXCMPLT */ +#define _ETH_TXSTATUS_TXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_TXCMPLT_DEFAULT (_ETH_TXSTATUS_TXCMPLT_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_TXUNDERRUN (0x1UL << 6) /**< Transmit under run */ +#define _ETH_TXSTATUS_TXUNDERRUN_SHIFT 6 /**< Shift value for ETH_TXUNDERRUN */ +#define _ETH_TXSTATUS_TXUNDERRUN_MASK 0x40UL /**< Bit mask for ETH_TXUNDERRUN */ +#define _ETH_TXSTATUS_TXUNDERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_TXUNDERRUN_DEFAULT (_ETH_TXSTATUS_TXUNDERRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_LATECOLOCCRD (0x1UL << 7) /**< Late collision occurred */ +#define _ETH_TXSTATUS_LATECOLOCCRD_SHIFT 7 /**< Shift value for ETH_LATECOLOCCRD */ +#define _ETH_TXSTATUS_LATECOLOCCRD_MASK 0x80UL /**< Bit mask for ETH_LATECOLOCCRD */ +#define _ETH_TXSTATUS_LATECOLOCCRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_LATECOLOCCRD_DEFAULT (_ETH_TXSTATUS_LATECOLOCCRD_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_RESPNOTOK (0x1UL << 8) /**< bresp/hresp not OK */ +#define _ETH_TXSTATUS_RESPNOTOK_SHIFT 8 /**< Shift value for ETH_RESPNOTOK */ +#define _ETH_TXSTATUS_RESPNOTOK_MASK 0x100UL /**< Bit mask for ETH_RESPNOTOK */ +#define _ETH_TXSTATUS_RESPNOTOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ +#define ETH_TXSTATUS_RESPNOTOK_DEFAULT (_ETH_TXSTATUS_RESPNOTOK_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ + +/* Bit fields for ETH RXQPTR */ +#define _ETH_RXQPTR_RESETVALUE 0x00000000UL /**< Default value for ETH_RXQPTR */ +#define _ETH_RXQPTR_MASK 0xFFFFFFFCUL /**< Mask for ETH_RXQPTR */ +#define _ETH_RXQPTR_DMARXQPTR_SHIFT 2 /**< Shift value for ETH_DMARXQPTR */ +#define _ETH_RXQPTR_DMARXQPTR_MASK 0xFFFFFFFCUL /**< Bit mask for ETH_DMARXQPTR */ +#define _ETH_RXQPTR_DMARXQPTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXQPTR */ +#define ETH_RXQPTR_DMARXQPTR_DEFAULT (_ETH_RXQPTR_DMARXQPTR_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_RXQPTR */ + +/* Bit fields for ETH TXQPTR */ +#define _ETH_TXQPTR_RESETVALUE 0x00000000UL /**< Default value for ETH_TXQPTR */ +#define _ETH_TXQPTR_MASK 0xFFFFFFFCUL /**< Mask for ETH_TXQPTR */ +#define _ETH_TXQPTR_DMATXQPTR_SHIFT 2 /**< Shift value for ETH_DMATXQPTR */ +#define _ETH_TXQPTR_DMATXQPTR_MASK 0xFFFFFFFCUL /**< Bit mask for ETH_DMATXQPTR */ +#define _ETH_TXQPTR_DMATXQPTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXQPTR */ +#define ETH_TXQPTR_DMATXQPTR_DEFAULT (_ETH_TXQPTR_DMATXQPTR_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_TXQPTR */ + +/* Bit fields for ETH RXSTATUS */ +#define _ETH_RXSTATUS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXSTATUS */ +#define _ETH_RXSTATUS_MASK 0x0000000FUL /**< Mask for ETH_RXSTATUS */ +#define ETH_RXSTATUS_BUFFNOTAVAIL (0x1UL << 0) /**< Buffer not available */ +#define _ETH_RXSTATUS_BUFFNOTAVAIL_SHIFT 0 /**< Shift value for ETH_BUFFNOTAVAIL */ +#define _ETH_RXSTATUS_BUFFNOTAVAIL_MASK 0x1UL /**< Bit mask for ETH_BUFFNOTAVAIL */ +#define _ETH_RXSTATUS_BUFFNOTAVAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXSTATUS */ +#define ETH_RXSTATUS_BUFFNOTAVAIL_DEFAULT (_ETH_RXSTATUS_BUFFNOTAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXSTATUS */ +#define ETH_RXSTATUS_FRMRX (0x1UL << 1) /**< Frame received */ +#define _ETH_RXSTATUS_FRMRX_SHIFT 1 /**< Shift value for ETH_FRMRX */ +#define _ETH_RXSTATUS_FRMRX_MASK 0x2UL /**< Bit mask for ETH_FRMRX */ +#define _ETH_RXSTATUS_FRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXSTATUS */ +#define ETH_RXSTATUS_FRMRX_DEFAULT (_ETH_RXSTATUS_FRMRX_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_RXSTATUS */ +#define ETH_RXSTATUS_RXOVERRUN (0x1UL << 2) /**< Receive overrun */ +#define _ETH_RXSTATUS_RXOVERRUN_SHIFT 2 /**< Shift value for ETH_RXOVERRUN */ +#define _ETH_RXSTATUS_RXOVERRUN_MASK 0x4UL /**< Bit mask for ETH_RXOVERRUN */ +#define _ETH_RXSTATUS_RXOVERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXSTATUS */ +#define ETH_RXSTATUS_RXOVERRUN_DEFAULT (_ETH_RXSTATUS_RXOVERRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_RXSTATUS */ +#define ETH_RXSTATUS_RESPNOTOK (0x1UL << 3) /**< bresp/hresp not OK */ +#define _ETH_RXSTATUS_RESPNOTOK_SHIFT 3 /**< Shift value for ETH_RESPNOTOK */ +#define _ETH_RXSTATUS_RESPNOTOK_MASK 0x8UL /**< Bit mask for ETH_RESPNOTOK */ +#define _ETH_RXSTATUS_RESPNOTOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXSTATUS */ +#define ETH_RXSTATUS_RESPNOTOK_DEFAULT (_ETH_RXSTATUS_RESPNOTOK_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_RXSTATUS */ + +/* Bit fields for ETH IFCR */ +#define _ETH_IFCR_RESETVALUE 0x00000000UL /**< Default value for ETH_IFCR */ +#define _ETH_IFCR_MASK 0x3FFC7CFFUL /**< Mask for ETH_IFCR */ +#define ETH_IFCR_MNGMNTDONE (0x1UL << 0) /**< Management frame sent */ +#define _ETH_IFCR_MNGMNTDONE_SHIFT 0 /**< Shift value for ETH_MNGMNTDONE */ +#define _ETH_IFCR_MNGMNTDONE_MASK 0x1UL /**< Bit mask for ETH_MNGMNTDONE */ +#define _ETH_IFCR_MNGMNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_MNGMNTDONE_DEFAULT (_ETH_IFCR_MNGMNTDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RXCMPLT (0x1UL << 1) /**< Receive complete */ +#define _ETH_IFCR_RXCMPLT_SHIFT 1 /**< Shift value for ETH_RXCMPLT */ +#define _ETH_IFCR_RXCMPLT_MASK 0x2UL /**< Bit mask for ETH_RXCMPLT */ +#define _ETH_IFCR_RXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RXCMPLT_DEFAULT (_ETH_IFCR_RXCMPLT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RXUSEDBITREAD (0x1UL << 2) /**< RX used bit read */ +#define _ETH_IFCR_RXUSEDBITREAD_SHIFT 2 /**< Shift value for ETH_RXUSEDBITREAD */ +#define _ETH_IFCR_RXUSEDBITREAD_MASK 0x4UL /**< Bit mask for ETH_RXUSEDBITREAD */ +#define _ETH_IFCR_RXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RXUSEDBITREAD_DEFAULT (_ETH_IFCR_RXUSEDBITREAD_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_TXUSEDBITREAD (0x1UL << 3) /**< TX used bit read */ +#define _ETH_IFCR_TXUSEDBITREAD_SHIFT 3 /**< Shift value for ETH_TXUSEDBITREAD */ +#define _ETH_IFCR_TXUSEDBITREAD_MASK 0x8UL /**< Bit mask for ETH_TXUSEDBITREAD */ +#define _ETH_IFCR_TXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_TXUSEDBITREAD_DEFAULT (_ETH_IFCR_TXUSEDBITREAD_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_TXUNDERRUN (0x1UL << 4) /**< Transmit under run */ +#define _ETH_IFCR_TXUNDERRUN_SHIFT 4 /**< Shift value for ETH_TXUNDERRUN */ +#define _ETH_IFCR_TXUNDERRUN_MASK 0x10UL /**< Bit mask for ETH_TXUNDERRUN */ +#define _ETH_IFCR_TXUNDERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_TXUNDERRUN_DEFAULT (_ETH_IFCR_TXUNDERRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RTRYLMTORLATECOL (0x1UL << 5) /**< Retry limit exceeded or late collision */ +#define _ETH_IFCR_RTRYLMTORLATECOL_SHIFT 5 /**< Shift value for ETH_RTRYLMTORLATECOL */ +#define _ETH_IFCR_RTRYLMTORLATECOL_MASK 0x20UL /**< Bit mask for ETH_RTRYLMTORLATECOL */ +#define _ETH_IFCR_RTRYLMTORLATECOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RTRYLMTORLATECOL_DEFAULT (_ETH_IFCR_RTRYLMTORLATECOL_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_AMBAERR (0x1UL << 6) /**< Transmit frame corruption due to AMBA (AHB) error. */ +#define _ETH_IFCR_AMBAERR_SHIFT 6 /**< Shift value for ETH_AMBAERR */ +#define _ETH_IFCR_AMBAERR_MASK 0x40UL /**< Bit mask for ETH_AMBAERR */ +#define _ETH_IFCR_AMBAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_AMBAERR_DEFAULT (_ETH_IFCR_AMBAERR_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_TXCMPLT (0x1UL << 7) /**< Transmit complete */ +#define _ETH_IFCR_TXCMPLT_SHIFT 7 /**< Shift value for ETH_TXCMPLT */ +#define _ETH_IFCR_TXCMPLT_MASK 0x80UL /**< Bit mask for ETH_TXCMPLT */ +#define _ETH_IFCR_TXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_TXCMPLT_DEFAULT (_ETH_IFCR_TXCMPLT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RXOVERRUN (0x1UL << 10) /**< Receive overrun */ +#define _ETH_IFCR_RXOVERRUN_SHIFT 10 /**< Shift value for ETH_RXOVERRUN */ +#define _ETH_IFCR_RXOVERRUN_MASK 0x400UL /**< Bit mask for ETH_RXOVERRUN */ +#define _ETH_IFCR_RXOVERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RXOVERRUN_DEFAULT (_ETH_IFCR_RXOVERRUN_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RESPNOTOK (0x1UL << 11) /**< Hresp not OK */ +#define _ETH_IFCR_RESPNOTOK_SHIFT 11 /**< Shift value for ETH_RESPNOTOK */ +#define _ETH_IFCR_RESPNOTOK_MASK 0x800UL /**< Bit mask for ETH_RESPNOTOK */ +#define _ETH_IFCR_RESPNOTOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RESPNOTOK_DEFAULT (_ETH_IFCR_RESPNOTOK_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_NONZEROPFRMQUANT (0x1UL << 12) /**< Pause frame with non-zero pause quantum received */ +#define _ETH_IFCR_NONZEROPFRMQUANT_SHIFT 12 /**< Shift value for ETH_NONZEROPFRMQUANT */ +#define _ETH_IFCR_NONZEROPFRMQUANT_MASK 0x1000UL /**< Bit mask for ETH_NONZEROPFRMQUANT */ +#define _ETH_IFCR_NONZEROPFRMQUANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_NONZEROPFRMQUANT_DEFAULT (_ETH_IFCR_NONZEROPFRMQUANT_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PAUSETIMEZERO (0x1UL << 13) /**< Pause Time zero */ +#define _ETH_IFCR_PAUSETIMEZERO_SHIFT 13 /**< Shift value for ETH_PAUSETIMEZERO */ +#define _ETH_IFCR_PAUSETIMEZERO_MASK 0x2000UL /**< Bit mask for ETH_PAUSETIMEZERO */ +#define _ETH_IFCR_PAUSETIMEZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PAUSETIMEZERO_DEFAULT (_ETH_IFCR_PAUSETIMEZERO_DEFAULT << 13) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PFRMTX (0x1UL << 14) /**< Pause frame transmitted */ +#define _ETH_IFCR_PFRMTX_SHIFT 14 /**< Shift value for ETH_PFRMTX */ +#define _ETH_IFCR_PFRMTX_MASK 0x4000UL /**< Bit mask for ETH_PFRMTX */ +#define _ETH_IFCR_PFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PFRMTX_DEFAULT (_ETH_IFCR_PFRMTX_DEFAULT << 14) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPDLYREQFRMRX (0x1UL << 18) /**< PTP delay_req frame received */ +#define _ETH_IFCR_PTPDLYREQFRMRX_SHIFT 18 /**< Shift value for ETH_PTPDLYREQFRMRX */ +#define _ETH_IFCR_PTPDLYREQFRMRX_MASK 0x40000UL /**< Bit mask for ETH_PTPDLYREQFRMRX */ +#define _ETH_IFCR_PTPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPDLYREQFRMRX_DEFAULT (_ETH_IFCR_PTPDLYREQFRMRX_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPSYNCFRMRX (0x1UL << 19) /**< PTP sync frame received */ +#define _ETH_IFCR_PTPSYNCFRMRX_SHIFT 19 /**< Shift value for ETH_PTPSYNCFRMRX */ +#define _ETH_IFCR_PTPSYNCFRMRX_MASK 0x80000UL /**< Bit mask for ETH_PTPSYNCFRMRX */ +#define _ETH_IFCR_PTPSYNCFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPSYNCFRMRX_DEFAULT (_ETH_IFCR_PTPSYNCFRMRX_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPDLYREQFRMTX (0x1UL << 20) /**< PTP delay_req frame transmitted */ +#define _ETH_IFCR_PTPDLYREQFRMTX_SHIFT 20 /**< Shift value for ETH_PTPDLYREQFRMTX */ +#define _ETH_IFCR_PTPDLYREQFRMTX_MASK 0x100000UL /**< Bit mask for ETH_PTPDLYREQFRMTX */ +#define _ETH_IFCR_PTPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPDLYREQFRMTX_DEFAULT (_ETH_IFCR_PTPDLYREQFRMTX_DEFAULT << 20) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPSYNCFRMTX (0x1UL << 21) /**< PTP sync frame transmitted */ +#define _ETH_IFCR_PTPSYNCFRMTX_SHIFT 21 /**< Shift value for ETH_PTPSYNCFRMTX */ +#define _ETH_IFCR_PTPSYNCFRMTX_MASK 0x200000UL /**< Bit mask for ETH_PTPSYNCFRMTX */ +#define _ETH_IFCR_PTPSYNCFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPSYNCFRMTX_DEFAULT (_ETH_IFCR_PTPSYNCFRMTX_DEFAULT << 21) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPPDLYREQFRMRX (0x1UL << 22) /**< PTP pdelay_req frame received */ +#define _ETH_IFCR_PTPPDLYREQFRMRX_SHIFT 22 /**< Shift value for ETH_PTPPDLYREQFRMRX */ +#define _ETH_IFCR_PTPPDLYREQFRMRX_MASK 0x400000UL /**< Bit mask for ETH_PTPPDLYREQFRMRX */ +#define _ETH_IFCR_PTPPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPPDLYREQFRMRX_DEFAULT (_ETH_IFCR_PTPPDLYREQFRMRX_DEFAULT << 22) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPPDLYRESPFRMRX (0x1UL << 23) /**< PTP pdelay_resp frame received */ +#define _ETH_IFCR_PTPPDLYRESPFRMRX_SHIFT 23 /**< Shift value for ETH_PTPPDLYRESPFRMRX */ +#define _ETH_IFCR_PTPPDLYRESPFRMRX_MASK 0x800000UL /**< Bit mask for ETH_PTPPDLYRESPFRMRX */ +#define _ETH_IFCR_PTPPDLYRESPFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPPDLYRESPFRMRX_DEFAULT (_ETH_IFCR_PTPPDLYRESPFRMRX_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPPDLYREQFRMTX (0x1UL << 24) /**< PTP pdelay_req frame transmitted */ +#define _ETH_IFCR_PTPPDLYREQFRMTX_SHIFT 24 /**< Shift value for ETH_PTPPDLYREQFRMTX */ +#define _ETH_IFCR_PTPPDLYREQFRMTX_MASK 0x1000000UL /**< Bit mask for ETH_PTPPDLYREQFRMTX */ +#define _ETH_IFCR_PTPPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPPDLYREQFRMTX_DEFAULT (_ETH_IFCR_PTPPDLYREQFRMTX_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPPDLYRESPFRMTX (0x1UL << 25) /**< PTP pdelay_resp frame transmitted */ +#define _ETH_IFCR_PTPPDLYRESPFRMTX_SHIFT 25 /**< Shift value for ETH_PTPPDLYRESPFRMTX */ +#define _ETH_IFCR_PTPPDLYRESPFRMTX_MASK 0x2000000UL /**< Bit mask for ETH_PTPPDLYRESPFRMTX */ +#define _ETH_IFCR_PTPPDLYRESPFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_PTPPDLYRESPFRMTX_DEFAULT (_ETH_IFCR_PTPPDLYRESPFRMTX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_TSUSECREGINCR (0x1UL << 26) /**< TSU seconds register increment */ +#define _ETH_IFCR_TSUSECREGINCR_SHIFT 26 /**< Shift value for ETH_TSUSECREGINCR */ +#define _ETH_IFCR_TSUSECREGINCR_MASK 0x4000000UL /**< Bit mask for ETH_TSUSECREGINCR */ +#define _ETH_IFCR_TSUSECREGINCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_TSUSECREGINCR_DEFAULT (_ETH_IFCR_TSUSECREGINCR_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RXLPIINDC (0x1UL << 27) /**< Receive LPI indication status bit change */ +#define _ETH_IFCR_RXLPIINDC_SHIFT 27 /**< Shift value for ETH_RXLPIINDC */ +#define _ETH_IFCR_RXLPIINDC_MASK 0x8000000UL /**< Bit mask for ETH_RXLPIINDC */ +#define _ETH_IFCR_RXLPIINDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_RXLPIINDC_DEFAULT (_ETH_IFCR_RXLPIINDC_DEFAULT << 27) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_WOLEVNTRX (0x1UL << 28) /**< WOL event received interrupt. */ +#define _ETH_IFCR_WOLEVNTRX_SHIFT 28 /**< Shift value for ETH_WOLEVNTRX */ +#define _ETH_IFCR_WOLEVNTRX_MASK 0x10000000UL /**< Bit mask for ETH_WOLEVNTRX */ +#define _ETH_IFCR_WOLEVNTRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_WOLEVNTRX_DEFAULT (_ETH_IFCR_WOLEVNTRX_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_TSUTIMERCOMP (0x1UL << 29) /**< TSU timer comparison interrupt. */ +#define _ETH_IFCR_TSUTIMERCOMP_SHIFT 29 /**< Shift value for ETH_TSUTIMERCOMP */ +#define _ETH_IFCR_TSUTIMERCOMP_MASK 0x20000000UL /**< Bit mask for ETH_TSUTIMERCOMP */ +#define _ETH_IFCR_TSUTIMERCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ +#define ETH_IFCR_TSUTIMERCOMP_DEFAULT (_ETH_IFCR_TSUTIMERCOMP_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_IFCR */ + +/* Bit fields for ETH IENS */ +#define _ETH_IENS_RESETVALUE 0x00000000UL /**< Default value for ETH_IENS */ +#define _ETH_IENS_MASK 0x3FFC7CFFUL /**< Mask for ETH_IENS */ +#define ETH_IENS_MNGMNTDONE (0x1UL << 0) /**< Enable management done interrupt */ +#define _ETH_IENS_MNGMNTDONE_SHIFT 0 /**< Shift value for ETH_MNGMNTDONE */ +#define _ETH_IENS_MNGMNTDONE_MASK 0x1UL /**< Bit mask for ETH_MNGMNTDONE */ +#define _ETH_IENS_MNGMNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_MNGMNTDONE_DEFAULT (_ETH_IENS_MNGMNTDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RXCMPLT (0x1UL << 1) /**< Enable receive complete interrupt */ +#define _ETH_IENS_RXCMPLT_SHIFT 1 /**< Shift value for ETH_RXCMPLT */ +#define _ETH_IENS_RXCMPLT_MASK 0x2UL /**< Bit mask for ETH_RXCMPLT */ +#define _ETH_IENS_RXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RXCMPLT_DEFAULT (_ETH_IENS_RXCMPLT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RXUSEDBITREAD (0x1UL << 2) /**< Enable receive used bit read interrupt */ +#define _ETH_IENS_RXUSEDBITREAD_SHIFT 2 /**< Shift value for ETH_RXUSEDBITREAD */ +#define _ETH_IENS_RXUSEDBITREAD_MASK 0x4UL /**< Bit mask for ETH_RXUSEDBITREAD */ +#define _ETH_IENS_RXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RXUSEDBITREAD_DEFAULT (_ETH_IENS_RXUSEDBITREAD_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_TXUSEDBITREAD (0x1UL << 3) /**< Enable transmit used bit read interrupt */ +#define _ETH_IENS_TXUSEDBITREAD_SHIFT 3 /**< Shift value for ETH_TXUSEDBITREAD */ +#define _ETH_IENS_TXUSEDBITREAD_MASK 0x8UL /**< Bit mask for ETH_TXUSEDBITREAD */ +#define _ETH_IENS_TXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_TXUSEDBITREAD_DEFAULT (_ETH_IENS_TXUSEDBITREAD_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_TXUNDERRUN (0x1UL << 4) /**< Enable transmit buffer under run interrupt */ +#define _ETH_IENS_TXUNDERRUN_SHIFT 4 /**< Shift value for ETH_TXUNDERRUN */ +#define _ETH_IENS_TXUNDERRUN_MASK 0x10UL /**< Bit mask for ETH_TXUNDERRUN */ +#define _ETH_IENS_TXUNDERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_TXUNDERRUN_DEFAULT (_ETH_IENS_TXUNDERRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RTRYLMTORLATECOL (0x1UL << 5) /**< Enable retry limit exceeded or late collision interrupt */ +#define _ETH_IENS_RTRYLMTORLATECOL_SHIFT 5 /**< Shift value for ETH_RTRYLMTORLATECOL */ +#define _ETH_IENS_RTRYLMTORLATECOL_MASK 0x20UL /**< Bit mask for ETH_RTRYLMTORLATECOL */ +#define _ETH_IENS_RTRYLMTORLATECOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RTRYLMTORLATECOL_DEFAULT (_ETH_IENS_RTRYLMTORLATECOL_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_AMBAERR (0x1UL << 6) /**< Enable transmit frame corruption due to AMBA (AHB) error interrupt */ +#define _ETH_IENS_AMBAERR_SHIFT 6 /**< Shift value for ETH_AMBAERR */ +#define _ETH_IENS_AMBAERR_MASK 0x40UL /**< Bit mask for ETH_AMBAERR */ +#define _ETH_IENS_AMBAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_AMBAERR_DEFAULT (_ETH_IENS_AMBAERR_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_TXCMPLT (0x1UL << 7) /**< Enable transmit complete interrupt */ +#define _ETH_IENS_TXCMPLT_SHIFT 7 /**< Shift value for ETH_TXCMPLT */ +#define _ETH_IENS_TXCMPLT_MASK 0x80UL /**< Bit mask for ETH_TXCMPLT */ +#define _ETH_IENS_TXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_TXCMPLT_DEFAULT (_ETH_IENS_TXCMPLT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RXOVERRUN (0x1UL << 10) /**< Enable receive overrun interrupt */ +#define _ETH_IENS_RXOVERRUN_SHIFT 10 /**< Shift value for ETH_RXOVERRUN */ +#define _ETH_IENS_RXOVERRUN_MASK 0x400UL /**< Bit mask for ETH_RXOVERRUN */ +#define _ETH_IENS_RXOVERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RXOVERRUN_DEFAULT (_ETH_IENS_RXOVERRUN_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RESPNOTOK (0x1UL << 11) /**< Enable bresp/hresp not OK interrupt */ +#define _ETH_IENS_RESPNOTOK_SHIFT 11 /**< Shift value for ETH_RESPNOTOK */ +#define _ETH_IENS_RESPNOTOK_MASK 0x800UL /**< Bit mask for ETH_RESPNOTOK */ +#define _ETH_IENS_RESPNOTOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RESPNOTOK_DEFAULT (_ETH_IENS_RESPNOTOK_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_NONZEROPFRMQUANT (0x1UL << 12) /**< Enable pause frame with non-zero pause quantum interrupt */ +#define _ETH_IENS_NONZEROPFRMQUANT_SHIFT 12 /**< Shift value for ETH_NONZEROPFRMQUANT */ +#define _ETH_IENS_NONZEROPFRMQUANT_MASK 0x1000UL /**< Bit mask for ETH_NONZEROPFRMQUANT */ +#define _ETH_IENS_NONZEROPFRMQUANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_NONZEROPFRMQUANT_DEFAULT (_ETH_IENS_NONZEROPFRMQUANT_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PAUSETIMEZERO (0x1UL << 13) /**< Enable pause time zero interrupt */ +#define _ETH_IENS_PAUSETIMEZERO_SHIFT 13 /**< Shift value for ETH_PAUSETIMEZERO */ +#define _ETH_IENS_PAUSETIMEZERO_MASK 0x2000UL /**< Bit mask for ETH_PAUSETIMEZERO */ +#define _ETH_IENS_PAUSETIMEZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PAUSETIMEZERO_DEFAULT (_ETH_IENS_PAUSETIMEZERO_DEFAULT << 13) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PFRMTX (0x1UL << 14) /**< Enable pause frame transmitted interrupt */ +#define _ETH_IENS_PFRMTX_SHIFT 14 /**< Shift value for ETH_PFRMTX */ +#define _ETH_IENS_PFRMTX_MASK 0x4000UL /**< Bit mask for ETH_PFRMTX */ +#define _ETH_IENS_PFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PFRMTX_DEFAULT (_ETH_IENS_PFRMTX_DEFAULT << 14) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPDLYREQFRMRX (0x1UL << 18) /**< Enable PTP delay_req frame received interrupt */ +#define _ETH_IENS_PTPDLYREQFRMRX_SHIFT 18 /**< Shift value for ETH_PTPDLYREQFRMRX */ +#define _ETH_IENS_PTPDLYREQFRMRX_MASK 0x40000UL /**< Bit mask for ETH_PTPDLYREQFRMRX */ +#define _ETH_IENS_PTPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPDLYREQFRMRX_DEFAULT (_ETH_IENS_PTPDLYREQFRMRX_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPSYNCFRMRX (0x1UL << 19) /**< Enable PTP sync frame received interrupt */ +#define _ETH_IENS_PTPSYNCFRMRX_SHIFT 19 /**< Shift value for ETH_PTPSYNCFRMRX */ +#define _ETH_IENS_PTPSYNCFRMRX_MASK 0x80000UL /**< Bit mask for ETH_PTPSYNCFRMRX */ +#define _ETH_IENS_PTPSYNCFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPSYNCFRMRX_DEFAULT (_ETH_IENS_PTPSYNCFRMRX_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPDLYREQFRMTX (0x1UL << 20) /**< Enable PTP delay_req frame transmitted interrupt */ +#define _ETH_IENS_PTPDLYREQFRMTX_SHIFT 20 /**< Shift value for ETH_PTPDLYREQFRMTX */ +#define _ETH_IENS_PTPDLYREQFRMTX_MASK 0x100000UL /**< Bit mask for ETH_PTPDLYREQFRMTX */ +#define _ETH_IENS_PTPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPDLYREQFRMTX_DEFAULT (_ETH_IENS_PTPDLYREQFRMTX_DEFAULT << 20) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPSYNCFRMTX (0x1UL << 21) /**< Enable PTP sync frame transmitted interrupt */ +#define _ETH_IENS_PTPSYNCFRMTX_SHIFT 21 /**< Shift value for ETH_PTPSYNCFRMTX */ +#define _ETH_IENS_PTPSYNCFRMTX_MASK 0x200000UL /**< Bit mask for ETH_PTPSYNCFRMTX */ +#define _ETH_IENS_PTPSYNCFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPSYNCFRMTX_DEFAULT (_ETH_IENS_PTPSYNCFRMTX_DEFAULT << 21) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPPDLYREQFRMRX (0x1UL << 22) /**< Enable PTP pdelay_req frame received interrupt */ +#define _ETH_IENS_PTPPDLYREQFRMRX_SHIFT 22 /**< Shift value for ETH_PTPPDLYREQFRMRX */ +#define _ETH_IENS_PTPPDLYREQFRMRX_MASK 0x400000UL /**< Bit mask for ETH_PTPPDLYREQFRMRX */ +#define _ETH_IENS_PTPPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPPDLYREQFRMRX_DEFAULT (_ETH_IENS_PTPPDLYREQFRMRX_DEFAULT << 22) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPPDLYRESPFRMRX (0x1UL << 23) /**< Enable PTP pdelay_resp frame received interrupt */ +#define _ETH_IENS_PTPPDLYRESPFRMRX_SHIFT 23 /**< Shift value for ETH_PTPPDLYRESPFRMRX */ +#define _ETH_IENS_PTPPDLYRESPFRMRX_MASK 0x800000UL /**< Bit mask for ETH_PTPPDLYRESPFRMRX */ +#define _ETH_IENS_PTPPDLYRESPFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPPDLYRESPFRMRX_DEFAULT (_ETH_IENS_PTPPDLYRESPFRMRX_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPPDLYREQFRMTX (0x1UL << 24) /**< Enable PTP pdelay_req frame transmitted interrupt */ +#define _ETH_IENS_PTPPDLYREQFRMTX_SHIFT 24 /**< Shift value for ETH_PTPPDLYREQFRMTX */ +#define _ETH_IENS_PTPPDLYREQFRMTX_MASK 0x1000000UL /**< Bit mask for ETH_PTPPDLYREQFRMTX */ +#define _ETH_IENS_PTPPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPPDLYREQFRMTX_DEFAULT (_ETH_IENS_PTPPDLYREQFRMTX_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPPDLYRESPFRMTX (0x1UL << 25) /**< Enable PTP pdelay_resp frame transmitted interrupt */ +#define _ETH_IENS_PTPPDLYRESPFRMTX_SHIFT 25 /**< Shift value for ETH_PTPPDLYRESPFRMTX */ +#define _ETH_IENS_PTPPDLYRESPFRMTX_MASK 0x2000000UL /**< Bit mask for ETH_PTPPDLYRESPFRMTX */ +#define _ETH_IENS_PTPPDLYRESPFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_PTPPDLYRESPFRMTX_DEFAULT (_ETH_IENS_PTPPDLYRESPFRMTX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_TSUSECREGINCR (0x1UL << 26) /**< Enable TSU seconds register increment interrupt */ +#define _ETH_IENS_TSUSECREGINCR_SHIFT 26 /**< Shift value for ETH_TSUSECREGINCR */ +#define _ETH_IENS_TSUSECREGINCR_MASK 0x4000000UL /**< Bit mask for ETH_TSUSECREGINCR */ +#define _ETH_IENS_TSUSECREGINCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_TSUSECREGINCR_DEFAULT (_ETH_IENS_TSUSECREGINCR_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RXLPIINDC (0x1UL << 27) /**< Enable RX LPI indication interrupt */ +#define _ETH_IENS_RXLPIINDC_SHIFT 27 /**< Shift value for ETH_RXLPIINDC */ +#define _ETH_IENS_RXLPIINDC_MASK 0x8000000UL /**< Bit mask for ETH_RXLPIINDC */ +#define _ETH_IENS_RXLPIINDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_RXLPIINDC_DEFAULT (_ETH_IENS_RXLPIINDC_DEFAULT << 27) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_WOLEVNTRX (0x1UL << 28) /**< Enable WOL event received interrupt */ +#define _ETH_IENS_WOLEVNTRX_SHIFT 28 /**< Shift value for ETH_WOLEVNTRX */ +#define _ETH_IENS_WOLEVNTRX_MASK 0x10000000UL /**< Bit mask for ETH_WOLEVNTRX */ +#define _ETH_IENS_WOLEVNTRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_WOLEVNTRX_DEFAULT (_ETH_IENS_WOLEVNTRX_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_IENS */ +#define ETH_IENS_TSUTIMERCOMP (0x1UL << 29) /**< Enable TSU timer comparison interrupt. */ +#define _ETH_IENS_TSUTIMERCOMP_SHIFT 29 /**< Shift value for ETH_TSUTIMERCOMP */ +#define _ETH_IENS_TSUTIMERCOMP_MASK 0x20000000UL /**< Bit mask for ETH_TSUTIMERCOMP */ +#define _ETH_IENS_TSUTIMERCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ +#define ETH_IENS_TSUTIMERCOMP_DEFAULT (_ETH_IENS_TSUTIMERCOMP_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_IENS */ + +/* Bit fields for ETH IENC */ +#define _ETH_IENC_RESETVALUE 0x00000000UL /**< Default value for ETH_IENC */ +#define _ETH_IENC_MASK 0x3FFC7CFFUL /**< Mask for ETH_IENC */ +#define ETH_IENC_MNGMNTDONE (0x1UL << 0) /**< Disable management done interrupt */ +#define _ETH_IENC_MNGMNTDONE_SHIFT 0 /**< Shift value for ETH_MNGMNTDONE */ +#define _ETH_IENC_MNGMNTDONE_MASK 0x1UL /**< Bit mask for ETH_MNGMNTDONE */ +#define _ETH_IENC_MNGMNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_MNGMNTDONE_DEFAULT (_ETH_IENC_MNGMNTDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RXCMPLT (0x1UL << 1) /**< Disable receive complete interrupt */ +#define _ETH_IENC_RXCMPLT_SHIFT 1 /**< Shift value for ETH_RXCMPLT */ +#define _ETH_IENC_RXCMPLT_MASK 0x2UL /**< Bit mask for ETH_RXCMPLT */ +#define _ETH_IENC_RXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RXCMPLT_DEFAULT (_ETH_IENC_RXCMPLT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RXUSEDBITREAD (0x1UL << 2) /**< Disable receive used bit read interrupt */ +#define _ETH_IENC_RXUSEDBITREAD_SHIFT 2 /**< Shift value for ETH_RXUSEDBITREAD */ +#define _ETH_IENC_RXUSEDBITREAD_MASK 0x4UL /**< Bit mask for ETH_RXUSEDBITREAD */ +#define _ETH_IENC_RXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RXUSEDBITREAD_DEFAULT (_ETH_IENC_RXUSEDBITREAD_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_TXUSEDBITREAD (0x1UL << 3) /**< Disable transmit used bit read interrupt */ +#define _ETH_IENC_TXUSEDBITREAD_SHIFT 3 /**< Shift value for ETH_TXUSEDBITREAD */ +#define _ETH_IENC_TXUSEDBITREAD_MASK 0x8UL /**< Bit mask for ETH_TXUSEDBITREAD */ +#define _ETH_IENC_TXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_TXUSEDBITREAD_DEFAULT (_ETH_IENC_TXUSEDBITREAD_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_TXUNDERRUN (0x1UL << 4) /**< Disable transmit buffer under run interrupt */ +#define _ETH_IENC_TXUNDERRUN_SHIFT 4 /**< Shift value for ETH_TXUNDERRUN */ +#define _ETH_IENC_TXUNDERRUN_MASK 0x10UL /**< Bit mask for ETH_TXUNDERRUN */ +#define _ETH_IENC_TXUNDERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_TXUNDERRUN_DEFAULT (_ETH_IENC_TXUNDERRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RTRYLMTORLATECOL (0x1UL << 5) /**< Disable retry limit exceeded or late collision interrupt */ +#define _ETH_IENC_RTRYLMTORLATECOL_SHIFT 5 /**< Shift value for ETH_RTRYLMTORLATECOL */ +#define _ETH_IENC_RTRYLMTORLATECOL_MASK 0x20UL /**< Bit mask for ETH_RTRYLMTORLATECOL */ +#define _ETH_IENC_RTRYLMTORLATECOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RTRYLMTORLATECOL_DEFAULT (_ETH_IENC_RTRYLMTORLATECOL_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_AMBAERR (0x1UL << 6) /**< Disable transmit frame corruption due to AMBA (AHB) error interrupt */ +#define _ETH_IENC_AMBAERR_SHIFT 6 /**< Shift value for ETH_AMBAERR */ +#define _ETH_IENC_AMBAERR_MASK 0x40UL /**< Bit mask for ETH_AMBAERR */ +#define _ETH_IENC_AMBAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_AMBAERR_DEFAULT (_ETH_IENC_AMBAERR_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_TXCMPLT (0x1UL << 7) /**< Disable transmit complete interrupt */ +#define _ETH_IENC_TXCMPLT_SHIFT 7 /**< Shift value for ETH_TXCMPLT */ +#define _ETH_IENC_TXCMPLT_MASK 0x80UL /**< Bit mask for ETH_TXCMPLT */ +#define _ETH_IENC_TXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_TXCMPLT_DEFAULT (_ETH_IENC_TXCMPLT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RXOVERRUN (0x1UL << 10) /**< Disable receive overrun interrupt */ +#define _ETH_IENC_RXOVERRUN_SHIFT 10 /**< Shift value for ETH_RXOVERRUN */ +#define _ETH_IENC_RXOVERRUN_MASK 0x400UL /**< Bit mask for ETH_RXOVERRUN */ +#define _ETH_IENC_RXOVERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RXOVERRUN_DEFAULT (_ETH_IENC_RXOVERRUN_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RESPNOTOK (0x1UL << 11) /**< Disable bresp/hresp not OK interrupt */ +#define _ETH_IENC_RESPNOTOK_SHIFT 11 /**< Shift value for ETH_RESPNOTOK */ +#define _ETH_IENC_RESPNOTOK_MASK 0x800UL /**< Bit mask for ETH_RESPNOTOK */ +#define _ETH_IENC_RESPNOTOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RESPNOTOK_DEFAULT (_ETH_IENC_RESPNOTOK_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_NONZEROPFRMQUANT (0x1UL << 12) /**< Disable pause frame with non-zero pause quantum interrupt */ +#define _ETH_IENC_NONZEROPFRMQUANT_SHIFT 12 /**< Shift value for ETH_NONZEROPFRMQUANT */ +#define _ETH_IENC_NONZEROPFRMQUANT_MASK 0x1000UL /**< Bit mask for ETH_NONZEROPFRMQUANT */ +#define _ETH_IENC_NONZEROPFRMQUANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_NONZEROPFRMQUANT_DEFAULT (_ETH_IENC_NONZEROPFRMQUANT_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PAUSETIMEZERO (0x1UL << 13) /**< Disable pause time zero interrupt */ +#define _ETH_IENC_PAUSETIMEZERO_SHIFT 13 /**< Shift value for ETH_PAUSETIMEZERO */ +#define _ETH_IENC_PAUSETIMEZERO_MASK 0x2000UL /**< Bit mask for ETH_PAUSETIMEZERO */ +#define _ETH_IENC_PAUSETIMEZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PAUSETIMEZERO_DEFAULT (_ETH_IENC_PAUSETIMEZERO_DEFAULT << 13) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PFRMTX (0x1UL << 14) /**< Disable pause frame transmitted interrupt */ +#define _ETH_IENC_PFRMTX_SHIFT 14 /**< Shift value for ETH_PFRMTX */ +#define _ETH_IENC_PFRMTX_MASK 0x4000UL /**< Bit mask for ETH_PFRMTX */ +#define _ETH_IENC_PFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PFRMTX_DEFAULT (_ETH_IENC_PFRMTX_DEFAULT << 14) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPDLYREQFRMRX (0x1UL << 18) /**< Disable PTP delay_req frame received interrupt */ +#define _ETH_IENC_PTPDLYREQFRMRX_SHIFT 18 /**< Shift value for ETH_PTPDLYREQFRMRX */ +#define _ETH_IENC_PTPDLYREQFRMRX_MASK 0x40000UL /**< Bit mask for ETH_PTPDLYREQFRMRX */ +#define _ETH_IENC_PTPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPDLYREQFRMRX_DEFAULT (_ETH_IENC_PTPDLYREQFRMRX_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPSYNCFRMRX (0x1UL << 19) /**< Disable PTP sync frame received interrupt */ +#define _ETH_IENC_PTPSYNCFRMRX_SHIFT 19 /**< Shift value for ETH_PTPSYNCFRMRX */ +#define _ETH_IENC_PTPSYNCFRMRX_MASK 0x80000UL /**< Bit mask for ETH_PTPSYNCFRMRX */ +#define _ETH_IENC_PTPSYNCFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPSYNCFRMRX_DEFAULT (_ETH_IENC_PTPSYNCFRMRX_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPDLYREQFRMTX (0x1UL << 20) /**< Disable PTP delay_req frame transmitted interrupt */ +#define _ETH_IENC_PTPDLYREQFRMTX_SHIFT 20 /**< Shift value for ETH_PTPDLYREQFRMTX */ +#define _ETH_IENC_PTPDLYREQFRMTX_MASK 0x100000UL /**< Bit mask for ETH_PTPDLYREQFRMTX */ +#define _ETH_IENC_PTPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPDLYREQFRMTX_DEFAULT (_ETH_IENC_PTPDLYREQFRMTX_DEFAULT << 20) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPSYNCFRMTX (0x1UL << 21) /**< Disable PTP sync frame transmitted interrupt */ +#define _ETH_IENC_PTPSYNCFRMTX_SHIFT 21 /**< Shift value for ETH_PTPSYNCFRMTX */ +#define _ETH_IENC_PTPSYNCFRMTX_MASK 0x200000UL /**< Bit mask for ETH_PTPSYNCFRMTX */ +#define _ETH_IENC_PTPSYNCFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPSYNCFRMTX_DEFAULT (_ETH_IENC_PTPSYNCFRMTX_DEFAULT << 21) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPPDLYREQFRMRX (0x1UL << 22) /**< Disable PTP pdelay_req frame received interrupt */ +#define _ETH_IENC_PTPPDLYREQFRMRX_SHIFT 22 /**< Shift value for ETH_PTPPDLYREQFRMRX */ +#define _ETH_IENC_PTPPDLYREQFRMRX_MASK 0x400000UL /**< Bit mask for ETH_PTPPDLYREQFRMRX */ +#define _ETH_IENC_PTPPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPPDLYREQFRMRX_DEFAULT (_ETH_IENC_PTPPDLYREQFRMRX_DEFAULT << 22) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPPDLYRESPFRMRX (0x1UL << 23) /**< Disable PTP pdelay_resp frame received interrupt */ +#define _ETH_IENC_PTPPDLYRESPFRMRX_SHIFT 23 /**< Shift value for ETH_PTPPDLYRESPFRMRX */ +#define _ETH_IENC_PTPPDLYRESPFRMRX_MASK 0x800000UL /**< Bit mask for ETH_PTPPDLYRESPFRMRX */ +#define _ETH_IENC_PTPPDLYRESPFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPPDLYRESPFRMRX_DEFAULT (_ETH_IENC_PTPPDLYRESPFRMRX_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPPDLYREQFRMTX (0x1UL << 24) /**< Disable PTP pdelay_req frame transmitted interrupt */ +#define _ETH_IENC_PTPPDLYREQFRMTX_SHIFT 24 /**< Shift value for ETH_PTPPDLYREQFRMTX */ +#define _ETH_IENC_PTPPDLYREQFRMTX_MASK 0x1000000UL /**< Bit mask for ETH_PTPPDLYREQFRMTX */ +#define _ETH_IENC_PTPPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPPDLYREQFRMTX_DEFAULT (_ETH_IENC_PTPPDLYREQFRMTX_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPPDLYRESPFRMTX (0x1UL << 25) /**< Disable PTP pdelay_resp frame transmitted interrupt */ +#define _ETH_IENC_PTPPDLYRESPFRMTX_SHIFT 25 /**< Shift value for ETH_PTPPDLYRESPFRMTX */ +#define _ETH_IENC_PTPPDLYRESPFRMTX_MASK 0x2000000UL /**< Bit mask for ETH_PTPPDLYRESPFRMTX */ +#define _ETH_IENC_PTPPDLYRESPFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_PTPPDLYRESPFRMTX_DEFAULT (_ETH_IENC_PTPPDLYRESPFRMTX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_TSUSECREGINCR (0x1UL << 26) /**< Disable TSU seconds register increment interrupt */ +#define _ETH_IENC_TSUSECREGINCR_SHIFT 26 /**< Shift value for ETH_TSUSECREGINCR */ +#define _ETH_IENC_TSUSECREGINCR_MASK 0x4000000UL /**< Bit mask for ETH_TSUSECREGINCR */ +#define _ETH_IENC_TSUSECREGINCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_TSUSECREGINCR_DEFAULT (_ETH_IENC_TSUSECREGINCR_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RXLPIINDC (0x1UL << 27) /**< Disable RX LPI indication interrupt */ +#define _ETH_IENC_RXLPIINDC_SHIFT 27 /**< Shift value for ETH_RXLPIINDC */ +#define _ETH_IENC_RXLPIINDC_MASK 0x8000000UL /**< Bit mask for ETH_RXLPIINDC */ +#define _ETH_IENC_RXLPIINDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_RXLPIINDC_DEFAULT (_ETH_IENC_RXLPIINDC_DEFAULT << 27) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_WOLEVNTRX (0x1UL << 28) /**< Disable WOL event received interrupt */ +#define _ETH_IENC_WOLEVNTRX_SHIFT 28 /**< Shift value for ETH_WOLEVNTRX */ +#define _ETH_IENC_WOLEVNTRX_MASK 0x10000000UL /**< Bit mask for ETH_WOLEVNTRX */ +#define _ETH_IENC_WOLEVNTRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_WOLEVNTRX_DEFAULT (_ETH_IENC_WOLEVNTRX_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_IENC */ +#define ETH_IENC_TSUTIMERCOMP (0x1UL << 29) /**< Disable TSU timer comparison interrupt. */ +#define _ETH_IENC_TSUTIMERCOMP_SHIFT 29 /**< Shift value for ETH_TSUTIMERCOMP */ +#define _ETH_IENC_TSUTIMERCOMP_MASK 0x20000000UL /**< Bit mask for ETH_TSUTIMERCOMP */ +#define _ETH_IENC_TSUTIMERCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ +#define ETH_IENC_TSUTIMERCOMP_DEFAULT (_ETH_IENC_TSUTIMERCOMP_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_IENC */ + +/* Bit fields for ETH IENRO */ +#define _ETH_IENRO_RESETVALUE 0x3FFC7DFFUL /**< Default value for ETH_IENRO */ +#define _ETH_IENRO_MASK 0x3FFC7DFFUL /**< Mask for ETH_IENRO */ +#define ETH_IENRO_MNGMNTDONE (0x1UL << 0) /**< management done interrupt mask */ +#define _ETH_IENRO_MNGMNTDONE_SHIFT 0 /**< Shift value for ETH_MNGMNTDONE */ +#define _ETH_IENRO_MNGMNTDONE_MASK 0x1UL /**< Bit mask for ETH_MNGMNTDONE */ +#define _ETH_IENRO_MNGMNTDONE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_MNGMNTDONE_DEFAULT (_ETH_IENRO_MNGMNTDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RXCMPLT (0x1UL << 1) /**< receive complete interrupt mask */ +#define _ETH_IENRO_RXCMPLT_SHIFT 1 /**< Shift value for ETH_RXCMPLT */ +#define _ETH_IENRO_RXCMPLT_MASK 0x2UL /**< Bit mask for ETH_RXCMPLT */ +#define _ETH_IENRO_RXCMPLT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RXCMPLT_DEFAULT (_ETH_IENRO_RXCMPLT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RXUSEDBITREAD (0x1UL << 2) /**< receive used bit read interrupt mask */ +#define _ETH_IENRO_RXUSEDBITREAD_SHIFT 2 /**< Shift value for ETH_RXUSEDBITREAD */ +#define _ETH_IENRO_RXUSEDBITREAD_MASK 0x4UL /**< Bit mask for ETH_RXUSEDBITREAD */ +#define _ETH_IENRO_RXUSEDBITREAD_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RXUSEDBITREAD_DEFAULT (_ETH_IENRO_RXUSEDBITREAD_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_TXUSEDBITREAD (0x1UL << 3) /**< transmit used bit read interrupt mask */ +#define _ETH_IENRO_TXUSEDBITREAD_SHIFT 3 /**< Shift value for ETH_TXUSEDBITREAD */ +#define _ETH_IENRO_TXUSEDBITREAD_MASK 0x8UL /**< Bit mask for ETH_TXUSEDBITREAD */ +#define _ETH_IENRO_TXUSEDBITREAD_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_TXUSEDBITREAD_DEFAULT (_ETH_IENRO_TXUSEDBITREAD_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_TXUNDERRUN (0x1UL << 4) /**< transmit buffer under run interrupt mask */ +#define _ETH_IENRO_TXUNDERRUN_SHIFT 4 /**< Shift value for ETH_TXUNDERRUN */ +#define _ETH_IENRO_TXUNDERRUN_MASK 0x10UL /**< Bit mask for ETH_TXUNDERRUN */ +#define _ETH_IENRO_TXUNDERRUN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_TXUNDERRUN_DEFAULT (_ETH_IENRO_TXUNDERRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RTRYLMTORLATECOL (0x1UL << 5) /**< Retry limit exceeded or late collision (gigabit mode only) interrupt mask */ +#define _ETH_IENRO_RTRYLMTORLATECOL_SHIFT 5 /**< Shift value for ETH_RTRYLMTORLATECOL */ +#define _ETH_IENRO_RTRYLMTORLATECOL_MASK 0x20UL /**< Bit mask for ETH_RTRYLMTORLATECOL */ +#define _ETH_IENRO_RTRYLMTORLATECOL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RTRYLMTORLATECOL_DEFAULT (_ETH_IENRO_RTRYLMTORLATECOL_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_AMBAERR (0x1UL << 6) /**< Transmit frame corruption due to AMBA (AHB) error interrupt mask */ +#define _ETH_IENRO_AMBAERR_SHIFT 6 /**< Shift value for ETH_AMBAERR */ +#define _ETH_IENRO_AMBAERR_MASK 0x40UL /**< Bit mask for ETH_AMBAERR */ +#define _ETH_IENRO_AMBAERR_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_AMBAERR_DEFAULT (_ETH_IENRO_AMBAERR_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_TXCMPLT (0x1UL << 7) /**< Transmit complete interrupt mask */ +#define _ETH_IENRO_TXCMPLT_SHIFT 7 /**< Shift value for ETH_TXCMPLT */ +#define _ETH_IENRO_TXCMPLT_MASK 0x80UL /**< Bit mask for ETH_TXCMPLT */ +#define _ETH_IENRO_TXCMPLT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_TXCMPLT_DEFAULT (_ETH_IENRO_TXCMPLT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_UNUSED (0x1UL << 8) /**< Unused */ +#define _ETH_IENRO_UNUSED_SHIFT 8 /**< Shift value for ETH_UNUSED */ +#define _ETH_IENRO_UNUSED_MASK 0x100UL /**< Bit mask for ETH_UNUSED */ +#define _ETH_IENRO_UNUSED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_UNUSED_DEFAULT (_ETH_IENRO_UNUSED_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RXOVERRUN (0x1UL << 10) /**< Receive overrun interrupt mask */ +#define _ETH_IENRO_RXOVERRUN_SHIFT 10 /**< Shift value for ETH_RXOVERRUN */ +#define _ETH_IENRO_RXOVERRUN_MASK 0x400UL /**< Bit mask for ETH_RXOVERRUN */ +#define _ETH_IENRO_RXOVERRUN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RXOVERRUN_DEFAULT (_ETH_IENRO_RXOVERRUN_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RESPNOTOK (0x1UL << 11) /**< bresp/hresp not OK interrupt mask */ +#define _ETH_IENRO_RESPNOTOK_SHIFT 11 /**< Shift value for ETH_RESPNOTOK */ +#define _ETH_IENRO_RESPNOTOK_MASK 0x800UL /**< Bit mask for ETH_RESPNOTOK */ +#define _ETH_IENRO_RESPNOTOK_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RESPNOTOK_DEFAULT (_ETH_IENRO_RESPNOTOK_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_NONZEROPFRMQUANT (0x1UL << 12) /**< Pause frame with non-zero pause quantum interrupt mask */ +#define _ETH_IENRO_NONZEROPFRMQUANT_SHIFT 12 /**< Shift value for ETH_NONZEROPFRMQUANT */ +#define _ETH_IENRO_NONZEROPFRMQUANT_MASK 0x1000UL /**< Bit mask for ETH_NONZEROPFRMQUANT */ +#define _ETH_IENRO_NONZEROPFRMQUANT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_NONZEROPFRMQUANT_DEFAULT (_ETH_IENRO_NONZEROPFRMQUANT_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PAUSETIMEZERO (0x1UL << 13) /**< pause time zero interrupt mask */ +#define _ETH_IENRO_PAUSETIMEZERO_SHIFT 13 /**< Shift value for ETH_PAUSETIMEZERO */ +#define _ETH_IENRO_PAUSETIMEZERO_MASK 0x2000UL /**< Bit mask for ETH_PAUSETIMEZERO */ +#define _ETH_IENRO_PAUSETIMEZERO_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PAUSETIMEZERO_DEFAULT (_ETH_IENRO_PAUSETIMEZERO_DEFAULT << 13) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PFRMTX (0x1UL << 14) /**< pause frame transmitted interrupt mask */ +#define _ETH_IENRO_PFRMTX_SHIFT 14 /**< Shift value for ETH_PFRMTX */ +#define _ETH_IENRO_PFRMTX_MASK 0x4000UL /**< Bit mask for ETH_PFRMTX */ +#define _ETH_IENRO_PFRMTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PFRMTX_DEFAULT (_ETH_IENRO_PFRMTX_DEFAULT << 14) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPDLYREQFRMRX (0x1UL << 18) /**< PTP delay_req frame received mask */ +#define _ETH_IENRO_PTPDLYREQFRMRX_SHIFT 18 /**< Shift value for ETH_PTPDLYREQFRMRX */ +#define _ETH_IENRO_PTPDLYREQFRMRX_MASK 0x40000UL /**< Bit mask for ETH_PTPDLYREQFRMRX */ +#define _ETH_IENRO_PTPDLYREQFRMRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPDLYREQFRMRX_DEFAULT (_ETH_IENRO_PTPDLYREQFRMRX_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPSYNCFRMRX (0x1UL << 19) /**< PTP sync frame received mask */ +#define _ETH_IENRO_PTPSYNCFRMRX_SHIFT 19 /**< Shift value for ETH_PTPSYNCFRMRX */ +#define _ETH_IENRO_PTPSYNCFRMRX_MASK 0x80000UL /**< Bit mask for ETH_PTPSYNCFRMRX */ +#define _ETH_IENRO_PTPSYNCFRMRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPSYNCFRMRX_DEFAULT (_ETH_IENRO_PTPSYNCFRMRX_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPDLYREQFRMTX (0x1UL << 20) /**< PTP delay_req frame transmitted mask */ +#define _ETH_IENRO_PTPDLYREQFRMTX_SHIFT 20 /**< Shift value for ETH_PTPDLYREQFRMTX */ +#define _ETH_IENRO_PTPDLYREQFRMTX_MASK 0x100000UL /**< Bit mask for ETH_PTPDLYREQFRMTX */ +#define _ETH_IENRO_PTPDLYREQFRMTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPDLYREQFRMTX_DEFAULT (_ETH_IENRO_PTPDLYREQFRMTX_DEFAULT << 20) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPSYNCFRMTX (0x1UL << 21) /**< PTP sync frame transmitted mask */ +#define _ETH_IENRO_PTPSYNCFRMTX_SHIFT 21 /**< Shift value for ETH_PTPSYNCFRMTX */ +#define _ETH_IENRO_PTPSYNCFRMTX_MASK 0x200000UL /**< Bit mask for ETH_PTPSYNCFRMTX */ +#define _ETH_IENRO_PTPSYNCFRMTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPSYNCFRMTX_DEFAULT (_ETH_IENRO_PTPSYNCFRMTX_DEFAULT << 21) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPPDLYREQFRMRX (0x1UL << 22) /**< PTP pdelay_req frame received mask */ +#define _ETH_IENRO_PTPPDLYREQFRMRX_SHIFT 22 /**< Shift value for ETH_PTPPDLYREQFRMRX */ +#define _ETH_IENRO_PTPPDLYREQFRMRX_MASK 0x400000UL /**< Bit mask for ETH_PTPPDLYREQFRMRX */ +#define _ETH_IENRO_PTPPDLYREQFRMRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPPDLYREQFRMRX_DEFAULT (_ETH_IENRO_PTPPDLYREQFRMRX_DEFAULT << 22) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPPDLYRESPFRMRX (0x1UL << 23) /**< PTP pdelay_resp frame received mask */ +#define _ETH_IENRO_PTPPDLYRESPFRMRX_SHIFT 23 /**< Shift value for ETH_PTPPDLYRESPFRMRX */ +#define _ETH_IENRO_PTPPDLYRESPFRMRX_MASK 0x800000UL /**< Bit mask for ETH_PTPPDLYRESPFRMRX */ +#define _ETH_IENRO_PTPPDLYRESPFRMRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPPDLYRESPFRMRX_DEFAULT (_ETH_IENRO_PTPPDLYRESPFRMRX_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPPDLYREQFRMTX (0x1UL << 24) /**< PTP pdelay_req frame transmitted mask */ +#define _ETH_IENRO_PTPPDLYREQFRMTX_SHIFT 24 /**< Shift value for ETH_PTPPDLYREQFRMTX */ +#define _ETH_IENRO_PTPPDLYREQFRMTX_MASK 0x1000000UL /**< Bit mask for ETH_PTPPDLYREQFRMTX */ +#define _ETH_IENRO_PTPPDLYREQFRMTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPPDLYREQFRMTX_DEFAULT (_ETH_IENRO_PTPPDLYREQFRMTX_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPPDLYRESPFRMTX (0x1UL << 25) /**< PTP pdelay_resp frame transmitted mask */ +#define _ETH_IENRO_PTPPDLYRESPFRMTX_SHIFT 25 /**< Shift value for ETH_PTPPDLYRESPFRMTX */ +#define _ETH_IENRO_PTPPDLYRESPFRMTX_MASK 0x2000000UL /**< Bit mask for ETH_PTPPDLYRESPFRMTX */ +#define _ETH_IENRO_PTPPDLYRESPFRMTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_PTPPDLYRESPFRMTX_DEFAULT (_ETH_IENRO_PTPPDLYRESPFRMTX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_TSUSECREGINCR (0x1UL << 26) /**< TSU seconds register increment mask */ +#define _ETH_IENRO_TSUSECREGINCR_SHIFT 26 /**< Shift value for ETH_TSUSECREGINCR */ +#define _ETH_IENRO_TSUSECREGINCR_MASK 0x4000000UL /**< Bit mask for ETH_TSUSECREGINCR */ +#define _ETH_IENRO_TSUSECREGINCR_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_TSUSECREGINCR_DEFAULT (_ETH_IENRO_TSUSECREGINCR_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RXLPIINDC (0x1UL << 27) /**< RX LPI indication mask */ +#define _ETH_IENRO_RXLPIINDC_SHIFT 27 /**< Shift value for ETH_RXLPIINDC */ +#define _ETH_IENRO_RXLPIINDC_MASK 0x8000000UL /**< Bit mask for ETH_RXLPIINDC */ +#define _ETH_IENRO_RXLPIINDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_RXLPIINDC_DEFAULT (_ETH_IENRO_RXLPIINDC_DEFAULT << 27) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_WOLEVNTRX (0x1UL << 28) /**< WOL event received mask */ +#define _ETH_IENRO_WOLEVNTRX_SHIFT 28 /**< Shift value for ETH_WOLEVNTRX */ +#define _ETH_IENRO_WOLEVNTRX_MASK 0x10000000UL /**< Bit mask for ETH_WOLEVNTRX */ +#define _ETH_IENRO_WOLEVNTRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_WOLEVNTRX_DEFAULT (_ETH_IENRO_WOLEVNTRX_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_TSUTIMERCOMP (0x1UL << 29) /**< TSU timer comparison interrupt mask. */ +#define _ETH_IENRO_TSUTIMERCOMP_SHIFT 29 /**< Shift value for ETH_TSUTIMERCOMP */ +#define _ETH_IENRO_TSUTIMERCOMP_MASK 0x20000000UL /**< Bit mask for ETH_TSUTIMERCOMP */ +#define _ETH_IENRO_TSUTIMERCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ +#define ETH_IENRO_TSUTIMERCOMP_DEFAULT (_ETH_IENRO_TSUTIMERCOMP_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_IENRO */ + +/* Bit fields for ETH PHYMNGMNT */ +#define _ETH_PHYMNGMNT_RESETVALUE 0x00000000UL /**< Default value for ETH_PHYMNGMNT */ +#define _ETH_PHYMNGMNT_MASK 0xFFFFFFFFUL /**< Mask for ETH_PHYMNGMNT */ +#define _ETH_PHYMNGMNT_PHYRWDATA_SHIFT 0 /**< Shift value for ETH_PHYRWDATA */ +#define _ETH_PHYMNGMNT_PHYRWDATA_MASK 0xFFFFUL /**< Bit mask for ETH_PHYRWDATA */ +#define _ETH_PHYMNGMNT_PHYRWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ +#define ETH_PHYMNGMNT_PHYRWDATA_DEFAULT (_ETH_PHYMNGMNT_PHYRWDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ +#define _ETH_PHYMNGMNT_WRITE10_SHIFT 16 /**< Shift value for ETH_WRITE10 */ +#define _ETH_PHYMNGMNT_WRITE10_MASK 0x30000UL /**< Bit mask for ETH_WRITE10 */ +#define _ETH_PHYMNGMNT_WRITE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ +#define ETH_PHYMNGMNT_WRITE10_DEFAULT (_ETH_PHYMNGMNT_WRITE10_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ +#define _ETH_PHYMNGMNT_REGADDR_SHIFT 18 /**< Shift value for ETH_REGADDR */ +#define _ETH_PHYMNGMNT_REGADDR_MASK 0x7C0000UL /**< Bit mask for ETH_REGADDR */ +#define _ETH_PHYMNGMNT_REGADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ +#define ETH_PHYMNGMNT_REGADDR_DEFAULT (_ETH_PHYMNGMNT_REGADDR_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ +#define _ETH_PHYMNGMNT_PHYADDR_SHIFT 23 /**< Shift value for ETH_PHYADDR */ +#define _ETH_PHYMNGMNT_PHYADDR_MASK 0xF800000UL /**< Bit mask for ETH_PHYADDR */ +#define _ETH_PHYMNGMNT_PHYADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ +#define ETH_PHYMNGMNT_PHYADDR_DEFAULT (_ETH_PHYMNGMNT_PHYADDR_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ +#define _ETH_PHYMNGMNT_OPERATION_SHIFT 28 /**< Shift value for ETH_OPERATION */ +#define _ETH_PHYMNGMNT_OPERATION_MASK 0x30000000UL /**< Bit mask for ETH_OPERATION */ +#define _ETH_PHYMNGMNT_OPERATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ +#define ETH_PHYMNGMNT_OPERATION_DEFAULT (_ETH_PHYMNGMNT_OPERATION_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ +#define ETH_PHYMNGMNT_WRITE1 (0x1UL << 30) /**< Must be written to 1 for a valid Clause 22 frame and to 0 for a valid Clause 45 frame. */ +#define _ETH_PHYMNGMNT_WRITE1_SHIFT 30 /**< Shift value for ETH_WRITE1 */ +#define _ETH_PHYMNGMNT_WRITE1_MASK 0x40000000UL /**< Bit mask for ETH_WRITE1 */ +#define _ETH_PHYMNGMNT_WRITE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ +#define ETH_PHYMNGMNT_WRITE1_DEFAULT (_ETH_PHYMNGMNT_WRITE1_DEFAULT << 30) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ +#define ETH_PHYMNGMNT_WRITE0 (0x1UL << 31) /**< Must be written with 0. */ +#define _ETH_PHYMNGMNT_WRITE0_SHIFT 31 /**< Shift value for ETH_WRITE0 */ +#define _ETH_PHYMNGMNT_WRITE0_MASK 0x80000000UL /**< Bit mask for ETH_WRITE0 */ +#define _ETH_PHYMNGMNT_WRITE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ +#define ETH_PHYMNGMNT_WRITE0_DEFAULT (_ETH_PHYMNGMNT_WRITE0_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ + +/* Bit fields for ETH RXPAUSEQUANT */ +#define _ETH_RXPAUSEQUANT_RESETVALUE 0x00000000UL /**< Default value for ETH_RXPAUSEQUANT */ +#define _ETH_RXPAUSEQUANT_MASK 0x0000FFFFUL /**< Mask for ETH_RXPAUSEQUANT */ +#define _ETH_RXPAUSEQUANT_QUANT_SHIFT 0 /**< Shift value for ETH_QUANT */ +#define _ETH_RXPAUSEQUANT_QUANT_MASK 0xFFFFUL /**< Bit mask for ETH_QUANT */ +#define _ETH_RXPAUSEQUANT_QUANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXPAUSEQUANT */ +#define ETH_RXPAUSEQUANT_QUANT_DEFAULT (_ETH_RXPAUSEQUANT_QUANT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXPAUSEQUANT */ + +/* Bit fields for ETH TXPAUSEQUANT */ +#define _ETH_TXPAUSEQUANT_RESETVALUE 0xFFFFFFFFUL /**< Default value for ETH_TXPAUSEQUANT */ +#define _ETH_TXPAUSEQUANT_MASK 0xFFFFFFFFUL /**< Mask for ETH_TXPAUSEQUANT */ +#define _ETH_TXPAUSEQUANT_QUANT_SHIFT 0 /**< Shift value for ETH_QUANT */ +#define _ETH_TXPAUSEQUANT_QUANT_MASK 0xFFFFUL /**< Bit mask for ETH_QUANT */ +#define _ETH_TXPAUSEQUANT_QUANT_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT */ +#define ETH_TXPAUSEQUANT_QUANT_DEFAULT (_ETH_TXPAUSEQUANT_QUANT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT */ +#define _ETH_TXPAUSEQUANT_QUANTP1_SHIFT 16 /**< Shift value for ETH_QUANTP1 */ +#define _ETH_TXPAUSEQUANT_QUANTP1_MASK 0xFFFF0000UL /**< Bit mask for ETH_QUANTP1 */ +#define _ETH_TXPAUSEQUANT_QUANTP1_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT */ +#define ETH_TXPAUSEQUANT_QUANTP1_DEFAULT (_ETH_TXPAUSEQUANT_QUANTP1_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT */ + +/* Bit fields for ETH PBUFTXCUTTHRU */ +#define _ETH_PBUFTXCUTTHRU_RESETVALUE 0x000003FFUL /**< Default value for ETH_PBUFTXCUTTHRU */ +#define _ETH_PBUFTXCUTTHRU_MASK 0x800003FFUL /**< Mask for ETH_PBUFTXCUTTHRU */ +#define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRUTHR_SHIFT 0 /**< Shift value for ETH_DMATXCUTTHRUTHR */ +#define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRUTHR_MASK 0x3FFUL /**< Bit mask for ETH_DMATXCUTTHRUTHR */ +#define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRUTHR_DEFAULT 0x000003FFUL /**< Mode DEFAULT for ETH_PBUFTXCUTTHRU */ +#define ETH_PBUFTXCUTTHRU_DMATXCUTTHRUTHR_DEFAULT (_ETH_PBUFTXCUTTHRU_DMATXCUTTHRUTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_PBUFTXCUTTHRU */ +#define ETH_PBUFTXCUTTHRU_DMATXCUTTHRU (0x1UL << 31) /**< Enable TX partial store and forward operation */ +#define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRU_SHIFT 31 /**< Shift value for ETH_DMATXCUTTHRU */ +#define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRU_MASK 0x80000000UL /**< Bit mask for ETH_DMATXCUTTHRU */ +#define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PBUFTXCUTTHRU */ +#define ETH_PBUFTXCUTTHRU_DMATXCUTTHRU_DEFAULT (_ETH_PBUFTXCUTTHRU_DMATXCUTTHRU_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_PBUFTXCUTTHRU */ + +/* Bit fields for ETH PBUFRXCUTTHRU */ +#define _ETH_PBUFRXCUTTHRU_RESETVALUE 0x000003FFUL /**< Default value for ETH_PBUFRXCUTTHRU */ +#define _ETH_PBUFRXCUTTHRU_MASK 0x800003FFUL /**< Mask for ETH_PBUFRXCUTTHRU */ +#define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRUTHR_SHIFT 0 /**< Shift value for ETH_DMARXCUTTHRUTHR */ +#define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRUTHR_MASK 0x3FFUL /**< Bit mask for ETH_DMARXCUTTHRUTHR */ +#define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRUTHR_DEFAULT 0x000003FFUL /**< Mode DEFAULT for ETH_PBUFRXCUTTHRU */ +#define ETH_PBUFRXCUTTHRU_DMARXCUTTHRUTHR_DEFAULT (_ETH_PBUFRXCUTTHRU_DMARXCUTTHRUTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_PBUFRXCUTTHRU */ +#define ETH_PBUFRXCUTTHRU_DMARXCUTTHRU (0x1UL << 31) /**< Enable RX partial store and forward operation */ +#define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRU_SHIFT 31 /**< Shift value for ETH_DMARXCUTTHRU */ +#define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRU_MASK 0x80000000UL /**< Bit mask for ETH_DMARXCUTTHRU */ +#define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PBUFRXCUTTHRU */ +#define ETH_PBUFRXCUTTHRU_DMARXCUTTHRU_DEFAULT (_ETH_PBUFRXCUTTHRU_DMARXCUTTHRU_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_PBUFRXCUTTHRU */ + +/* Bit fields for ETH JUMBOMAXLEN */ +#define _ETH_JUMBOMAXLEN_RESETVALUE 0x00002800UL /**< Default value for ETH_JUMBOMAXLEN */ +#define _ETH_JUMBOMAXLEN_MASK 0x00003FFFUL /**< Mask for ETH_JUMBOMAXLEN */ +#define _ETH_JUMBOMAXLEN_JUMBOMAXLEN_SHIFT 0 /**< Shift value for ETH_JUMBOMAXLEN */ +#define _ETH_JUMBOMAXLEN_JUMBOMAXLEN_MASK 0x3FFFUL /**< Bit mask for ETH_JUMBOMAXLEN */ +#define _ETH_JUMBOMAXLEN_JUMBOMAXLEN_DEFAULT 0x00002800UL /**< Mode DEFAULT for ETH_JUMBOMAXLEN */ +#define ETH_JUMBOMAXLEN_JUMBOMAXLEN_DEFAULT (_ETH_JUMBOMAXLEN_JUMBOMAXLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_JUMBOMAXLEN */ + +/* Bit fields for ETH IMOD */ +#define _ETH_IMOD_RESETVALUE 0x00000000UL /**< Default value for ETH_IMOD */ +#define _ETH_IMOD_MASK 0x00FF00FFUL /**< Mask for ETH_IMOD */ +#define _ETH_IMOD_RXINTMOD_SHIFT 0 /**< Shift value for ETH_RXINTMOD */ +#define _ETH_IMOD_RXINTMOD_MASK 0xFFUL /**< Bit mask for ETH_RXINTMOD */ +#define _ETH_IMOD_RXINTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IMOD */ +#define ETH_IMOD_RXINTMOD_DEFAULT (_ETH_IMOD_RXINTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_IMOD */ +#define _ETH_IMOD_TXINTMOD_SHIFT 16 /**< Shift value for ETH_TXINTMOD */ +#define _ETH_IMOD_TXINTMOD_MASK 0xFF0000UL /**< Bit mask for ETH_TXINTMOD */ +#define _ETH_IMOD_TXINTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IMOD */ +#define ETH_IMOD_TXINTMOD_DEFAULT (_ETH_IMOD_TXINTMOD_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_IMOD */ + +/* Bit fields for ETH SYSWAKETIME */ +#define _ETH_SYSWAKETIME_RESETVALUE 0x00000000UL /**< Default value for ETH_SYSWAKETIME */ +#define _ETH_SYSWAKETIME_MASK 0x0000FFFFUL /**< Mask for ETH_SYSWAKETIME */ +#define _ETH_SYSWAKETIME_SYSWAKETIME_SHIFT 0 /**< Shift value for ETH_SYSWAKETIME */ +#define _ETH_SYSWAKETIME_SYSWAKETIME_MASK 0xFFFFUL /**< Bit mask for ETH_SYSWAKETIME */ +#define _ETH_SYSWAKETIME_SYSWAKETIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SYSWAKETIME */ +#define ETH_SYSWAKETIME_SYSWAKETIME_DEFAULT (_ETH_SYSWAKETIME_SYSWAKETIME_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SYSWAKETIME */ + +/* Bit fields for ETH HASHBOTTOM */ +#define _ETH_HASHBOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_HASHBOTTOM */ +#define _ETH_HASHBOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_HASHBOTTOM */ +#define _ETH_HASHBOTTOM_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_HASHBOTTOM_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_HASHBOTTOM_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_HASHBOTTOM */ +#define ETH_HASHBOTTOM_ADDR_DEFAULT (_ETH_HASHBOTTOM_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_HASHBOTTOM */ + +/* Bit fields for ETH HASHTOP */ +#define _ETH_HASHTOP_RESETVALUE 0x00000000UL /**< Default value for ETH_HASHTOP */ +#define _ETH_HASHTOP_MASK 0xFFFFFFFFUL /**< Mask for ETH_HASHTOP */ +#define _ETH_HASHTOP_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_HASHTOP_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_HASHTOP_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_HASHTOP */ +#define ETH_HASHTOP_ADDR_DEFAULT (_ETH_HASHTOP_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_HASHTOP */ + +/* Bit fields for ETH SPECADDR1BOTTOM */ +#define _ETH_SPECADDR1BOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR1BOTTOM */ +#define _ETH_SPECADDR1BOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_SPECADDR1BOTTOM */ +#define _ETH_SPECADDR1BOTTOM_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_SPECADDR1BOTTOM_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_SPECADDR1BOTTOM_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR1BOTTOM */ +#define ETH_SPECADDR1BOTTOM_ADDR_DEFAULT (_ETH_SPECADDR1BOTTOM_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR1BOTTOM */ + +/* Bit fields for ETH SPECADDR1TOP */ +#define _ETH_SPECADDR1TOP_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR1TOP */ +#define _ETH_SPECADDR1TOP_MASK 0x0001FFFFUL /**< Mask for ETH_SPECADDR1TOP */ +#define _ETH_SPECADDR1TOP_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_SPECADDR1TOP_ADDR_MASK 0xFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_SPECADDR1TOP_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR1TOP */ +#define ETH_SPECADDR1TOP_ADDR_DEFAULT (_ETH_SPECADDR1TOP_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR1TOP */ +#define ETH_SPECADDR1TOP_FILTERTYPE (0x1UL << 16) /**< MAC SA or DA selection */ +#define _ETH_SPECADDR1TOP_FILTERTYPE_SHIFT 16 /**< Shift value for ETH_FILTERTYPE */ +#define _ETH_SPECADDR1TOP_FILTERTYPE_MASK 0x10000UL /**< Bit mask for ETH_FILTERTYPE */ +#define _ETH_SPECADDR1TOP_FILTERTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR1TOP */ +#define _ETH_SPECADDR1TOP_FILTERTYPE_DA 0x00000000UL /**< Mode DA for ETH_SPECADDR1TOP */ +#define _ETH_SPECADDR1TOP_FILTERTYPE_SA 0x00000001UL /**< Mode SA for ETH_SPECADDR1TOP */ +#define ETH_SPECADDR1TOP_FILTERTYPE_DEFAULT (_ETH_SPECADDR1TOP_FILTERTYPE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_SPECADDR1TOP */ +#define ETH_SPECADDR1TOP_FILTERTYPE_DA (_ETH_SPECADDR1TOP_FILTERTYPE_DA << 16) /**< Shifted mode DA for ETH_SPECADDR1TOP */ +#define ETH_SPECADDR1TOP_FILTERTYPE_SA (_ETH_SPECADDR1TOP_FILTERTYPE_SA << 16) /**< Shifted mode SA for ETH_SPECADDR1TOP */ + +/* Bit fields for ETH SPECADDR2BOTTOM */ +#define _ETH_SPECADDR2BOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR2BOTTOM */ +#define _ETH_SPECADDR2BOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_SPECADDR2BOTTOM */ +#define _ETH_SPECADDR2BOTTOM_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_SPECADDR2BOTTOM_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_SPECADDR2BOTTOM_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR2BOTTOM */ +#define ETH_SPECADDR2BOTTOM_ADDR_DEFAULT (_ETH_SPECADDR2BOTTOM_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR2BOTTOM */ + +/* Bit fields for ETH SPECADDR2TOP */ +#define _ETH_SPECADDR2TOP_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR2TOP */ +#define _ETH_SPECADDR2TOP_MASK 0x3F01FFFFUL /**< Mask for ETH_SPECADDR2TOP */ +#define _ETH_SPECADDR2TOP_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_SPECADDR2TOP_ADDR_MASK 0xFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_SPECADDR2TOP_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR2TOP */ +#define ETH_SPECADDR2TOP_ADDR_DEFAULT (_ETH_SPECADDR2TOP_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR2TOP */ +#define ETH_SPECADDR2TOP_FILTERTYPE (0x1UL << 16) /**< MAC SA or DA selection */ +#define _ETH_SPECADDR2TOP_FILTERTYPE_SHIFT 16 /**< Shift value for ETH_FILTERTYPE */ +#define _ETH_SPECADDR2TOP_FILTERTYPE_MASK 0x10000UL /**< Bit mask for ETH_FILTERTYPE */ +#define _ETH_SPECADDR2TOP_FILTERTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR2TOP */ +#define _ETH_SPECADDR2TOP_FILTERTYPE_DA 0x00000000UL /**< Mode DA for ETH_SPECADDR2TOP */ +#define _ETH_SPECADDR2TOP_FILTERTYPE_SA 0x00000001UL /**< Mode SA for ETH_SPECADDR2TOP */ +#define ETH_SPECADDR2TOP_FILTERTYPE_DEFAULT (_ETH_SPECADDR2TOP_FILTERTYPE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_SPECADDR2TOP */ +#define ETH_SPECADDR2TOP_FILTERTYPE_DA (_ETH_SPECADDR2TOP_FILTERTYPE_DA << 16) /**< Shifted mode DA for ETH_SPECADDR2TOP */ +#define ETH_SPECADDR2TOP_FILTERTYPE_SA (_ETH_SPECADDR2TOP_FILTERTYPE_SA << 16) /**< Shifted mode SA for ETH_SPECADDR2TOP */ +#define _ETH_SPECADDR2TOP_FILTERBYTEMASK_SHIFT 24 /**< Shift value for ETH_FILTERBYTEMASK */ +#define _ETH_SPECADDR2TOP_FILTERBYTEMASK_MASK 0x3F000000UL /**< Bit mask for ETH_FILTERBYTEMASK */ +#define _ETH_SPECADDR2TOP_FILTERBYTEMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR2TOP */ +#define ETH_SPECADDR2TOP_FILTERBYTEMASK_DEFAULT (_ETH_SPECADDR2TOP_FILTERBYTEMASK_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_SPECADDR2TOP */ + +/* Bit fields for ETH SPECADDR3BOTTOM */ +#define _ETH_SPECADDR3BOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR3BOTTOM */ +#define _ETH_SPECADDR3BOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_SPECADDR3BOTTOM */ +#define _ETH_SPECADDR3BOTTOM_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_SPECADDR3BOTTOM_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_SPECADDR3BOTTOM_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR3BOTTOM */ +#define ETH_SPECADDR3BOTTOM_ADDR_DEFAULT (_ETH_SPECADDR3BOTTOM_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR3BOTTOM */ + +/* Bit fields for ETH SPECADDR3TOP */ +#define _ETH_SPECADDR3TOP_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR3TOP */ +#define _ETH_SPECADDR3TOP_MASK 0x3F01FFFFUL /**< Mask for ETH_SPECADDR3TOP */ +#define _ETH_SPECADDR3TOP_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_SPECADDR3TOP_ADDR_MASK 0xFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_SPECADDR3TOP_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR3TOP */ +#define ETH_SPECADDR3TOP_ADDR_DEFAULT (_ETH_SPECADDR3TOP_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR3TOP */ +#define ETH_SPECADDR3TOP_FILTERTYPE (0x1UL << 16) /**< MAC SA or DA selection */ +#define _ETH_SPECADDR3TOP_FILTERTYPE_SHIFT 16 /**< Shift value for ETH_FILTERTYPE */ +#define _ETH_SPECADDR3TOP_FILTERTYPE_MASK 0x10000UL /**< Bit mask for ETH_FILTERTYPE */ +#define _ETH_SPECADDR3TOP_FILTERTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR3TOP */ +#define _ETH_SPECADDR3TOP_FILTERTYPE_DA 0x00000000UL /**< Mode DA for ETH_SPECADDR3TOP */ +#define _ETH_SPECADDR3TOP_FILTERTYPE_SA 0x00000001UL /**< Mode SA for ETH_SPECADDR3TOP */ +#define ETH_SPECADDR3TOP_FILTERTYPE_DEFAULT (_ETH_SPECADDR3TOP_FILTERTYPE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_SPECADDR3TOP */ +#define ETH_SPECADDR3TOP_FILTERTYPE_DA (_ETH_SPECADDR3TOP_FILTERTYPE_DA << 16) /**< Shifted mode DA for ETH_SPECADDR3TOP */ +#define ETH_SPECADDR3TOP_FILTERTYPE_SA (_ETH_SPECADDR3TOP_FILTERTYPE_SA << 16) /**< Shifted mode SA for ETH_SPECADDR3TOP */ +#define _ETH_SPECADDR3TOP_FILTERBYTEMASK_SHIFT 24 /**< Shift value for ETH_FILTERBYTEMASK */ +#define _ETH_SPECADDR3TOP_FILTERBYTEMASK_MASK 0x3F000000UL /**< Bit mask for ETH_FILTERBYTEMASK */ +#define _ETH_SPECADDR3TOP_FILTERBYTEMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR3TOP */ +#define ETH_SPECADDR3TOP_FILTERBYTEMASK_DEFAULT (_ETH_SPECADDR3TOP_FILTERBYTEMASK_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_SPECADDR3TOP */ + +/* Bit fields for ETH SPECADDR4BOTTOM */ +#define _ETH_SPECADDR4BOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR4BOTTOM */ +#define _ETH_SPECADDR4BOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_SPECADDR4BOTTOM */ +#define _ETH_SPECADDR4BOTTOM_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_SPECADDR4BOTTOM_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_SPECADDR4BOTTOM_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR4BOTTOM */ +#define ETH_SPECADDR4BOTTOM_ADDR_DEFAULT (_ETH_SPECADDR4BOTTOM_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR4BOTTOM */ + +/* Bit fields for ETH SPECADDR4TOP */ +#define _ETH_SPECADDR4TOP_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR4TOP */ +#define _ETH_SPECADDR4TOP_MASK 0x3F01FFFFUL /**< Mask for ETH_SPECADDR4TOP */ +#define _ETH_SPECADDR4TOP_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_SPECADDR4TOP_ADDR_MASK 0xFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_SPECADDR4TOP_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR4TOP */ +#define ETH_SPECADDR4TOP_ADDR_DEFAULT (_ETH_SPECADDR4TOP_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR4TOP */ +#define ETH_SPECADDR4TOP_FILTERTYPE (0x1UL << 16) /**< MAC SA or DA selection */ +#define _ETH_SPECADDR4TOP_FILTERTYPE_SHIFT 16 /**< Shift value for ETH_FILTERTYPE */ +#define _ETH_SPECADDR4TOP_FILTERTYPE_MASK 0x10000UL /**< Bit mask for ETH_FILTERTYPE */ +#define _ETH_SPECADDR4TOP_FILTERTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR4TOP */ +#define _ETH_SPECADDR4TOP_FILTERTYPE_DA 0x00000000UL /**< Mode DA for ETH_SPECADDR4TOP */ +#define _ETH_SPECADDR4TOP_FILTERTYPE_SA 0x00000001UL /**< Mode SA for ETH_SPECADDR4TOP */ +#define ETH_SPECADDR4TOP_FILTERTYPE_DEFAULT (_ETH_SPECADDR4TOP_FILTERTYPE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_SPECADDR4TOP */ +#define ETH_SPECADDR4TOP_FILTERTYPE_DA (_ETH_SPECADDR4TOP_FILTERTYPE_DA << 16) /**< Shifted mode DA for ETH_SPECADDR4TOP */ +#define ETH_SPECADDR4TOP_FILTERTYPE_SA (_ETH_SPECADDR4TOP_FILTERTYPE_SA << 16) /**< Shifted mode SA for ETH_SPECADDR4TOP */ +#define _ETH_SPECADDR4TOP_FILTERBYTEMASK_SHIFT 24 /**< Shift value for ETH_FILTERBYTEMASK */ +#define _ETH_SPECADDR4TOP_FILTERBYTEMASK_MASK 0x3F000000UL /**< Bit mask for ETH_FILTERBYTEMASK */ +#define _ETH_SPECADDR4TOP_FILTERBYTEMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR4TOP */ +#define ETH_SPECADDR4TOP_FILTERBYTEMASK_DEFAULT (_ETH_SPECADDR4TOP_FILTERBYTEMASK_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_SPECADDR4TOP */ + +/* Bit fields for ETH SPECTYPE1 */ +#define _ETH_SPECTYPE1_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECTYPE1 */ +#define _ETH_SPECTYPE1_MASK 0x8000FFFFUL /**< Mask for ETH_SPECTYPE1 */ +#define _ETH_SPECTYPE1_MATCH_SHIFT 0 /**< Shift value for ETH_MATCH */ +#define _ETH_SPECTYPE1_MATCH_MASK 0xFFFFUL /**< Bit mask for ETH_MATCH */ +#define _ETH_SPECTYPE1_MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE1 */ +#define ETH_SPECTYPE1_MATCH_DEFAULT (_ETH_SPECTYPE1_MATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECTYPE1 */ +#define ETH_SPECTYPE1_ENBCOPY (0x1UL << 31) /**< Enable copying of type ID match 1 matched frames. */ +#define _ETH_SPECTYPE1_ENBCOPY_SHIFT 31 /**< Shift value for ETH_ENBCOPY */ +#define _ETH_SPECTYPE1_ENBCOPY_MASK 0x80000000UL /**< Bit mask for ETH_ENBCOPY */ +#define _ETH_SPECTYPE1_ENBCOPY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE1 */ +#define ETH_SPECTYPE1_ENBCOPY_DEFAULT (_ETH_SPECTYPE1_ENBCOPY_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_SPECTYPE1 */ + +/* Bit fields for ETH SPECTYPE2 */ +#define _ETH_SPECTYPE2_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECTYPE2 */ +#define _ETH_SPECTYPE2_MASK 0x8000FFFFUL /**< Mask for ETH_SPECTYPE2 */ +#define _ETH_SPECTYPE2_MATCH_SHIFT 0 /**< Shift value for ETH_MATCH */ +#define _ETH_SPECTYPE2_MATCH_MASK 0xFFFFUL /**< Bit mask for ETH_MATCH */ +#define _ETH_SPECTYPE2_MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE2 */ +#define ETH_SPECTYPE2_MATCH_DEFAULT (_ETH_SPECTYPE2_MATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECTYPE2 */ +#define ETH_SPECTYPE2_ENBCOPY (0x1UL << 31) /**< Enable copying of type ID match 2 matched frames. */ +#define _ETH_SPECTYPE2_ENBCOPY_SHIFT 31 /**< Shift value for ETH_ENBCOPY */ +#define _ETH_SPECTYPE2_ENBCOPY_MASK 0x80000000UL /**< Bit mask for ETH_ENBCOPY */ +#define _ETH_SPECTYPE2_ENBCOPY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE2 */ +#define ETH_SPECTYPE2_ENBCOPY_DEFAULT (_ETH_SPECTYPE2_ENBCOPY_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_SPECTYPE2 */ + +/* Bit fields for ETH SPECTYPE3 */ +#define _ETH_SPECTYPE3_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECTYPE3 */ +#define _ETH_SPECTYPE3_MASK 0x8000FFFFUL /**< Mask for ETH_SPECTYPE3 */ +#define _ETH_SPECTYPE3_MATCH_SHIFT 0 /**< Shift value for ETH_MATCH */ +#define _ETH_SPECTYPE3_MATCH_MASK 0xFFFFUL /**< Bit mask for ETH_MATCH */ +#define _ETH_SPECTYPE3_MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE3 */ +#define ETH_SPECTYPE3_MATCH_DEFAULT (_ETH_SPECTYPE3_MATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECTYPE3 */ +#define ETH_SPECTYPE3_ENBCOPY (0x1UL << 31) /**< Enable copying of type ID match 3 matched frames. */ +#define _ETH_SPECTYPE3_ENBCOPY_SHIFT 31 /**< Shift value for ETH_ENBCOPY */ +#define _ETH_SPECTYPE3_ENBCOPY_MASK 0x80000000UL /**< Bit mask for ETH_ENBCOPY */ +#define _ETH_SPECTYPE3_ENBCOPY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE3 */ +#define ETH_SPECTYPE3_ENBCOPY_DEFAULT (_ETH_SPECTYPE3_ENBCOPY_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_SPECTYPE3 */ + +/* Bit fields for ETH SPECTYPE4 */ +#define _ETH_SPECTYPE4_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECTYPE4 */ +#define _ETH_SPECTYPE4_MASK 0x8000FFFFUL /**< Mask for ETH_SPECTYPE4 */ +#define _ETH_SPECTYPE4_MATCH_SHIFT 0 /**< Shift value for ETH_MATCH */ +#define _ETH_SPECTYPE4_MATCH_MASK 0xFFFFUL /**< Bit mask for ETH_MATCH */ +#define _ETH_SPECTYPE4_MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE4 */ +#define ETH_SPECTYPE4_MATCH_DEFAULT (_ETH_SPECTYPE4_MATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECTYPE4 */ +#define ETH_SPECTYPE4_ENBCOPY (0x1UL << 31) /**< Enable copying of type ID match 4 matched frames. */ +#define _ETH_SPECTYPE4_ENBCOPY_SHIFT 31 /**< Shift value for ETH_ENBCOPY */ +#define _ETH_SPECTYPE4_ENBCOPY_MASK 0x80000000UL /**< Bit mask for ETH_ENBCOPY */ +#define _ETH_SPECTYPE4_ENBCOPY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE4 */ +#define ETH_SPECTYPE4_ENBCOPY_DEFAULT (_ETH_SPECTYPE4_ENBCOPY_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_SPECTYPE4 */ + +/* Bit fields for ETH WOLREG */ +#define _ETH_WOLREG_RESETVALUE 0x00000000UL /**< Default value for ETH_WOLREG */ +#define _ETH_WOLREG_MASK 0x000FFFFFUL /**< Mask for ETH_WOLREG */ +#define _ETH_WOLREG_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_WOLREG_ADDR_MASK 0xFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_WOLREG_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_WOLREG */ +#define ETH_WOLREG_ADDR_DEFAULT (_ETH_WOLREG_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_WOLREG */ +#define ETH_WOLREG_WOLMASK0 (0x1UL << 16) /**< Wake on LAN magic packet event enable */ +#define _ETH_WOLREG_WOLMASK0_SHIFT 16 /**< Shift value for ETH_WOLMASK0 */ +#define _ETH_WOLREG_WOLMASK0_MASK 0x10000UL /**< Bit mask for ETH_WOLMASK0 */ +#define _ETH_WOLREG_WOLMASK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_WOLREG */ +#define ETH_WOLREG_WOLMASK0_DEFAULT (_ETH_WOLREG_WOLMASK0_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_WOLREG */ +#define ETH_WOLREG_WOLMASK1 (0x1UL << 17) /**< Wake on LAN ARP request event enable */ +#define _ETH_WOLREG_WOLMASK1_SHIFT 17 /**< Shift value for ETH_WOLMASK1 */ +#define _ETH_WOLREG_WOLMASK1_MASK 0x20000UL /**< Bit mask for ETH_WOLMASK1 */ +#define _ETH_WOLREG_WOLMASK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_WOLREG */ +#define ETH_WOLREG_WOLMASK1_DEFAULT (_ETH_WOLREG_WOLMASK1_DEFAULT << 17) /**< Shifted mode DEFAULT for ETH_WOLREG */ +#define ETH_WOLREG_WOLMASK2 (0x1UL << 18) /**< Wake on LAN specific address register 1 event enable */ +#define _ETH_WOLREG_WOLMASK2_SHIFT 18 /**< Shift value for ETH_WOLMASK2 */ +#define _ETH_WOLREG_WOLMASK2_MASK 0x40000UL /**< Bit mask for ETH_WOLMASK2 */ +#define _ETH_WOLREG_WOLMASK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_WOLREG */ +#define ETH_WOLREG_WOLMASK2_DEFAULT (_ETH_WOLREG_WOLMASK2_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_WOLREG */ +#define ETH_WOLREG_WOLMASK3 (0x1UL << 19) /**< Wake on LAN multicast hash event enable */ +#define _ETH_WOLREG_WOLMASK3_SHIFT 19 /**< Shift value for ETH_WOLMASK3 */ +#define _ETH_WOLREG_WOLMASK3_MASK 0x80000UL /**< Bit mask for ETH_WOLMASK3 */ +#define _ETH_WOLREG_WOLMASK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_WOLREG */ +#define ETH_WOLREG_WOLMASK3_DEFAULT (_ETH_WOLREG_WOLMASK3_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_WOLREG */ + +/* Bit fields for ETH STRETCHRATIO */ +#define _ETH_STRETCHRATIO_RESETVALUE 0x00000000UL /**< Default value for ETH_STRETCHRATIO */ +#define _ETH_STRETCHRATIO_MASK 0x0000FFFFUL /**< Mask for ETH_STRETCHRATIO */ +#define _ETH_STRETCHRATIO_IPGSTRETCH_SHIFT 0 /**< Shift value for ETH_IPGSTRETCH */ +#define _ETH_STRETCHRATIO_IPGSTRETCH_MASK 0xFFFFUL /**< Bit mask for ETH_IPGSTRETCH */ +#define _ETH_STRETCHRATIO_IPGSTRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_STRETCHRATIO */ +#define ETH_STRETCHRATIO_IPGSTRETCH_DEFAULT (_ETH_STRETCHRATIO_IPGSTRETCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_STRETCHRATIO */ + +/* Bit fields for ETH STACKEDVLAN */ +#define _ETH_STACKEDVLAN_RESETVALUE 0x00000000UL /**< Default value for ETH_STACKEDVLAN */ +#define _ETH_STACKEDVLAN_MASK 0x8000FFFFUL /**< Mask for ETH_STACKEDVLAN */ +#define _ETH_STACKEDVLAN_MATCH_SHIFT 0 /**< Shift value for ETH_MATCH */ +#define _ETH_STACKEDVLAN_MATCH_MASK 0xFFFFUL /**< Bit mask for ETH_MATCH */ +#define _ETH_STACKEDVLAN_MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_STACKEDVLAN */ +#define ETH_STACKEDVLAN_MATCH_DEFAULT (_ETH_STACKEDVLAN_MATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_STACKEDVLAN */ +#define ETH_STACKEDVLAN_ENBPROCESSING (0x1UL << 31) /**< Enable stacked VLAN processing mode */ +#define _ETH_STACKEDVLAN_ENBPROCESSING_SHIFT 31 /**< Shift value for ETH_ENBPROCESSING */ +#define _ETH_STACKEDVLAN_ENBPROCESSING_MASK 0x80000000UL /**< Bit mask for ETH_ENBPROCESSING */ +#define _ETH_STACKEDVLAN_ENBPROCESSING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_STACKEDVLAN */ +#define ETH_STACKEDVLAN_ENBPROCESSING_DEFAULT (_ETH_STACKEDVLAN_ENBPROCESSING_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_STACKEDVLAN */ + +/* Bit fields for ETH TXPFCPAUSE */ +#define _ETH_TXPFCPAUSE_RESETVALUE 0x00000000UL /**< Default value for ETH_TXPFCPAUSE */ +#define _ETH_TXPFCPAUSE_MASK 0x0000FFFFUL /**< Mask for ETH_TXPFCPAUSE */ +#define _ETH_TXPFCPAUSE_VECTORENB_SHIFT 0 /**< Shift value for ETH_VECTORENB */ +#define _ETH_TXPFCPAUSE_VECTORENB_MASK 0xFFUL /**< Bit mask for ETH_VECTORENB */ +#define _ETH_TXPFCPAUSE_VECTORENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXPFCPAUSE */ +#define ETH_TXPFCPAUSE_VECTORENB_DEFAULT (_ETH_TXPFCPAUSE_VECTORENB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPFCPAUSE */ +#define _ETH_TXPFCPAUSE_VECTOR_SHIFT 8 /**< Shift value for ETH_VECTOR */ +#define _ETH_TXPFCPAUSE_VECTOR_MASK 0xFF00UL /**< Bit mask for ETH_VECTOR */ +#define _ETH_TXPFCPAUSE_VECTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXPFCPAUSE */ +#define ETH_TXPFCPAUSE_VECTOR_DEFAULT (_ETH_TXPFCPAUSE_VECTOR_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_TXPFCPAUSE */ + +/* Bit fields for ETH MASKADD1BOTTOM */ +#define _ETH_MASKADD1BOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_MASKADD1BOTTOM */ +#define _ETH_MASKADD1BOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_MASKADD1BOTTOM */ +#define _ETH_MASKADD1BOTTOM_ADDRMASK_SHIFT 0 /**< Shift value for ETH_ADDRMASK */ +#define _ETH_MASKADD1BOTTOM_ADDRMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDRMASK */ +#define _ETH_MASKADD1BOTTOM_ADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_MASKADD1BOTTOM */ +#define ETH_MASKADD1BOTTOM_ADDRMASK_DEFAULT (_ETH_MASKADD1BOTTOM_ADDRMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_MASKADD1BOTTOM */ + +/* Bit fields for ETH MASKADD1TOP */ +#define _ETH_MASKADD1TOP_RESETVALUE 0x00000000UL /**< Default value for ETH_MASKADD1TOP */ +#define _ETH_MASKADD1TOP_MASK 0x0000FFFFUL /**< Mask for ETH_MASKADD1TOP */ +#define _ETH_MASKADD1TOP_ADDRMASK_SHIFT 0 /**< Shift value for ETH_ADDRMASK */ +#define _ETH_MASKADD1TOP_ADDRMASK_MASK 0xFFFFUL /**< Bit mask for ETH_ADDRMASK */ +#define _ETH_MASKADD1TOP_ADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_MASKADD1TOP */ +#define ETH_MASKADD1TOP_ADDRMASK_DEFAULT (_ETH_MASKADD1TOP_ADDRMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_MASKADD1TOP */ + +/* Bit fields for ETH RXPTPUNICAST */ +#define _ETH_RXPTPUNICAST_RESETVALUE 0x00000000UL /**< Default value for ETH_RXPTPUNICAST */ +#define _ETH_RXPTPUNICAST_MASK 0xFFFFFFFFUL /**< Mask for ETH_RXPTPUNICAST */ +#define _ETH_RXPTPUNICAST_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_RXPTPUNICAST_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_RXPTPUNICAST_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXPTPUNICAST */ +#define ETH_RXPTPUNICAST_ADDR_DEFAULT (_ETH_RXPTPUNICAST_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXPTPUNICAST */ + +/* Bit fields for ETH TXPTPUNICAST */ +#define _ETH_TXPTPUNICAST_RESETVALUE 0x00000000UL /**< Default value for ETH_TXPTPUNICAST */ +#define _ETH_TXPTPUNICAST_MASK 0xFFFFFFFFUL /**< Mask for ETH_TXPTPUNICAST */ +#define _ETH_TXPTPUNICAST_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ +#define _ETH_TXPTPUNICAST_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ +#define _ETH_TXPTPUNICAST_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXPTPUNICAST */ +#define ETH_TXPTPUNICAST_ADDR_DEFAULT (_ETH_TXPTPUNICAST_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPTPUNICAST */ + +/* Bit fields for ETH TSUNSECCMP */ +#define _ETH_TSUNSECCMP_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUNSECCMP */ +#define _ETH_TSUNSECCMP_MASK 0x003FFFFFUL /**< Mask for ETH_TSUNSECCMP */ +#define _ETH_TSUNSECCMP_COMPVAL_SHIFT 0 /**< Shift value for ETH_COMPVAL */ +#define _ETH_TSUNSECCMP_COMPVAL_MASK 0x3FFFFFUL /**< Bit mask for ETH_COMPVAL */ +#define _ETH_TSUNSECCMP_COMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUNSECCMP */ +#define ETH_TSUNSECCMP_COMPVAL_DEFAULT (_ETH_TSUNSECCMP_COMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUNSECCMP */ + +/* Bit fields for ETH TSUSECCMP */ +#define _ETH_TSUSECCMP_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUSECCMP */ +#define _ETH_TSUSECCMP_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUSECCMP */ +#define _ETH_TSUSECCMP_COMPVAL_SHIFT 0 /**< Shift value for ETH_COMPVAL */ +#define _ETH_TSUSECCMP_COMPVAL_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COMPVAL */ +#define _ETH_TSUSECCMP_COMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUSECCMP */ +#define ETH_TSUSECCMP_COMPVAL_DEFAULT (_ETH_TSUSECCMP_COMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUSECCMP */ + +/* Bit fields for ETH TSUMSBSECCMP */ +#define _ETH_TSUMSBSECCMP_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUMSBSECCMP */ +#define _ETH_TSUMSBSECCMP_MASK 0x0000FFFFUL /**< Mask for ETH_TSUMSBSECCMP */ +#define _ETH_TSUMSBSECCMP_COMPVAL_SHIFT 0 /**< Shift value for ETH_COMPVAL */ +#define _ETH_TSUMSBSECCMP_COMPVAL_MASK 0xFFFFUL /**< Bit mask for ETH_COMPVAL */ +#define _ETH_TSUMSBSECCMP_COMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUMSBSECCMP */ +#define ETH_TSUMSBSECCMP_COMPVAL_DEFAULT (_ETH_TSUMSBSECCMP_COMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUMSBSECCMP */ + +/* Bit fields for ETH TSUPTPTXMSBSEC */ +#define _ETH_TSUPTPTXMSBSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPTXMSBSEC */ +#define _ETH_TSUPTPTXMSBSEC_MASK 0x0000FFFFUL /**< Mask for ETH_TSUPTPTXMSBSEC */ +#define _ETH_TSUPTPTXMSBSEC_TIMERSEC_SHIFT 0 /**< Shift value for ETH_TIMERSEC */ +#define _ETH_TSUPTPTXMSBSEC_TIMERSEC_MASK 0xFFFFUL /**< Bit mask for ETH_TIMERSEC */ +#define _ETH_TSUPTPTXMSBSEC_TIMERSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPTXMSBSEC */ +#define ETH_TSUPTPTXMSBSEC_TIMERSEC_DEFAULT (_ETH_TSUPTPTXMSBSEC_TIMERSEC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPTXMSBSEC */ + +/* Bit fields for ETH TSUPTPRXMSBSEC */ +#define _ETH_TSUPTPRXMSBSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPRXMSBSEC */ +#define _ETH_TSUPTPRXMSBSEC_MASK 0x0000FFFFUL /**< Mask for ETH_TSUPTPRXMSBSEC */ +#define _ETH_TSUPTPRXMSBSEC_TIMERSEC_SHIFT 0 /**< Shift value for ETH_TIMERSEC */ +#define _ETH_TSUPTPRXMSBSEC_TIMERSEC_MASK 0xFFFFUL /**< Bit mask for ETH_TIMERSEC */ +#define _ETH_TSUPTPRXMSBSEC_TIMERSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPRXMSBSEC */ +#define ETH_TSUPTPRXMSBSEC_TIMERSEC_DEFAULT (_ETH_TSUPTPRXMSBSEC_TIMERSEC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPRXMSBSEC */ + +/* Bit fields for ETH TSUPEERTXMSBSEC */ +#define _ETH_TSUPEERTXMSBSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERTXMSBSEC */ +#define _ETH_TSUPEERTXMSBSEC_MASK 0x0000FFFFUL /**< Mask for ETH_TSUPEERTXMSBSEC */ +#define _ETH_TSUPEERTXMSBSEC_TIMERSEC_SHIFT 0 /**< Shift value for ETH_TIMERSEC */ +#define _ETH_TSUPEERTXMSBSEC_TIMERSEC_MASK 0xFFFFUL /**< Bit mask for ETH_TIMERSEC */ +#define _ETH_TSUPEERTXMSBSEC_TIMERSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERTXMSBSEC */ +#define ETH_TSUPEERTXMSBSEC_TIMERSEC_DEFAULT (_ETH_TSUPEERTXMSBSEC_TIMERSEC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERTXMSBSEC */ + +/* Bit fields for ETH TSUPEERRXMSBSEC */ +#define _ETH_TSUPEERRXMSBSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERRXMSBSEC */ +#define _ETH_TSUPEERRXMSBSEC_MASK 0x0000FFFFUL /**< Mask for ETH_TSUPEERRXMSBSEC */ +#define _ETH_TSUPEERRXMSBSEC_TIMERSEC_SHIFT 0 /**< Shift value for ETH_TIMERSEC */ +#define _ETH_TSUPEERRXMSBSEC_TIMERSEC_MASK 0xFFFFUL /**< Bit mask for ETH_TIMERSEC */ +#define _ETH_TSUPEERRXMSBSEC_TIMERSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERRXMSBSEC */ +#define ETH_TSUPEERRXMSBSEC_TIMERSEC_DEFAULT (_ETH_TSUPEERRXMSBSEC_TIMERSEC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERRXMSBSEC */ + +/* Bit fields for ETH OCTETSTXEDBOTTOM */ +#define _ETH_OCTETSTXEDBOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_OCTETSTXEDBOTTOM */ +#define _ETH_OCTETSTXEDBOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_OCTETSTXEDBOTTOM */ +#define _ETH_OCTETSTXEDBOTTOM_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_OCTETSTXEDBOTTOM_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_OCTETSTXEDBOTTOM_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_OCTETSTXEDBOTTOM */ +#define ETH_OCTETSTXEDBOTTOM_COUNT_DEFAULT (_ETH_OCTETSTXEDBOTTOM_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_OCTETSTXEDBOTTOM */ + +/* Bit fields for ETH OCTETSTXEDTOP */ +#define _ETH_OCTETSTXEDTOP_RESETVALUE 0x00000000UL /**< Default value for ETH_OCTETSTXEDTOP */ +#define _ETH_OCTETSTXEDTOP_MASK 0x0000FFFFUL /**< Mask for ETH_OCTETSTXEDTOP */ +#define _ETH_OCTETSTXEDTOP_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_OCTETSTXEDTOP_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_OCTETSTXEDTOP_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_OCTETSTXEDTOP */ +#define ETH_OCTETSTXEDTOP_COUNT_DEFAULT (_ETH_OCTETSTXEDTOP_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_OCTETSTXEDTOP */ + +/* Bit fields for ETH FRAMESTXEDOK */ +#define _ETH_FRAMESTXEDOK_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXEDOK */ +#define _ETH_FRAMESTXEDOK_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXEDOK */ +#define _ETH_FRAMESTXEDOK_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESTXEDOK_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESTXEDOK_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXEDOK */ +#define ETH_FRAMESTXEDOK_COUNT_DEFAULT (_ETH_FRAMESTXEDOK_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXEDOK */ + +/* Bit fields for ETH BROADCASTTXED */ +#define _ETH_BROADCASTTXED_RESETVALUE 0x00000000UL /**< Default value for ETH_BROADCASTTXED */ +#define _ETH_BROADCASTTXED_MASK 0xFFFFFFFFUL /**< Mask for ETH_BROADCASTTXED */ +#define _ETH_BROADCASTTXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_BROADCASTTXED_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_BROADCASTTXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_BROADCASTTXED */ +#define ETH_BROADCASTTXED_COUNT_DEFAULT (_ETH_BROADCASTTXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_BROADCASTTXED */ + +/* Bit fields for ETH MULTICASTTXED */ +#define _ETH_MULTICASTTXED_RESETVALUE 0x00000000UL /**< Default value for ETH_MULTICASTTXED */ +#define _ETH_MULTICASTTXED_MASK 0xFFFFFFFFUL /**< Mask for ETH_MULTICASTTXED */ +#define _ETH_MULTICASTTXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_MULTICASTTXED_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_MULTICASTTXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_MULTICASTTXED */ +#define ETH_MULTICASTTXED_COUNT_DEFAULT (_ETH_MULTICASTTXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_MULTICASTTXED */ + +/* Bit fields for ETH PFRAMESTXED */ +#define _ETH_PFRAMESTXED_RESETVALUE 0x00000000UL /**< Default value for ETH_PFRAMESTXED */ +#define _ETH_PFRAMESTXED_MASK 0x0000FFFFUL /**< Mask for ETH_PFRAMESTXED */ +#define _ETH_PFRAMESTXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_PFRAMESTXED_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_PFRAMESTXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PFRAMESTXED */ +#define ETH_PFRAMESTXED_COUNT_DEFAULT (_ETH_PFRAMESTXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_PFRAMESTXED */ + +/* Bit fields for ETH FRAMESTXED64 */ +#define _ETH_FRAMESTXED64_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED64 */ +#define _ETH_FRAMESTXED64_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED64 */ +#define _ETH_FRAMESTXED64_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESTXED64_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESTXED64_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED64 */ +#define ETH_FRAMESTXED64_COUNT_DEFAULT (_ETH_FRAMESTXED64_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED64 */ + +/* Bit fields for ETH FRAMESTXED65 */ +#define _ETH_FRAMESTXED65_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED65 */ +#define _ETH_FRAMESTXED65_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED65 */ +#define _ETH_FRAMESTXED65_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESTXED65_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESTXED65_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED65 */ +#define ETH_FRAMESTXED65_COUNT_DEFAULT (_ETH_FRAMESTXED65_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED65 */ + +/* Bit fields for ETH FRAMESTXED128 */ +#define _ETH_FRAMESTXED128_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED128 */ +#define _ETH_FRAMESTXED128_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED128 */ +#define _ETH_FRAMESTXED128_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESTXED128_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESTXED128_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED128 */ +#define ETH_FRAMESTXED128_COUNT_DEFAULT (_ETH_FRAMESTXED128_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED128 */ + +/* Bit fields for ETH FRAMESTXED256 */ +#define _ETH_FRAMESTXED256_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED256 */ +#define _ETH_FRAMESTXED256_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED256 */ +#define _ETH_FRAMESTXED256_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESTXED256_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESTXED256_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED256 */ +#define ETH_FRAMESTXED256_COUNT_DEFAULT (_ETH_FRAMESTXED256_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED256 */ + +/* Bit fields for ETH FRAMESTXED512 */ +#define _ETH_FRAMESTXED512_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED512 */ +#define _ETH_FRAMESTXED512_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED512 */ +#define _ETH_FRAMESTXED512_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESTXED512_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESTXED512_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED512 */ +#define ETH_FRAMESTXED512_COUNT_DEFAULT (_ETH_FRAMESTXED512_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED512 */ + +/* Bit fields for ETH FRAMESTXED1024 */ +#define _ETH_FRAMESTXED1024_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED1024 */ +#define _ETH_FRAMESTXED1024_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED1024 */ +#define _ETH_FRAMESTXED1024_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESTXED1024_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESTXED1024_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED1024 */ +#define ETH_FRAMESTXED1024_COUNT_DEFAULT (_ETH_FRAMESTXED1024_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED1024 */ + +/* Bit fields for ETH FRAMESTXED1519 */ +#define _ETH_FRAMESTXED1519_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED1519 */ +#define _ETH_FRAMESTXED1519_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED1519 */ +#define _ETH_FRAMESTXED1519_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESTXED1519_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESTXED1519_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED1519 */ +#define ETH_FRAMESTXED1519_COUNT_DEFAULT (_ETH_FRAMESTXED1519_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED1519 */ + +/* Bit fields for ETH TXUNDERRUNS */ +#define _ETH_TXUNDERRUNS_RESETVALUE 0x00000000UL /**< Default value for ETH_TXUNDERRUNS */ +#define _ETH_TXUNDERRUNS_MASK 0x000003FFUL /**< Mask for ETH_TXUNDERRUNS */ +#define _ETH_TXUNDERRUNS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_TXUNDERRUNS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_TXUNDERRUNS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXUNDERRUNS */ +#define ETH_TXUNDERRUNS_COUNT_DEFAULT (_ETH_TXUNDERRUNS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXUNDERRUNS */ + +/* Bit fields for ETH SINGLECOLS */ +#define _ETH_SINGLECOLS_RESETVALUE 0x00000000UL /**< Default value for ETH_SINGLECOLS */ +#define _ETH_SINGLECOLS_MASK 0x0003FFFFUL /**< Mask for ETH_SINGLECOLS */ +#define _ETH_SINGLECOLS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_SINGLECOLS_COUNT_MASK 0x3FFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_SINGLECOLS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SINGLECOLS */ +#define ETH_SINGLECOLS_COUNT_DEFAULT (_ETH_SINGLECOLS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SINGLECOLS */ + +/* Bit fields for ETH MULTICOLS */ +#define _ETH_MULTICOLS_RESETVALUE 0x00000000UL /**< Default value for ETH_MULTICOLS */ +#define _ETH_MULTICOLS_MASK 0x0003FFFFUL /**< Mask for ETH_MULTICOLS */ +#define _ETH_MULTICOLS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_MULTICOLS_COUNT_MASK 0x3FFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_MULTICOLS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_MULTICOLS */ +#define ETH_MULTICOLS_COUNT_DEFAULT (_ETH_MULTICOLS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_MULTICOLS */ + +/* Bit fields for ETH EXCESSCOLS */ +#define _ETH_EXCESSCOLS_RESETVALUE 0x00000000UL /**< Default value for ETH_EXCESSCOLS */ +#define _ETH_EXCESSCOLS_MASK 0x000003FFUL /**< Mask for ETH_EXCESSCOLS */ +#define _ETH_EXCESSCOLS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_EXCESSCOLS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_EXCESSCOLS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_EXCESSCOLS */ +#define ETH_EXCESSCOLS_COUNT_DEFAULT (_ETH_EXCESSCOLS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_EXCESSCOLS */ + +/* Bit fields for ETH LATECOLS */ +#define _ETH_LATECOLS_RESETVALUE 0x00000000UL /**< Default value for ETH_LATECOLS */ +#define _ETH_LATECOLS_MASK 0x000003FFUL /**< Mask for ETH_LATECOLS */ +#define _ETH_LATECOLS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_LATECOLS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_LATECOLS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_LATECOLS */ +#define ETH_LATECOLS_COUNT_DEFAULT (_ETH_LATECOLS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_LATECOLS */ + +/* Bit fields for ETH DEFERREDFRAMES */ +#define _ETH_DEFERREDFRAMES_RESETVALUE 0x00000000UL /**< Default value for ETH_DEFERREDFRAMES */ +#define _ETH_DEFERREDFRAMES_MASK 0x0003FFFFUL /**< Mask for ETH_DEFERREDFRAMES */ +#define _ETH_DEFERREDFRAMES_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_DEFERREDFRAMES_COUNT_MASK 0x3FFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_DEFERREDFRAMES_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DEFERREDFRAMES */ +#define ETH_DEFERREDFRAMES_COUNT_DEFAULT (_ETH_DEFERREDFRAMES_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_DEFERREDFRAMES */ + +/* Bit fields for ETH CRSERRS */ +#define _ETH_CRSERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_CRSERRS */ +#define _ETH_CRSERRS_MASK 0x000003FFUL /**< Mask for ETH_CRSERRS */ +#define _ETH_CRSERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_CRSERRS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_CRSERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CRSERRS */ +#define ETH_CRSERRS_COUNT_DEFAULT (_ETH_CRSERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_CRSERRS */ + +/* Bit fields for ETH OCTETSRXEDBOTTOM */ +#define _ETH_OCTETSRXEDBOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_OCTETSRXEDBOTTOM */ +#define _ETH_OCTETSRXEDBOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_OCTETSRXEDBOTTOM */ +#define _ETH_OCTETSRXEDBOTTOM_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_OCTETSRXEDBOTTOM_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_OCTETSRXEDBOTTOM_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_OCTETSRXEDBOTTOM */ +#define ETH_OCTETSRXEDBOTTOM_COUNT_DEFAULT (_ETH_OCTETSRXEDBOTTOM_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_OCTETSRXEDBOTTOM */ + +/* Bit fields for ETH OCTETSRXEDTOP */ +#define _ETH_OCTETSRXEDTOP_RESETVALUE 0x00000000UL /**< Default value for ETH_OCTETSRXEDTOP */ +#define _ETH_OCTETSRXEDTOP_MASK 0x0000FFFFUL /**< Mask for ETH_OCTETSRXEDTOP */ +#define _ETH_OCTETSRXEDTOP_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_OCTETSRXEDTOP_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_OCTETSRXEDTOP_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_OCTETSRXEDTOP */ +#define ETH_OCTETSRXEDTOP_COUNT_DEFAULT (_ETH_OCTETSRXEDTOP_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_OCTETSRXEDTOP */ + +/* Bit fields for ETH FRAMESRXEDOK */ +#define _ETH_FRAMESRXEDOK_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXEDOK */ +#define _ETH_FRAMESRXEDOK_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXEDOK */ +#define _ETH_FRAMESRXEDOK_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESRXEDOK_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESRXEDOK_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXEDOK */ +#define ETH_FRAMESRXEDOK_COUNT_DEFAULT (_ETH_FRAMESRXEDOK_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXEDOK */ + +/* Bit fields for ETH BROADCASTRXED */ +#define _ETH_BROADCASTRXED_RESETVALUE 0x00000000UL /**< Default value for ETH_BROADCASTRXED */ +#define _ETH_BROADCASTRXED_MASK 0xFFFFFFFFUL /**< Mask for ETH_BROADCASTRXED */ +#define _ETH_BROADCASTRXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_BROADCASTRXED_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_BROADCASTRXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_BROADCASTRXED */ +#define ETH_BROADCASTRXED_COUNT_DEFAULT (_ETH_BROADCASTRXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_BROADCASTRXED */ + +/* Bit fields for ETH MULTICASTRXED */ +#define _ETH_MULTICASTRXED_RESETVALUE 0x00000000UL /**< Default value for ETH_MULTICASTRXED */ +#define _ETH_MULTICASTRXED_MASK 0xFFFFFFFFUL /**< Mask for ETH_MULTICASTRXED */ +#define _ETH_MULTICASTRXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_MULTICASTRXED_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_MULTICASTRXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_MULTICASTRXED */ +#define ETH_MULTICASTRXED_COUNT_DEFAULT (_ETH_MULTICASTRXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_MULTICASTRXED */ + +/* Bit fields for ETH PFRAMESRXED */ +#define _ETH_PFRAMESRXED_RESETVALUE 0x00000000UL /**< Default value for ETH_PFRAMESRXED */ +#define _ETH_PFRAMESRXED_MASK 0x0000FFFFUL /**< Mask for ETH_PFRAMESRXED */ +#define _ETH_PFRAMESRXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_PFRAMESRXED_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_PFRAMESRXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PFRAMESRXED */ +#define ETH_PFRAMESRXED_COUNT_DEFAULT (_ETH_PFRAMESRXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_PFRAMESRXED */ + +/* Bit fields for ETH FRAMESRXED64 */ +#define _ETH_FRAMESRXED64_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED64 */ +#define _ETH_FRAMESRXED64_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED64 */ +#define _ETH_FRAMESRXED64_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESRXED64_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESRXED64_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED64 */ +#define ETH_FRAMESRXED64_COUNT_DEFAULT (_ETH_FRAMESRXED64_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED64 */ + +/* Bit fields for ETH FRAMESRXED65 */ +#define _ETH_FRAMESRXED65_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED65 */ +#define _ETH_FRAMESRXED65_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED65 */ +#define _ETH_FRAMESRXED65_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESRXED65_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESRXED65_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED65 */ +#define ETH_FRAMESRXED65_COUNT_DEFAULT (_ETH_FRAMESRXED65_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED65 */ + +/* Bit fields for ETH FRAMESRXED128 */ +#define _ETH_FRAMESRXED128_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED128 */ +#define _ETH_FRAMESRXED128_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED128 */ +#define _ETH_FRAMESRXED128_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESRXED128_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESRXED128_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED128 */ +#define ETH_FRAMESRXED128_COUNT_DEFAULT (_ETH_FRAMESRXED128_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED128 */ + +/* Bit fields for ETH FRAMESRXED256 */ +#define _ETH_FRAMESRXED256_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED256 */ +#define _ETH_FRAMESRXED256_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED256 */ +#define _ETH_FRAMESRXED256_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESRXED256_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESRXED256_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED256 */ +#define ETH_FRAMESRXED256_COUNT_DEFAULT (_ETH_FRAMESRXED256_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED256 */ + +/* Bit fields for ETH FRAMESRXED512 */ +#define _ETH_FRAMESRXED512_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED512 */ +#define _ETH_FRAMESRXED512_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED512 */ +#define _ETH_FRAMESRXED512_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESRXED512_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESRXED512_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED512 */ +#define ETH_FRAMESRXED512_COUNT_DEFAULT (_ETH_FRAMESRXED512_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED512 */ + +/* Bit fields for ETH FRAMESRXED1024 */ +#define _ETH_FRAMESRXED1024_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED1024 */ +#define _ETH_FRAMESRXED1024_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED1024 */ +#define _ETH_FRAMESRXED1024_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESRXED1024_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESRXED1024_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED1024 */ +#define ETH_FRAMESRXED1024_COUNT_DEFAULT (_ETH_FRAMESRXED1024_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED1024 */ + +/* Bit fields for ETH FRAMESRXED1519 */ +#define _ETH_FRAMESRXED1519_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED1519 */ +#define _ETH_FRAMESRXED1519_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED1519 */ +#define _ETH_FRAMESRXED1519_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FRAMESRXED1519_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FRAMESRXED1519_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED1519 */ +#define ETH_FRAMESRXED1519_COUNT_DEFAULT (_ETH_FRAMESRXED1519_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED1519 */ + +/* Bit fields for ETH UNDERSIZEFRAMES */ +#define _ETH_UNDERSIZEFRAMES_RESETVALUE 0x00000000UL /**< Default value for ETH_UNDERSIZEFRAMES */ +#define _ETH_UNDERSIZEFRAMES_MASK 0x000003FFUL /**< Mask for ETH_UNDERSIZEFRAMES */ +#define _ETH_UNDERSIZEFRAMES_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_UNDERSIZEFRAMES_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_UNDERSIZEFRAMES_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_UNDERSIZEFRAMES */ +#define ETH_UNDERSIZEFRAMES_COUNT_DEFAULT (_ETH_UNDERSIZEFRAMES_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_UNDERSIZEFRAMES */ + +/* Bit fields for ETH EXCESSIVERXLEN */ +#define _ETH_EXCESSIVERXLEN_RESETVALUE 0x00000000UL /**< Default value for ETH_EXCESSIVERXLEN */ +#define _ETH_EXCESSIVERXLEN_MASK 0x000003FFUL /**< Mask for ETH_EXCESSIVERXLEN */ +#define _ETH_EXCESSIVERXLEN_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_EXCESSIVERXLEN_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_EXCESSIVERXLEN_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_EXCESSIVERXLEN */ +#define ETH_EXCESSIVERXLEN_COUNT_DEFAULT (_ETH_EXCESSIVERXLEN_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_EXCESSIVERXLEN */ + +/* Bit fields for ETH RXJABBERS */ +#define _ETH_RXJABBERS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXJABBERS */ +#define _ETH_RXJABBERS_MASK 0x000003FFUL /**< Mask for ETH_RXJABBERS */ +#define _ETH_RXJABBERS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_RXJABBERS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_RXJABBERS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXJABBERS */ +#define ETH_RXJABBERS_COUNT_DEFAULT (_ETH_RXJABBERS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXJABBERS */ + +/* Bit fields for ETH FCSERRS */ +#define _ETH_FCSERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_FCSERRS */ +#define _ETH_FCSERRS_MASK 0x000003FFUL /**< Mask for ETH_FCSERRS */ +#define _ETH_FCSERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_FCSERRS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_FCSERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FCSERRS */ +#define ETH_FCSERRS_COUNT_DEFAULT (_ETH_FCSERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FCSERRS */ + +/* Bit fields for ETH RXLENERRS */ +#define _ETH_RXLENERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXLENERRS */ +#define _ETH_RXLENERRS_MASK 0x000003FFUL /**< Mask for ETH_RXLENERRS */ +#define _ETH_RXLENERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_RXLENERRS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_RXLENERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXLENERRS */ +#define ETH_RXLENERRS_COUNT_DEFAULT (_ETH_RXLENERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXLENERRS */ + +/* Bit fields for ETH RXSYMBOLERRS */ +#define _ETH_RXSYMBOLERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXSYMBOLERRS */ +#define _ETH_RXSYMBOLERRS_MASK 0x000003FFUL /**< Mask for ETH_RXSYMBOLERRS */ +#define _ETH_RXSYMBOLERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_RXSYMBOLERRS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_RXSYMBOLERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXSYMBOLERRS */ +#define ETH_RXSYMBOLERRS_COUNT_DEFAULT (_ETH_RXSYMBOLERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXSYMBOLERRS */ + +/* Bit fields for ETH ALIGNERRS */ +#define _ETH_ALIGNERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_ALIGNERRS */ +#define _ETH_ALIGNERRS_MASK 0x000003FFUL /**< Mask for ETH_ALIGNERRS */ +#define _ETH_ALIGNERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_ALIGNERRS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_ALIGNERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ALIGNERRS */ +#define ETH_ALIGNERRS_COUNT_DEFAULT (_ETH_ALIGNERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_ALIGNERRS */ + +/* Bit fields for ETH RXRESOURCEERRS */ +#define _ETH_RXRESOURCEERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXRESOURCEERRS */ +#define _ETH_RXRESOURCEERRS_MASK 0x0003FFFFUL /**< Mask for ETH_RXRESOURCEERRS */ +#define _ETH_RXRESOURCEERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_RXRESOURCEERRS_COUNT_MASK 0x3FFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_RXRESOURCEERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXRESOURCEERRS */ +#define ETH_RXRESOURCEERRS_COUNT_DEFAULT (_ETH_RXRESOURCEERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXRESOURCEERRS */ + +/* Bit fields for ETH RXOVERRUNS */ +#define _ETH_RXOVERRUNS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXOVERRUNS */ +#define _ETH_RXOVERRUNS_MASK 0x000003FFUL /**< Mask for ETH_RXOVERRUNS */ +#define _ETH_RXOVERRUNS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_RXOVERRUNS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_RXOVERRUNS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXOVERRUNS */ +#define ETH_RXOVERRUNS_COUNT_DEFAULT (_ETH_RXOVERRUNS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXOVERRUNS */ + +/* Bit fields for ETH RXIPCKERRS */ +#define _ETH_RXIPCKERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXIPCKERRS */ +#define _ETH_RXIPCKERRS_MASK 0x000000FFUL /**< Mask for ETH_RXIPCKERRS */ +#define _ETH_RXIPCKERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_RXIPCKERRS_COUNT_MASK 0xFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_RXIPCKERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXIPCKERRS */ +#define ETH_RXIPCKERRS_COUNT_DEFAULT (_ETH_RXIPCKERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXIPCKERRS */ + +/* Bit fields for ETH RXTCPCKERRS */ +#define _ETH_RXTCPCKERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXTCPCKERRS */ +#define _ETH_RXTCPCKERRS_MASK 0x000000FFUL /**< Mask for ETH_RXTCPCKERRS */ +#define _ETH_RXTCPCKERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_RXTCPCKERRS_COUNT_MASK 0xFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_RXTCPCKERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXTCPCKERRS */ +#define ETH_RXTCPCKERRS_COUNT_DEFAULT (_ETH_RXTCPCKERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXTCPCKERRS */ + +/* Bit fields for ETH RXUDPCKERRS */ +#define _ETH_RXUDPCKERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXUDPCKERRS */ +#define _ETH_RXUDPCKERRS_MASK 0x000000FFUL /**< Mask for ETH_RXUDPCKERRS */ +#define _ETH_RXUDPCKERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_RXUDPCKERRS_COUNT_MASK 0xFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_RXUDPCKERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXUDPCKERRS */ +#define ETH_RXUDPCKERRS_COUNT_DEFAULT (_ETH_RXUDPCKERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXUDPCKERRS */ + +/* Bit fields for ETH AUTOFLUSHEDPKTS */ +#define _ETH_AUTOFLUSHEDPKTS_RESETVALUE 0x00000000UL /**< Default value for ETH_AUTOFLUSHEDPKTS */ +#define _ETH_AUTOFLUSHEDPKTS_MASK 0x0000FFFFUL /**< Mask for ETH_AUTOFLUSHEDPKTS */ +#define _ETH_AUTOFLUSHEDPKTS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_AUTOFLUSHEDPKTS_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_AUTOFLUSHEDPKTS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_AUTOFLUSHEDPKTS */ +#define ETH_AUTOFLUSHEDPKTS_COUNT_DEFAULT (_ETH_AUTOFLUSHEDPKTS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_AUTOFLUSHEDPKTS */ + +/* Bit fields for ETH TSUTIMERINCRSUBNSEC */ +#define _ETH_TSUTIMERINCRSUBNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERINCRSUBNSEC */ +#define _ETH_TSUTIMERINCRSUBNSEC_MASK 0xFF00FFFFUL /**< Mask for ETH_TSUTIMERINCRSUBNSEC */ +#define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCR_SHIFT 0 /**< Shift value for ETH_SUBNSINCR */ +#define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCR_MASK 0xFFFFUL /**< Bit mask for ETH_SUBNSINCR */ +#define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERINCRSUBNSEC */ +#define ETH_TSUTIMERINCRSUBNSEC_SUBNSINCR_DEFAULT (_ETH_TSUTIMERINCRSUBNSEC_SUBNSINCR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERINCRSUBNSEC */ +#define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCRLSB_SHIFT 24 /**< Shift value for ETH_SUBNSINCRLSB */ +#define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCRLSB_MASK 0xFF000000UL /**< Bit mask for ETH_SUBNSINCRLSB */ +#define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCRLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERINCRSUBNSEC */ +#define ETH_TSUTIMERINCRSUBNSEC_SUBNSINCRLSB_DEFAULT (_ETH_TSUTIMERINCRSUBNSEC_SUBNSINCRLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_TSUTIMERINCRSUBNSEC */ + +/* Bit fields for ETH TSUTIMERMSBSEC */ +#define _ETH_TSUTIMERMSBSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERMSBSEC */ +#define _ETH_TSUTIMERMSBSEC_MASK 0x0000FFFFUL /**< Mask for ETH_TSUTIMERMSBSEC */ +#define _ETH_TSUTIMERMSBSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ +#define _ETH_TSUTIMERMSBSEC_TIMER_MASK 0xFFFFUL /**< Bit mask for ETH_TIMER */ +#define _ETH_TSUTIMERMSBSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERMSBSEC */ +#define ETH_TSUTIMERMSBSEC_TIMER_DEFAULT (_ETH_TSUTIMERMSBSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERMSBSEC */ + +/* Bit fields for ETH TSUTIMERSEC */ +#define _ETH_TSUTIMERSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERSEC */ +#define _ETH_TSUTIMERSEC_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUTIMERSEC */ +#define _ETH_TSUTIMERSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ +#define _ETH_TSUTIMERSEC_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_TIMER */ +#define _ETH_TSUTIMERSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERSEC */ +#define ETH_TSUTIMERSEC_TIMER_DEFAULT (_ETH_TSUTIMERSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERSEC */ + +/* Bit fields for ETH TSUTIMERNSEC */ +#define _ETH_TSUTIMERNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERNSEC */ +#define _ETH_TSUTIMERNSEC_MASK 0x3FFFFFFFUL /**< Mask for ETH_TSUTIMERNSEC */ +#define _ETH_TSUTIMERNSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ +#define _ETH_TSUTIMERNSEC_TIMER_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_TIMER */ +#define _ETH_TSUTIMERNSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERNSEC */ +#define ETH_TSUTIMERNSEC_TIMER_DEFAULT (_ETH_TSUTIMERNSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERNSEC */ + +/* Bit fields for ETH TSUTIMERADJUST */ +#define _ETH_TSUTIMERADJUST_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERADJUST */ +#define _ETH_TSUTIMERADJUST_MASK 0xBFFFFFFFUL /**< Mask for ETH_TSUTIMERADJUST */ +#define _ETH_TSUTIMERADJUST_INCREMENTVAL_SHIFT 0 /**< Shift value for ETH_INCREMENTVAL */ +#define _ETH_TSUTIMERADJUST_INCREMENTVAL_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_INCREMENTVAL */ +#define _ETH_TSUTIMERADJUST_INCREMENTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERADJUST */ +#define ETH_TSUTIMERADJUST_INCREMENTVAL_DEFAULT (_ETH_TSUTIMERADJUST_INCREMENTVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERADJUST */ +#define ETH_TSUTIMERADJUST_ADDSUBTRACT (0x1UL << 31) /**< Write as one to subtract from the 1588 timer */ +#define _ETH_TSUTIMERADJUST_ADDSUBTRACT_SHIFT 31 /**< Shift value for ETH_ADDSUBTRACT */ +#define _ETH_TSUTIMERADJUST_ADDSUBTRACT_MASK 0x80000000UL /**< Bit mask for ETH_ADDSUBTRACT */ +#define _ETH_TSUTIMERADJUST_ADDSUBTRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERADJUST */ +#define ETH_TSUTIMERADJUST_ADDSUBTRACT_DEFAULT (_ETH_TSUTIMERADJUST_ADDSUBTRACT_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_TSUTIMERADJUST */ + +/* Bit fields for ETH TSUTIMERINCR */ +#define _ETH_TSUTIMERINCR_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERINCR */ +#define _ETH_TSUTIMERINCR_MASK 0x00FFFFFFUL /**< Mask for ETH_TSUTIMERINCR */ +#define _ETH_TSUTIMERINCR_NSINCREMENT_SHIFT 0 /**< Shift value for ETH_NSINCREMENT */ +#define _ETH_TSUTIMERINCR_NSINCREMENT_MASK 0xFFUL /**< Bit mask for ETH_NSINCREMENT */ +#define _ETH_TSUTIMERINCR_NSINCREMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERINCR */ +#define ETH_TSUTIMERINCR_NSINCREMENT_DEFAULT (_ETH_TSUTIMERINCR_NSINCREMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERINCR */ +#define _ETH_TSUTIMERINCR_ALTNSINCR_SHIFT 8 /**< Shift value for ETH_ALTNSINCR */ +#define _ETH_TSUTIMERINCR_ALTNSINCR_MASK 0xFF00UL /**< Bit mask for ETH_ALTNSINCR */ +#define _ETH_TSUTIMERINCR_ALTNSINCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERINCR */ +#define ETH_TSUTIMERINCR_ALTNSINCR_DEFAULT (_ETH_TSUTIMERINCR_ALTNSINCR_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_TSUTIMERINCR */ +#define _ETH_TSUTIMERINCR_NUMINCS_SHIFT 16 /**< Shift value for ETH_NUMINCS */ +#define _ETH_TSUTIMERINCR_NUMINCS_MASK 0xFF0000UL /**< Bit mask for ETH_NUMINCS */ +#define _ETH_TSUTIMERINCR_NUMINCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERINCR */ +#define ETH_TSUTIMERINCR_NUMINCS_DEFAULT (_ETH_TSUTIMERINCR_NUMINCS_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_TSUTIMERINCR */ + +/* Bit fields for ETH TSUPTPTXSEC */ +#define _ETH_TSUPTPTXSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPTXSEC */ +#define _ETH_TSUPTPTXSEC_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUPTPTXSEC */ +#define _ETH_TSUPTPTXSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ +#define _ETH_TSUPTPTXSEC_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_TIMER */ +#define _ETH_TSUPTPTXSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPTXSEC */ +#define ETH_TSUPTPTXSEC_TIMER_DEFAULT (_ETH_TSUPTPTXSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPTXSEC */ + +/* Bit fields for ETH TSUPTPTXNSEC */ +#define _ETH_TSUPTPTXNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPTXNSEC */ +#define _ETH_TSUPTPTXNSEC_MASK 0x3FFFFFFFUL /**< Mask for ETH_TSUPTPTXNSEC */ +#define _ETH_TSUPTPTXNSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ +#define _ETH_TSUPTPTXNSEC_TIMER_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_TIMER */ +#define _ETH_TSUPTPTXNSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPTXNSEC */ +#define ETH_TSUPTPTXNSEC_TIMER_DEFAULT (_ETH_TSUPTPTXNSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPTXNSEC */ + +/* Bit fields for ETH TSUPTPRXSEC */ +#define _ETH_TSUPTPRXSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPRXSEC */ +#define _ETH_TSUPTPRXSEC_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUPTPRXSEC */ +#define _ETH_TSUPTPRXSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ +#define _ETH_TSUPTPRXSEC_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_TIMER */ +#define _ETH_TSUPTPRXSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPRXSEC */ +#define ETH_TSUPTPRXSEC_TIMER_DEFAULT (_ETH_TSUPTPRXSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPRXSEC */ + +/* Bit fields for ETH TSUPTPRXNSEC */ +#define _ETH_TSUPTPRXNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPRXNSEC */ +#define _ETH_TSUPTPRXNSEC_MASK 0x3FFFFFFFUL /**< Mask for ETH_TSUPTPRXNSEC */ +#define _ETH_TSUPTPRXNSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ +#define _ETH_TSUPTPRXNSEC_TIMER_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_TIMER */ +#define _ETH_TSUPTPRXNSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPRXNSEC */ +#define ETH_TSUPTPRXNSEC_TIMER_DEFAULT (_ETH_TSUPTPRXNSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPRXNSEC */ + +/* Bit fields for ETH TSUPEERTXSEC */ +#define _ETH_TSUPEERTXSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERTXSEC */ +#define _ETH_TSUPEERTXSEC_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUPEERTXSEC */ +#define _ETH_TSUPEERTXSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ +#define _ETH_TSUPEERTXSEC_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_TIMER */ +#define _ETH_TSUPEERTXSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERTXSEC */ +#define ETH_TSUPEERTXSEC_TIMER_DEFAULT (_ETH_TSUPEERTXSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERTXSEC */ + +/* Bit fields for ETH TSUPEERTXNSEC */ +#define _ETH_TSUPEERTXNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERTXNSEC */ +#define _ETH_TSUPEERTXNSEC_MASK 0x3FFFFFFFUL /**< Mask for ETH_TSUPEERTXNSEC */ +#define _ETH_TSUPEERTXNSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ +#define _ETH_TSUPEERTXNSEC_TIMER_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_TIMER */ +#define _ETH_TSUPEERTXNSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERTXNSEC */ +#define ETH_TSUPEERTXNSEC_TIMER_DEFAULT (_ETH_TSUPEERTXNSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERTXNSEC */ + +/* Bit fields for ETH TSUPEERRXSEC */ +#define _ETH_TSUPEERRXSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERRXSEC */ +#define _ETH_TSUPEERRXSEC_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUPEERRXSEC */ +#define _ETH_TSUPEERRXSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ +#define _ETH_TSUPEERRXSEC_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_TIMER */ +#define _ETH_TSUPEERRXSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERRXSEC */ +#define ETH_TSUPEERRXSEC_TIMER_DEFAULT (_ETH_TSUPEERRXSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERRXSEC */ + +/* Bit fields for ETH TSUPEERRXNSEC */ +#define _ETH_TSUPEERRXNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERRXNSEC */ +#define _ETH_TSUPEERRXNSEC_MASK 0x3FFFFFFFUL /**< Mask for ETH_TSUPEERRXNSEC */ +#define _ETH_TSUPEERRXNSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ +#define _ETH_TSUPEERRXNSEC_TIMER_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_TIMER */ +#define _ETH_TSUPEERRXNSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERRXNSEC */ +#define ETH_TSUPEERRXNSEC_TIMER_DEFAULT (_ETH_TSUPEERRXNSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERRXNSEC */ + +/* Bit fields for ETH TXPAUSEQUANT1 */ +#define _ETH_TXPAUSEQUANT1_RESETVALUE 0xFFFFFFFFUL /**< Default value for ETH_TXPAUSEQUANT1 */ +#define _ETH_TXPAUSEQUANT1_MASK 0xFFFFFFFFUL /**< Mask for ETH_TXPAUSEQUANT1 */ +#define _ETH_TXPAUSEQUANT1_QUANTP2_SHIFT 0 /**< Shift value for ETH_QUANTP2 */ +#define _ETH_TXPAUSEQUANT1_QUANTP2_MASK 0xFFFFUL /**< Bit mask for ETH_QUANTP2 */ +#define _ETH_TXPAUSEQUANT1_QUANTP2_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT1 */ +#define ETH_TXPAUSEQUANT1_QUANTP2_DEFAULT (_ETH_TXPAUSEQUANT1_QUANTP2_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT1 */ +#define _ETH_TXPAUSEQUANT1_QUANTP3_SHIFT 16 /**< Shift value for ETH_QUANTP3 */ +#define _ETH_TXPAUSEQUANT1_QUANTP3_MASK 0xFFFF0000UL /**< Bit mask for ETH_QUANTP3 */ +#define _ETH_TXPAUSEQUANT1_QUANTP3_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT1 */ +#define ETH_TXPAUSEQUANT1_QUANTP3_DEFAULT (_ETH_TXPAUSEQUANT1_QUANTP3_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT1 */ + +/* Bit fields for ETH TXPAUSEQUANT2 */ +#define _ETH_TXPAUSEQUANT2_RESETVALUE 0xFFFFFFFFUL /**< Default value for ETH_TXPAUSEQUANT2 */ +#define _ETH_TXPAUSEQUANT2_MASK 0xFFFFFFFFUL /**< Mask for ETH_TXPAUSEQUANT2 */ +#define _ETH_TXPAUSEQUANT2_QUANTP4_SHIFT 0 /**< Shift value for ETH_QUANTP4 */ +#define _ETH_TXPAUSEQUANT2_QUANTP4_MASK 0xFFFFUL /**< Bit mask for ETH_QUANTP4 */ +#define _ETH_TXPAUSEQUANT2_QUANTP4_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT2 */ +#define ETH_TXPAUSEQUANT2_QUANTP4_DEFAULT (_ETH_TXPAUSEQUANT2_QUANTP4_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT2 */ +#define _ETH_TXPAUSEQUANT2_QUANTP5_SHIFT 16 /**< Shift value for ETH_QUANTP5 */ +#define _ETH_TXPAUSEQUANT2_QUANTP5_MASK 0xFFFF0000UL /**< Bit mask for ETH_QUANTP5 */ +#define _ETH_TXPAUSEQUANT2_QUANTP5_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT2 */ +#define ETH_TXPAUSEQUANT2_QUANTP5_DEFAULT (_ETH_TXPAUSEQUANT2_QUANTP5_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT2 */ + +/* Bit fields for ETH TXPAUSEQUANT3 */ +#define _ETH_TXPAUSEQUANT3_RESETVALUE 0xFFFFFFFFUL /**< Default value for ETH_TXPAUSEQUANT3 */ +#define _ETH_TXPAUSEQUANT3_MASK 0xFFFFFFFFUL /**< Mask for ETH_TXPAUSEQUANT3 */ +#define _ETH_TXPAUSEQUANT3_QUANTP6_SHIFT 0 /**< Shift value for ETH_QUANTP6 */ +#define _ETH_TXPAUSEQUANT3_QUANTP6_MASK 0xFFFFUL /**< Bit mask for ETH_QUANTP6 */ +#define _ETH_TXPAUSEQUANT3_QUANTP6_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT3 */ +#define ETH_TXPAUSEQUANT3_QUANTP6_DEFAULT (_ETH_TXPAUSEQUANT3_QUANTP6_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT3 */ +#define _ETH_TXPAUSEQUANT3_QUANTP7_SHIFT 16 /**< Shift value for ETH_QUANTP7 */ +#define _ETH_TXPAUSEQUANT3_QUANTP7_MASK 0xFFFF0000UL /**< Bit mask for ETH_QUANTP7 */ +#define _ETH_TXPAUSEQUANT3_QUANTP7_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT3 */ +#define ETH_TXPAUSEQUANT3_QUANTP7_DEFAULT (_ETH_TXPAUSEQUANT3_QUANTP7_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT3 */ + +/* Bit fields for ETH RXLPI */ +#define _ETH_RXLPI_RESETVALUE 0x00000000UL /**< Default value for ETH_RXLPI */ +#define _ETH_RXLPI_MASK 0x0000FFFFUL /**< Mask for ETH_RXLPI */ +#define _ETH_RXLPI_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_RXLPI_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_RXLPI_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXLPI */ +#define ETH_RXLPI_COUNT_DEFAULT (_ETH_RXLPI_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXLPI */ + +/* Bit fields for ETH RXLPITIME */ +#define _ETH_RXLPITIME_RESETVALUE 0x00000000UL /**< Default value for ETH_RXLPITIME */ +#define _ETH_RXLPITIME_MASK 0x00FFFFFFUL /**< Mask for ETH_RXLPITIME */ +#define _ETH_RXLPITIME_LPITIME_SHIFT 0 /**< Shift value for ETH_LPITIME */ +#define _ETH_RXLPITIME_LPITIME_MASK 0xFFFFFFUL /**< Bit mask for ETH_LPITIME */ +#define _ETH_RXLPITIME_LPITIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXLPITIME */ +#define ETH_RXLPITIME_LPITIME_DEFAULT (_ETH_RXLPITIME_LPITIME_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXLPITIME */ + +/* Bit fields for ETH TXLPI */ +#define _ETH_TXLPI_RESETVALUE 0x00000000UL /**< Default value for ETH_TXLPI */ +#define _ETH_TXLPI_MASK 0x0000FFFFUL /**< Mask for ETH_TXLPI */ +#define _ETH_TXLPI_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ +#define _ETH_TXLPI_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ +#define _ETH_TXLPI_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXLPI */ +#define ETH_TXLPI_COUNT_DEFAULT (_ETH_TXLPI_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXLPI */ + +/* Bit fields for ETH TXLPITIME */ +#define _ETH_TXLPITIME_RESETVALUE 0x00000000UL /**< Default value for ETH_TXLPITIME */ +#define _ETH_TXLPITIME_MASK 0x00FFFFFFUL /**< Mask for ETH_TXLPITIME */ +#define _ETH_TXLPITIME_LPITIME_SHIFT 0 /**< Shift value for ETH_LPITIME */ +#define _ETH_TXLPITIME_LPITIME_MASK 0xFFFFFFUL /**< Bit mask for ETH_LPITIME */ +#define _ETH_TXLPITIME_LPITIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXLPITIME */ +#define ETH_TXLPITIME_LPITIME_DEFAULT (_ETH_TXLPITIME_LPITIME_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXLPITIME */ + +/* Bit fields for ETH TXBDCTRL */ +#define _ETH_TXBDCTRL_RESETVALUE 0x00000000UL /**< Default value for ETH_TXBDCTRL */ +#define _ETH_TXBDCTRL_MASK 0x00000030UL /**< Mask for ETH_TXBDCTRL */ +#define _ETH_TXBDCTRL_TXBDTSMODE_SHIFT 4 /**< Shift value for ETH_TXBDTSMODE */ +#define _ETH_TXBDCTRL_TXBDTSMODE_MASK 0x30UL /**< Bit mask for ETH_TXBDTSMODE */ +#define _ETH_TXBDCTRL_TXBDTSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXBDCTRL */ +#define ETH_TXBDCTRL_TXBDTSMODE_DEFAULT (_ETH_TXBDCTRL_TXBDTSMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_TXBDCTRL */ + +/* Bit fields for ETH RXBDCTRL */ +#define _ETH_RXBDCTRL_RESETVALUE 0x00000000UL /**< Default value for ETH_RXBDCTRL */ +#define _ETH_RXBDCTRL_MASK 0x00000030UL /**< Mask for ETH_RXBDCTRL */ +#define _ETH_RXBDCTRL_RXBDTSMODE_SHIFT 4 /**< Shift value for ETH_RXBDTSMODE */ +#define _ETH_RXBDCTRL_RXBDTSMODE_MASK 0x30UL /**< Bit mask for ETH_RXBDTSMODE */ +#define _ETH_RXBDCTRL_RXBDTSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXBDCTRL */ +#define ETH_RXBDCTRL_RXBDTSMODE_DEFAULT (_ETH_RXBDCTRL_RXBDTSMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_RXBDCTRL */ + +/* Bit fields for ETH ROUTEPEN */ +#define _ETH_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_MASK 0x0000003FUL /**< Mask for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MDIOPEN (0x1UL << 0) /**< MDIO I/O Enable */ +#define _ETH_ROUTEPEN_MDIOPEN_SHIFT 0 /**< Shift value for ETH_MDIOPEN */ +#define _ETH_ROUTEPEN_MDIOPEN_MASK 0x1UL /**< Bit mask for ETH_MDIOPEN */ +#define _ETH_ROUTEPEN_MDIOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_MDIOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_MDIOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MDIOPEN_DEFAULT (_ETH_ROUTEPEN_MDIOPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MDIOPEN_DISABLE (_ETH_ROUTEPEN_MDIOPEN_DISABLE << 0) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MDIOPEN_ENABLE (_ETH_ROUTEPEN_MDIOPEN_ENABLE << 0) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIITXERPEN (0x1UL << 1) /**< MII TX ER I/O Enable */ +#define _ETH_ROUTEPEN_MIITXERPEN_SHIFT 1 /**< Shift value for ETH_MIITXERPEN */ +#define _ETH_ROUTEPEN_MIITXERPEN_MASK 0x2UL /**< Bit mask for ETH_MIITXERPEN */ +#define _ETH_ROUTEPEN_MIITXERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_MIITXERPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_MIITXERPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIITXERPEN_DEFAULT (_ETH_ROUTEPEN_MIITXERPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIITXERPEN_DISABLE (_ETH_ROUTEPEN_MIITXERPEN_DISABLE << 1) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIITXERPEN_ENABLE (_ETH_ROUTEPEN_MIITXERPEN_ENABLE << 1) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIIRXERPEN (0x1UL << 2) /**< MII TX ER I/O Enable */ +#define _ETH_ROUTEPEN_MIIRXERPEN_SHIFT 2 /**< Shift value for ETH_MIIRXERPEN */ +#define _ETH_ROUTEPEN_MIIRXERPEN_MASK 0x4UL /**< Bit mask for ETH_MIIRXERPEN */ +#define _ETH_ROUTEPEN_MIIRXERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_MIIRXERPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_MIIRXERPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIIRXERPEN_DEFAULT (_ETH_ROUTEPEN_MIIRXERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIIRXERPEN_DISABLE (_ETH_ROUTEPEN_MIIRXERPEN_DISABLE << 2) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIIRXERPEN_ENABLE (_ETH_ROUTEPEN_MIIRXERPEN_ENABLE << 2) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIIPEN (0x1UL << 3) /**< MII I/O Enable */ +#define _ETH_ROUTEPEN_MIIPEN_SHIFT 3 /**< Shift value for ETH_MIIPEN */ +#define _ETH_ROUTEPEN_MIIPEN_MASK 0x8UL /**< Bit mask for ETH_MIIPEN */ +#define _ETH_ROUTEPEN_MIIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_MIIPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_MIIPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIIPEN_DEFAULT (_ETH_ROUTEPEN_MIIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIIPEN_DISABLE (_ETH_ROUTEPEN_MIIPEN_DISABLE << 3) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_MIIPEN_ENABLE (_ETH_ROUTEPEN_MIIPEN_ENABLE << 3) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_RMIIPEN (0x1UL << 4) /**< RMII I/O Enable */ +#define _ETH_ROUTEPEN_RMIIPEN_SHIFT 4 /**< Shift value for ETH_RMIIPEN */ +#define _ETH_ROUTEPEN_RMIIPEN_MASK 0x10UL /**< Bit mask for ETH_RMIIPEN */ +#define _ETH_ROUTEPEN_RMIIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_RMIIPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_RMIIPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_RMIIPEN_DEFAULT (_ETH_ROUTEPEN_RMIIPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_RMIIPEN_DISABLE (_ETH_ROUTEPEN_RMIIPEN_DISABLE << 4) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_RMIIPEN_ENABLE (_ETH_ROUTEPEN_RMIIPEN_ENABLE << 4) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_TSUTMRTOGPEN (0x1UL << 5) /**< TSU_TMR_CNT_SEC Output Enable */ +#define _ETH_ROUTEPEN_TSUTMRTOGPEN_SHIFT 5 /**< Shift value for ETH_TSUTMRTOGPEN */ +#define _ETH_ROUTEPEN_TSUTMRTOGPEN_MASK 0x20UL /**< Bit mask for ETH_TSUTMRTOGPEN */ +#define _ETH_ROUTEPEN_TSUTMRTOGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_TSUTMRTOGPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ +#define _ETH_ROUTEPEN_TSUTMRTOGPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_TSUTMRTOGPEN_DEFAULT (_ETH_ROUTEPEN_TSUTMRTOGPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_TSUTMRTOGPEN_DISABLE (_ETH_ROUTEPEN_TSUTMRTOGPEN_DISABLE << 5) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ +#define ETH_ROUTEPEN_TSUTMRTOGPEN_ENABLE (_ETH_ROUTEPEN_TSUTMRTOGPEN_ENABLE << 5) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ + +/* Bit fields for ETH ROUTELOC0 */ +#define _ETH_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MASK 0x03030301UL /**< Mask for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIITXLOC_SHIFT 0 /**< Shift value for ETH_MIITXLOC */ +#define _ETH_ROUTELOC0_MIITXLOC_MASK 0x1UL /**< Bit mask for ETH_MIITXLOC */ +#define _ETH_ROUTELOC0_MIITXLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIITXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIITXLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIITXLOC_LOC0 (_ETH_ROUTELOC0_MIITXLOC_LOC0 << 0) /**< Shifted mode LOC0 for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIITXLOC_DEFAULT (_ETH_ROUTELOC0_MIITXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIITXLOC_LOC1 (_ETH_ROUTELOC0_MIITXLOC_LOC1 << 0) /**< Shifted mode LOC1 for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIIRXLOC_SHIFT 8 /**< Shift value for ETH_MIIRXLOC */ +#define _ETH_ROUTELOC0_MIIRXLOC_MASK 0x300UL /**< Bit mask for ETH_MIIRXLOC */ +#define _ETH_ROUTELOC0_MIIRXLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIIRXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIIRXLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIIRXLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIIRXLOC_LOC0 (_ETH_ROUTELOC0_MIIRXLOC_LOC0 << 8) /**< Shifted mode LOC0 for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIIRXLOC_DEFAULT (_ETH_ROUTELOC0_MIIRXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIIRXLOC_LOC1 (_ETH_ROUTELOC0_MIIRXLOC_LOC1 << 8) /**< Shifted mode LOC1 for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIIRXLOC_LOC2 (_ETH_ROUTELOC0_MIIRXLOC_LOC2 << 8) /**< Shifted mode LOC2 for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIICRSLOC_SHIFT 16 /**< Shift value for ETH_MIICRSLOC */ +#define _ETH_ROUTELOC0_MIICRSLOC_MASK 0x30000UL /**< Bit mask for ETH_MIICRSLOC */ +#define _ETH_ROUTELOC0_MIICRSLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIICRSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIICRSLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIICRSLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIICRSLOC_LOC0 (_ETH_ROUTELOC0_MIICRSLOC_LOC0 << 16) /**< Shifted mode LOC0 for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIICRSLOC_DEFAULT (_ETH_ROUTELOC0_MIICRSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIICRSLOC_LOC1 (_ETH_ROUTELOC0_MIICRSLOC_LOC1 << 16) /**< Shifted mode LOC1 for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIICRSLOC_LOC2 (_ETH_ROUTELOC0_MIICRSLOC_LOC2 << 16) /**< Shifted mode LOC2 for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIICOLLOC_SHIFT 24 /**< Shift value for ETH_MIICOLLOC */ +#define _ETH_ROUTELOC0_MIICOLLOC_MASK 0x3000000UL /**< Bit mask for ETH_MIICOLLOC */ +#define _ETH_ROUTELOC0_MIICOLLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIICOLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIICOLLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC0 */ +#define _ETH_ROUTELOC0_MIICOLLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIICOLLOC_LOC0 (_ETH_ROUTELOC0_MIICOLLOC_LOC0 << 24) /**< Shifted mode LOC0 for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIICOLLOC_DEFAULT (_ETH_ROUTELOC0_MIICOLLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIICOLLOC_LOC1 (_ETH_ROUTELOC0_MIICOLLOC_LOC1 << 24) /**< Shifted mode LOC1 for ETH_ROUTELOC0 */ +#define ETH_ROUTELOC0_MIICOLLOC_LOC2 (_ETH_ROUTELOC0_MIICOLLOC_LOC2 << 24) /**< Shifted mode LOC2 for ETH_ROUTELOC0 */ + +/* Bit fields for ETH ROUTELOC1 */ +#define _ETH_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_MASK 0x01030303UL /**< Mask for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_TSUEXTCLKLOC_SHIFT 0 /**< Shift value for ETH_TSUEXTCLKLOC */ +#define _ETH_ROUTELOC1_TSUEXTCLKLOC_MASK 0x3UL /**< Bit mask for ETH_TSUEXTCLKLOC */ +#define _ETH_ROUTELOC1_TSUEXTCLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_TSUEXTCLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_TSUEXTCLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_TSUEXTCLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_TSUEXTCLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_TSUEXTCLKLOC_LOC0 (_ETH_ROUTELOC1_TSUEXTCLKLOC_LOC0 << 0) /**< Shifted mode LOC0 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_TSUEXTCLKLOC_DEFAULT (_ETH_ROUTELOC1_TSUEXTCLKLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_TSUEXTCLKLOC_LOC1 (_ETH_ROUTELOC1_TSUEXTCLKLOC_LOC1 << 0) /**< Shifted mode LOC1 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_TSUEXTCLKLOC_LOC2 (_ETH_ROUTELOC1_TSUEXTCLKLOC_LOC2 << 0) /**< Shifted mode LOC2 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_TSUEXTCLKLOC_LOC3 (_ETH_ROUTELOC1_TSUEXTCLKLOC_LOC3 << 0) /**< Shifted mode LOC3 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_TSUTMRTOGLOC_SHIFT 8 /**< Shift value for ETH_TSUTMRTOGLOC */ +#define _ETH_ROUTELOC1_TSUTMRTOGLOC_MASK 0x300UL /**< Bit mask for ETH_TSUTMRTOGLOC */ +#define _ETH_ROUTELOC1_TSUTMRTOGLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_TSUTMRTOGLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_TSUTMRTOGLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_TSUTMRTOGLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_TSUTMRTOGLOC_LOC3 0x00000003UL /**< Mode LOC3 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_TSUTMRTOGLOC_LOC0 (_ETH_ROUTELOC1_TSUTMRTOGLOC_LOC0 << 8) /**< Shifted mode LOC0 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_TSUTMRTOGLOC_DEFAULT (_ETH_ROUTELOC1_TSUTMRTOGLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_TSUTMRTOGLOC_LOC1 (_ETH_ROUTELOC1_TSUTMRTOGLOC_LOC1 << 8) /**< Shifted mode LOC1 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_TSUTMRTOGLOC_LOC2 (_ETH_ROUTELOC1_TSUTMRTOGLOC_LOC2 << 8) /**< Shifted mode LOC2 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_TSUTMRTOGLOC_LOC3 (_ETH_ROUTELOC1_TSUTMRTOGLOC_LOC3 << 8) /**< Shifted mode LOC3 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_MDIOLOC_SHIFT 16 /**< Shift value for ETH_MDIOLOC */ +#define _ETH_ROUTELOC1_MDIOLOC_MASK 0x30000UL /**< Bit mask for ETH_MDIOLOC */ +#define _ETH_ROUTELOC1_MDIOLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_MDIOLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_MDIOLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_MDIOLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_MDIOLOC_LOC3 0x00000003UL /**< Mode LOC3 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_MDIOLOC_LOC0 (_ETH_ROUTELOC1_MDIOLOC_LOC0 << 16) /**< Shifted mode LOC0 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_MDIOLOC_DEFAULT (_ETH_ROUTELOC1_MDIOLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_MDIOLOC_LOC1 (_ETH_ROUTELOC1_MDIOLOC_LOC1 << 16) /**< Shifted mode LOC1 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_MDIOLOC_LOC2 (_ETH_ROUTELOC1_MDIOLOC_LOC2 << 16) /**< Shifted mode LOC2 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_MDIOLOC_LOC3 (_ETH_ROUTELOC1_MDIOLOC_LOC3 << 16) /**< Shifted mode LOC3 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_RMIILOC_SHIFT 24 /**< Shift value for ETH_RMIILOC */ +#define _ETH_ROUTELOC1_RMIILOC_MASK 0x1000000UL /**< Bit mask for ETH_RMIILOC */ +#define _ETH_ROUTELOC1_RMIILOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_RMIILOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC1 */ +#define _ETH_ROUTELOC1_RMIILOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_RMIILOC_LOC0 (_ETH_ROUTELOC1_RMIILOC_LOC0 << 24) /**< Shifted mode LOC0 for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_RMIILOC_DEFAULT (_ETH_ROUTELOC1_RMIILOC_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_ROUTELOC1 */ +#define ETH_ROUTELOC1_RMIILOC_LOC1 (_ETH_ROUTELOC1_RMIILOC_LOC1 << 24) /**< Shifted mode LOC1 for ETH_ROUTELOC1 */ + +/* Bit fields for ETH CTRL */ +#define _ETH_CTRL_RESETVALUE 0x00000000UL /**< Default value for ETH_CTRL */ +#define _ETH_CTRL_MASK 0x000007F7UL /**< Mask for ETH_CTRL */ +#define _ETH_CTRL_TSUCLKSEL_SHIFT 0 /**< Shift value for ETH_TSUCLKSEL */ +#define _ETH_CTRL_TSUCLKSEL_MASK 0x7UL /**< Bit mask for ETH_TSUCLKSEL */ +#define _ETH_CTRL_TSUCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CTRL */ +#define _ETH_CTRL_TSUCLKSEL_NOCLOCK 0x00000000UL /**< Mode NOCLOCK for ETH_CTRL */ +#define _ETH_CTRL_TSUCLKSEL_PLL 0x00000001UL /**< Mode PLL for ETH_CTRL */ +#define _ETH_CTRL_TSUCLKSEL_RXCLK 0x00000002UL /**< Mode RXCLK for ETH_CTRL */ +#define _ETH_CTRL_TSUCLKSEL_REFCLK 0x00000003UL /**< Mode REFCLK for ETH_CTRL */ +#define _ETH_CTRL_TSUCLKSEL_TSUEXTCLK 0x00000004UL /**< Mode TSUEXTCLK for ETH_CTRL */ +#define ETH_CTRL_TSUCLKSEL_DEFAULT (_ETH_CTRL_TSUCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_CTRL */ +#define ETH_CTRL_TSUCLKSEL_NOCLOCK (_ETH_CTRL_TSUCLKSEL_NOCLOCK << 0) /**< Shifted mode NOCLOCK for ETH_CTRL */ +#define ETH_CTRL_TSUCLKSEL_PLL (_ETH_CTRL_TSUCLKSEL_PLL << 0) /**< Shifted mode PLL for ETH_CTRL */ +#define ETH_CTRL_TSUCLKSEL_RXCLK (_ETH_CTRL_TSUCLKSEL_RXCLK << 0) /**< Shifted mode RXCLK for ETH_CTRL */ +#define ETH_CTRL_TSUCLKSEL_REFCLK (_ETH_CTRL_TSUCLKSEL_REFCLK << 0) /**< Shifted mode REFCLK for ETH_CTRL */ +#define ETH_CTRL_TSUCLKSEL_TSUEXTCLK (_ETH_CTRL_TSUCLKSEL_TSUEXTCLK << 0) /**< Shifted mode TSUEXTCLK for ETH_CTRL */ +#define _ETH_CTRL_TSUPRESC_SHIFT 4 /**< Shift value for ETH_TSUPRESC */ +#define _ETH_CTRL_TSUPRESC_MASK 0xF0UL /**< Bit mask for ETH_TSUPRESC */ +#define _ETH_CTRL_TSUPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CTRL */ +#define ETH_CTRL_TSUPRESC_DEFAULT (_ETH_CTRL_TSUPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_CTRL */ +#define ETH_CTRL_MIISEL (0x1UL << 8) /**< MII select signal */ +#define _ETH_CTRL_MIISEL_SHIFT 8 /**< Shift value for ETH_MIISEL */ +#define _ETH_CTRL_MIISEL_MASK 0x100UL /**< Bit mask for ETH_MIISEL */ +#define _ETH_CTRL_MIISEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CTRL */ +#define _ETH_CTRL_MIISEL_RMII 0x00000000UL /**< Mode RMII for ETH_CTRL */ +#define _ETH_CTRL_MIISEL_MII 0x00000001UL /**< Mode MII for ETH_CTRL */ +#define ETH_CTRL_MIISEL_DEFAULT (_ETH_CTRL_MIISEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_CTRL */ +#define ETH_CTRL_MIISEL_RMII (_ETH_CTRL_MIISEL_RMII << 8) /**< Shifted mode RMII for ETH_CTRL */ +#define ETH_CTRL_MIISEL_MII (_ETH_CTRL_MIISEL_MII << 8) /**< Shifted mode MII for ETH_CTRL */ +#define ETH_CTRL_GBLCLKEN (0x1UL << 9) /**< Global Clock Enable signal for Ethernet clocks tsu_clk, tx_clk, rx_clk and ref_clk */ +#define _ETH_CTRL_GBLCLKEN_SHIFT 9 /**< Shift value for ETH_GBLCLKEN */ +#define _ETH_CTRL_GBLCLKEN_MASK 0x200UL /**< Bit mask for ETH_GBLCLKEN */ +#define _ETH_CTRL_GBLCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CTRL */ +#define ETH_CTRL_GBLCLKEN_DEFAULT (_ETH_CTRL_GBLCLKEN_DEFAULT << 9) /**< Shifted mode DEFAULT for ETH_CTRL */ +#define ETH_CTRL_TXREFCLKSEL (0x1UL << 10) /**< REFCLK source select for RMII_TXD and RMII_TX_EN */ +#define _ETH_CTRL_TXREFCLKSEL_SHIFT 10 /**< Shift value for ETH_TXREFCLKSEL */ +#define _ETH_CTRL_TXREFCLKSEL_MASK 0x400UL /**< Bit mask for ETH_TXREFCLKSEL */ +#define _ETH_CTRL_TXREFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CTRL */ +#define _ETH_CTRL_TXREFCLKSEL_REFCLKINT 0x00000000UL /**< Mode REFCLKINT for ETH_CTRL */ +#define _ETH_CTRL_TXREFCLKSEL_REFCLKPIN 0x00000001UL /**< Mode REFCLKPIN for ETH_CTRL */ +#define ETH_CTRL_TXREFCLKSEL_DEFAULT (_ETH_CTRL_TXREFCLKSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_CTRL */ +#define ETH_CTRL_TXREFCLKSEL_REFCLKINT (_ETH_CTRL_TXREFCLKSEL_REFCLKINT << 10) /**< Shifted mode REFCLKINT for ETH_CTRL */ +#define ETH_CTRL_TXREFCLKSEL_REFCLKPIN (_ETH_CTRL_TXREFCLKSEL_REFCLKPIN << 10) /**< Shifted mode REFCLKPIN for ETH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B_ETH */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_etm.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_etm.h new file mode 100644 index 0000000000000..9c8f0d416ca9a --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_etm.h @@ -0,0 +1,797 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_ETM register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_ETM ETM + * @{ + * @brief EFM32GG11B_ETM Register Declaration + ******************************************************************************/ +/** ETM Register Declaration */ +typedef struct { + __IOM uint32_t ETMCR; /**< Main Control Register */ + __IM uint32_t ETMCCR; /**< Configuration Code Register */ + __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ETMSR; /**< ETM Status Register */ + __IM uint32_t ETMSCR; /**< ETM System Configuration Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */ + __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */ + uint32_t RESERVED3[68U]; /**< Reserved for future use **/ + __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */ + uint32_t RESERVED4[39U]; /**< Reserved for future use **/ + __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */ + __IM uint32_t ETMIDR; /**< ID Register */ + __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use **/ + __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use **/ + __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */ + uint32_t RESERVED7[1U]; /**< Reserved for future use **/ + __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use **/ + __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */ + uint32_t RESERVED9[66U]; /**< Reserved for future use **/ + __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */ + uint32_t RESERVED10[754U]; /**< Reserved for future use **/ + __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use **/ + __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use **/ + __IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */ + uint32_t RESERVED15[39U]; /**< Reserved for future use **/ + __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */ + __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */ + uint32_t RESERVED16[2U]; /**< Reserved for future use **/ + __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */ + __IM uint32_t ETMLSR; /**< Lock Status Register */ + __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */ + uint32_t RESERVED17[4U]; /**< Reserved for future use **/ + __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */ + __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */ + __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */ + __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */ + __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */ + __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */ + __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */ + __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */ + __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */ + __IM uint32_t ETMCIDR0; /**< Component ID0 Register */ + __IM uint32_t ETMCIDR1; /**< Component ID1 Register */ + __IM uint32_t ETMCIDR2; /**< Component ID2 Register */ + __IM uint32_t ETMCIDR3; /**< Component ID3 Register */ +} ETM_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_ETM + * @{ + * @defgroup EFM32GG11B_ETM_BitFields ETM Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for ETM ETMCR */ +#define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */ +#define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */ +#define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */ +#define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */ +#define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */ +#define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */ +#define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */ +#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */ +#define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */ +#define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */ +#define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */ +#define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */ +#define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */ + +/* Bit fields for ETM ETMCCR */ +#define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */ +#define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */ +#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */ +#define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */ +#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */ +#define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */ +#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */ +#define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */ + +/* Bit fields for ETM ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ + +/* Bit fields for ETM ETMSR */ +#define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */ +#define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */ +#define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */ +#define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */ +#define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */ +#define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */ +#define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */ + +/* Bit fields for ETM ETMSCR */ +#define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */ +#define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */ +#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */ +#define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */ +#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */ +#define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */ +#define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */ +#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */ + +/* Bit fields for ETM ETMTEEVR */ +#define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ + +/* Bit fields for ETM ETMTECR1 */ +#define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */ +#define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */ +#define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */ + +/* Bit fields for ETM ETMFFLR */ +#define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */ +#define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */ +#define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */ +#define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */ + +/* Bit fields for ETM ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */ +#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */ + +/* Bit fields for ETM ETMSYNCFR */ +#define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */ +#define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */ +#define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */ +#define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */ + +/* Bit fields for ETM ETMIDR */ +#define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */ +#define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */ +#define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */ +#define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */ +#define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */ +#define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */ +#define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */ +#define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */ +#define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */ + +/* Bit fields for ETM ETMCCER */ +#define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */ +#define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */ +#define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */ +#define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */ +#define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */ +#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */ +#define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */ +#define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */ +#define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */ +#define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */ +#define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */ +#define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */ +#define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */ + +/* Bit fields for ETM ETMTESSEICR */ +#define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ + +/* Bit fields for ETM ETMTSEVR */ +#define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ + +/* Bit fields for ETM ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */ +#define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */ + +/* Bit fields for ETM ETMIDR2 */ +#define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */ +#define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */ +#define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */ + +/* Bit fields for ETM ETMPDSR */ +#define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */ +#define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */ +#define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */ +#define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */ +#define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */ + +/* Bit fields for ETM ETMISCIN */ +#define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */ +#define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */ +#define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */ +#define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ + +/* Bit fields for ETM ITTRIGOUT */ +#define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */ +#define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */ +#define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */ +#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */ + +/* Bit fields for ETM ETMITATBCTR2 */ +#define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */ +#define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */ +#define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */ +#define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */ +#define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */ + +/* Bit fields for ETM ETMITATBCTR0 */ +#define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */ +#define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */ +#define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */ +#define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */ +#define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */ + +/* Bit fields for ETM ETMITCTRL */ +#define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */ +#define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */ +#define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */ +#define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */ +#define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */ + +/* Bit fields for ETM ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */ +#define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */ + +/* Bit fields for ETM ETMCLAIMCLR */ +#define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */ +#define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */ +#define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */ +#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */ +#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */ + +/* Bit fields for ETM ETMLAR */ +#define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */ +#define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */ +#define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */ +#define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */ +#define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */ +#define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */ +#define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */ + +/* Bit fields for ETM ETMLSR */ +#define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */ +#define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */ +#define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */ +#define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */ + +/* Bit fields for ETM ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ + +/* Bit fields for ETM ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ + +/* Bit fields for ETM ETMPIDR4 */ +#define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ + +/* Bit fields for ETM ETMPIDR5 */ +#define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */ +#define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */ + +/* Bit fields for ETM ETMPIDR6 */ +#define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */ +#define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */ + +/* Bit fields for ETM ETMPIDR7 */ +#define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */ +#define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */ + +/* Bit fields for ETM ETMPIDR0 */ +#define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */ +#define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */ +#define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */ +#define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */ + +/* Bit fields for ETM ETMPIDR1 */ +#define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ + +/* Bit fields for ETM ETMPIDR2 */ +#define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */ +#define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */ +#define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */ +#define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ + +/* Bit fields for ETM ETMPIDR3 */ +#define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ + +/* Bit fields for ETM ETMCIDR0 */ +#define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */ +#define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */ +#define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */ +#define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */ + +/* Bit fields for ETM ETMCIDR1 */ +#define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */ +#define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */ +#define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */ +#define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */ + +/* Bit fields for ETM ETMCIDR2 */ +#define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */ +#define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */ +#define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */ +#define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */ + +/* Bit fields for ETM ETMCIDR3 */ +#define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */ +#define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */ +#define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */ +#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */ + +/** @} */ +/** @} End of group EFM32GG11B_ETM */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_fpueh.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_fpueh.h new file mode 100644 index 0000000000000..3d1799af340cc --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_fpueh.h @@ -0,0 +1,208 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_FPUEH register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_FPUEH FPUEH + * @{ + * @brief EFM32GG11B_FPUEH Register Declaration + ******************************************************************************/ +/** FPUEH Register Declaration */ +typedef struct { + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} FPUEH_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_FPUEH + * @{ + * @defgroup EFM32GG11B_FPUEH_BitFields FPUEH Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for FPUEH IF */ +#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */ +#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */ +#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */ +#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */ +#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */ +#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */ +#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */ +#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */ +#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */ + +/* Bit fields for FPUEH IFS */ +#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */ +#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */ +#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */ +#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */ +#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */ +#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */ +#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */ +#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */ +#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */ + +/* Bit fields for FPUEH IFC */ +#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */ +#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */ +#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */ +#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */ +#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */ +#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */ +#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */ +#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */ +#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */ + +/* Bit fields for FPUEH IEN */ +#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */ +#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */ +#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */ +#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */ +#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */ +#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */ +#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */ +#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */ +#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */ + +/** @} */ +/** @} End of group EFM32GG11B_FPUEH */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpcrc.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpcrc.h new file mode 100644 index 0000000000000..88609e22e5fb8 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpcrc.h @@ -0,0 +1,201 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_GPCRC register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_GPCRC GPCRC + * @{ + * @brief EFM32GG11B_GPCRC Register Declaration + ******************************************************************************/ +/** GPCRC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_GPCRC + * @{ + * @defgroup EFM32GG11B_GPCRC_BitFields GPCRC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */ +#define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */ +#define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} */ +/** @} End of group EFM32GG11B_GPCRC */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio.h new file mode 100644 index 0000000000000..e1124df562951 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio.h @@ -0,0 +1,1557 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_GPIO register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_GPIO GPIO + * @{ + * @brief EFM32GG11B_GPIO Register Declaration + ******************************************************************************/ +/** GPIO Register Declaration */ +typedef struct { + GPIO_P_TypeDef P[12U]; /**< Port configuration bits */ + + uint32_t RESERVED0[112U]; /**< Reserved for future use **/ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */ + __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High Register */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */ + __IOM uint32_t EXTILEVEL; /**< External Interrupt Level Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t EM4WUEN; /**< EM4 Wake Up Enable Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t INSENSE; /**< Input Sense Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ +} GPIO_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_GPIO + * @{ + * @defgroup EFM32GG11B_GPIO_BitFields GPIO Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for GPIO P_CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00500050UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10711071UL /**< Mask for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive Strength for Port */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for GPIO_DRIVESTRENGTH */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_MASK 0x1UL /**< Bit mask for GPIO_DRIVESTRENGTH */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_STRONG (_GPIO_P_CTRL_DRIVESTRENGTH_STRONG << 0) /**< Shifted mode STRONG for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_WEAK (_GPIO_P_CTRL_DRIVESTRENGTH_WEAK << 0) /**< Shifted mode WEAK for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data in Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate Drive Strength for Port */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT 16 /**< Shift value for GPIO_DRIVESTRENGTHALT */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK 0x10000UL /**< Bit mask for GPIO_DRIVESTRENGTHALT */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG (_GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG << 16) /**< Shifted mode STRONG for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK (_GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK << 16) /**< Shifted mode WEAK for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data in Disable */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO P_MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ + +/* Bit fields for GPIO P_MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */ +#define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */ +#define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULLALT (_GPIO_P_MODEH_MODE8_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALT (_GPIO_P_MODEH_MODE8_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */ +#define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */ +#define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULLALT (_GPIO_P_MODEH_MODE9_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALT (_GPIO_P_MODEH_MODE9_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */ +#define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */ +#define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULLALT (_GPIO_P_MODEH_MODE10_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALT (_GPIO_P_MODEH_MODE10_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */ +#define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */ +#define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULLALT (_GPIO_P_MODEH_MODE11_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALT (_GPIO_P_MODEH_MODE11_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */ +#define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */ +#define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULLALT (_GPIO_P_MODEH_MODE12_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALT (_GPIO_P_MODEH_MODE12_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */ +#define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */ +#define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULLALT (_GPIO_P_MODEH_MODE13_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALT (_GPIO_P_MODEH_MODE13_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */ +#define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */ +#define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULLALT (_GPIO_P_MODEH_MODE14_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALT (_GPIO_P_MODEH_MODE14_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */ +#define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */ +#define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULLALT (_GPIO_P_MODEH_MODE15_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALT (_GPIO_P_MODEH_MODE15_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ + +/* Bit fields for GPIO P_DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */ +#define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */ + +/* Bit fields for GPIO P_DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ + +/* Bit fields for GPIO P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */ +#define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */ + +/* Bit fields for GPIO P_OVTDIS */ +#define _GPIO_P_OVTDIS_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_OVTDIS */ +#define _GPIO_P_OVTDIS_MASK 0x0000FFFFUL /**< Mask for GPIO_P_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_SHIFT 0 /**< Shift value for GPIO_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_MASK 0xFFFFUL /**< Bit mask for GPIO_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_OVTDIS */ +#define GPIO_P_OVTDIS_OVTDIS_DEFAULT (_GPIO_P_OVTDIS_OVTDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_OVTDIS */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTE (_GPIO_EXTIPSELL_EXTIPSEL0_PORTE << 0) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTG (_GPIO_EXTIPSELL_EXTIPSEL0_PORTG << 0) /**< Shifted mode PORTG for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTH (_GPIO_EXTIPSELL_EXTIPSEL0_PORTH << 0) /**< Shifted mode PORTH for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTI (_GPIO_EXTIPSELL_EXTIPSEL0_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTE (_GPIO_EXTIPSELL_EXTIPSEL1_PORTE << 4) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTG (_GPIO_EXTIPSELL_EXTIPSEL1_PORTG << 4) /**< Shifted mode PORTG for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTH (_GPIO_EXTIPSELL_EXTIPSEL1_PORTH << 4) /**< Shifted mode PORTH for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTI (_GPIO_EXTIPSELL_EXTIPSEL1_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTE (_GPIO_EXTIPSELL_EXTIPSEL2_PORTE << 8) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTG (_GPIO_EXTIPSELL_EXTIPSEL2_PORTG << 8) /**< Shifted mode PORTG for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTH (_GPIO_EXTIPSELL_EXTIPSEL2_PORTH << 8) /**< Shifted mode PORTH for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTI (_GPIO_EXTIPSELL_EXTIPSEL2_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTE (_GPIO_EXTIPSELL_EXTIPSEL3_PORTE << 12) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTG (_GPIO_EXTIPSELL_EXTIPSEL3_PORTG << 12) /**< Shifted mode PORTG for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTH (_GPIO_EXTIPSELL_EXTIPSEL3_PORTH << 12) /**< Shifted mode PORTH for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTI (_GPIO_EXTIPSELL_EXTIPSEL3_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTE (_GPIO_EXTIPSELL_EXTIPSEL4_PORTE << 16) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTG (_GPIO_EXTIPSELL_EXTIPSEL4_PORTG << 16) /**< Shifted mode PORTG for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTH (_GPIO_EXTIPSELL_EXTIPSEL4_PORTH << 16) /**< Shifted mode PORTH for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTI (_GPIO_EXTIPSELL_EXTIPSEL4_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTE (_GPIO_EXTIPSELL_EXTIPSEL5_PORTE << 20) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTG (_GPIO_EXTIPSELL_EXTIPSEL5_PORTG << 20) /**< Shifted mode PORTG for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTH (_GPIO_EXTIPSELL_EXTIPSEL5_PORTH << 20) /**< Shifted mode PORTH for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTI (_GPIO_EXTIPSELL_EXTIPSEL5_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTE (_GPIO_EXTIPSELL_EXTIPSEL6_PORTE << 24) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTG (_GPIO_EXTIPSELL_EXTIPSEL6_PORTG << 24) /**< Shifted mode PORTG for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTH (_GPIO_EXTIPSELL_EXTIPSEL6_PORTH << 24) /**< Shifted mode PORTH for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTI (_GPIO_EXTIPSELL_EXTIPSEL6_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTE (_GPIO_EXTIPSELL_EXTIPSEL7_PORTE << 28) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTG (_GPIO_EXTIPSELL_EXTIPSEL7_PORTG << 28) /**< Shifted mode PORTG for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTH (_GPIO_EXTIPSELL_EXTIPSEL7_PORTH << 28) /**< Shifted mode PORTH for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTI (_GPIO_EXTIPSELL_EXTIPSEL7_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL8 */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTE (_GPIO_EXTIPSELH_EXTIPSEL8_PORTE << 0) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTG (_GPIO_EXTIPSELH_EXTIPSEL8_PORTG << 0) /**< Shifted mode PORTG for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTH (_GPIO_EXTIPSELH_EXTIPSEL8_PORTH << 0) /**< Shifted mode PORTH for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTI (_GPIO_EXTIPSELH_EXTIPSEL8_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL9 */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTE (_GPIO_EXTIPSELH_EXTIPSEL9_PORTE << 4) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTG (_GPIO_EXTIPSELH_EXTIPSEL9_PORTG << 4) /**< Shifted mode PORTG for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTH (_GPIO_EXTIPSELH_EXTIPSEL9_PORTH << 4) /**< Shifted mode PORTH for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTI (_GPIO_EXTIPSELH_EXTIPSEL9_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL10 */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTE (_GPIO_EXTIPSELH_EXTIPSEL10_PORTE << 8) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTG (_GPIO_EXTIPSELH_EXTIPSEL10_PORTG << 8) /**< Shifted mode PORTG for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTH (_GPIO_EXTIPSELH_EXTIPSEL10_PORTH << 8) /**< Shifted mode PORTH for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTI (_GPIO_EXTIPSELH_EXTIPSEL10_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL11 */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTE (_GPIO_EXTIPSELH_EXTIPSEL11_PORTE << 12) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTG (_GPIO_EXTIPSELH_EXTIPSEL11_PORTG << 12) /**< Shifted mode PORTG for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTH (_GPIO_EXTIPSELH_EXTIPSEL11_PORTH << 12) /**< Shifted mode PORTH for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTI (_GPIO_EXTIPSELH_EXTIPSEL11_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL12 */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTE (_GPIO_EXTIPSELH_EXTIPSEL12_PORTE << 16) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTG (_GPIO_EXTIPSELH_EXTIPSEL12_PORTG << 16) /**< Shifted mode PORTG for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTH (_GPIO_EXTIPSELH_EXTIPSEL12_PORTH << 16) /**< Shifted mode PORTH for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTI (_GPIO_EXTIPSELH_EXTIPSEL12_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL13 */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTE (_GPIO_EXTIPSELH_EXTIPSEL13_PORTE << 20) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTG (_GPIO_EXTIPSELH_EXTIPSEL13_PORTG << 20) /**< Shifted mode PORTG for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTH (_GPIO_EXTIPSELH_EXTIPSEL13_PORTH << 20) /**< Shifted mode PORTH for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTI (_GPIO_EXTIPSELH_EXTIPSEL13_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL14 */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTE (_GPIO_EXTIPSELH_EXTIPSEL14_PORTE << 24) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTG (_GPIO_EXTIPSELH_EXTIPSEL14_PORTG << 24) /**< Shifted mode PORTG for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTH (_GPIO_EXTIPSELH_EXTIPSEL14_PORTH << 24) /**< Shifted mode PORTH for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTI (_GPIO_EXTIPSELH_EXTIPSEL14_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL15 */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL15 */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTG 0x00000006UL /**< Mode PORTG for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTH 0x00000007UL /**< Mode PORTH for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTE (_GPIO_EXTIPSELH_EXTIPSEL15_PORTE << 28) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTG (_GPIO_EXTIPSELH_EXTIPSEL15_PORTG << 28) /**< Shifted mode PORTG for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTH (_GPIO_EXTIPSELH_EXTIPSEL15_PORTH << 28) /**< Shifted mode PORTH for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTI (_GPIO_EXTIPSELH_EXTIPSEL15_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 << 16) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 << 16) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 << 16) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 << 16) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 << 20) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 << 20) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 << 20) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 << 20) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 << 24) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 << 24) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 << 24) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 << 24) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 << 28) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 << 28) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 << 28) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 << 28) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL8 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL8 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL9 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL9 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL10 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL10 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL11 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL11 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL12 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL12 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 << 16) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 << 16) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 << 16) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 << 16) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL13 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL13 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 << 20) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 << 20) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 << 20) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 << 20) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL14 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL14 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 << 24) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 << 24) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 << 24) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 << 24) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL15 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL15 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 << 28) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 << 28) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 << 28) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 << 28) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO EXTILEVEL */ +#define _GPIO_EXTILEVEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTILEVEL */ +#define _GPIO_EXTILEVEL_MASK 0x03FF0000UL /**< Mask for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU0 (0x1UL << 16) /**< EM4 Wake Up Level for EM4WU0 Pin */ +#define _GPIO_EXTILEVEL_EM4WU0_SHIFT 16 /**< Shift value for GPIO_EM4WU0 */ +#define _GPIO_EXTILEVEL_EM4WU0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WU0 */ +#define _GPIO_EXTILEVEL_EM4WU0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU0_DEFAULT (_GPIO_EXTILEVEL_EM4WU0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU1 (0x1UL << 17) /**< EM4 Wake Up Level for EM4WU1 Pin */ +#define _GPIO_EXTILEVEL_EM4WU1_SHIFT 17 /**< Shift value for GPIO_EM4WU1 */ +#define _GPIO_EXTILEVEL_EM4WU1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WU1 */ +#define _GPIO_EXTILEVEL_EM4WU1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU1_DEFAULT (_GPIO_EXTILEVEL_EM4WU1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU2 (0x1UL << 18) /**< EM4 Wake Up Level for EM4WU2 Pin */ +#define _GPIO_EXTILEVEL_EM4WU2_SHIFT 18 /**< Shift value for GPIO_EM4WU2 */ +#define _GPIO_EXTILEVEL_EM4WU2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WU2 */ +#define _GPIO_EXTILEVEL_EM4WU2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU2_DEFAULT (_GPIO_EXTILEVEL_EM4WU2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU3 (0x1UL << 19) /**< EM4 Wake Up Level for EM4WU3 Pin */ +#define _GPIO_EXTILEVEL_EM4WU3_SHIFT 19 /**< Shift value for GPIO_EM4WU3 */ +#define _GPIO_EXTILEVEL_EM4WU3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WU3 */ +#define _GPIO_EXTILEVEL_EM4WU3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU3_DEFAULT (_GPIO_EXTILEVEL_EM4WU3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU4 (0x1UL << 20) /**< EM4 Wake Up Level for EM4WU4 Pin */ +#define _GPIO_EXTILEVEL_EM4WU4_SHIFT 20 /**< Shift value for GPIO_EM4WU4 */ +#define _GPIO_EXTILEVEL_EM4WU4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WU4 */ +#define _GPIO_EXTILEVEL_EM4WU4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU4_DEFAULT (_GPIO_EXTILEVEL_EM4WU4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU5 (0x1UL << 21) /**< EM4 Wake Up Level for EM4WU5 Pin */ +#define _GPIO_EXTILEVEL_EM4WU5_SHIFT 21 /**< Shift value for GPIO_EM4WU5 */ +#define _GPIO_EXTILEVEL_EM4WU5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WU5 */ +#define _GPIO_EXTILEVEL_EM4WU5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU5_DEFAULT (_GPIO_EXTILEVEL_EM4WU5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU6 (0x1UL << 22) /**< EM4 Wake Up Level for EM4WU6 Pin */ +#define _GPIO_EXTILEVEL_EM4WU6_SHIFT 22 /**< Shift value for GPIO_EM4WU6 */ +#define _GPIO_EXTILEVEL_EM4WU6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WU6 */ +#define _GPIO_EXTILEVEL_EM4WU6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU6_DEFAULT (_GPIO_EXTILEVEL_EM4WU6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU7 (0x1UL << 23) /**< EM4 Wake Up Level for EM4WU7 Pin */ +#define _GPIO_EXTILEVEL_EM4WU7_SHIFT 23 /**< Shift value for GPIO_EM4WU7 */ +#define _GPIO_EXTILEVEL_EM4WU7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WU7 */ +#define _GPIO_EXTILEVEL_EM4WU7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU7_DEFAULT (_GPIO_EXTILEVEL_EM4WU7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU8 (0x1UL << 24) /**< EM4 Wake Up Level for EM4WU8 Pin */ +#define _GPIO_EXTILEVEL_EM4WU8_SHIFT 24 /**< Shift value for GPIO_EM4WU8 */ +#define _GPIO_EXTILEVEL_EM4WU8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WU8 */ +#define _GPIO_EXTILEVEL_EM4WU8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU8_DEFAULT (_GPIO_EXTILEVEL_EM4WU8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU9 (0x1UL << 25) /**< EM4 Wake Up Level for EM4WU9 Pin */ +#define _GPIO_EXTILEVEL_EM4WU9_SHIFT 25 /**< Shift value for GPIO_EM4WU9 */ +#define _GPIO_EXTILEVEL_EM4WU9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WU9 */ +#define _GPIO_EXTILEVEL_EM4WU9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU9_DEFAULT (_GPIO_EXTILEVEL_EM4WU9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IF */ +#define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IFS */ +#define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */ +#define _GPIO_IFS_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFS */ +#define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ +#define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFS */ +#define _GPIO_IFS_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IFS_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IFS_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ +#define GPIO_IFS_EM4WU_DEFAULT (_GPIO_IFS_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFS */ + +/* Bit fields for GPIO IFC */ +#define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */ +#define _GPIO_IFC_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFC */ +#define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ +#define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFC */ +#define _GPIO_IFC_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IFC_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IFC_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ +#define GPIO_IFC_EM4WU_DEFAULT (_GPIO_IFC_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFC */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IEN */ +#define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define _GPIO_IEN_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IEN_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WU_DEFAULT (_GPIO_IEN_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0xFFFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO ROUTEPEN */ +#define _GPIO_ROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_ROUTEPEN */ +#define _GPIO_ROUTEPEN_MASK 0x001F001FUL /**< Mask for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Serial Wire Clock and JTAG Test Clock Pin Enable */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Serial Wire Data and JTAG Test Mode Select Pin Enable */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_ROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_ROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_ROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDOPEN_DEFAULT (_GPIO_ROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_ROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_ROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_ROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDIPEN_DEFAULT (_GPIO_ROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWVPEN (0x1UL << 4) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_ROUTEPEN_SWVPEN_SHIFT 4 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_ROUTEPEN_SWVPEN_MASK 0x10UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_ROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWVPEN_DEFAULT (_GPIO_ROUTEPEN_SWVPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTCLKPEN (0x1UL << 16) /**< ETM Trace Clock Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_SHIFT 16 /**< Shift value for GPIO_ETMTCLKPEN */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_MASK 0x10000UL /**< Bit mask for GPIO_ETMTCLKPEN */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT (_GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD0PEN (0x1UL << 17) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_SHIFT 17 /**< Shift value for GPIO_ETMTD0PEN */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_MASK 0x20000UL /**< Bit mask for GPIO_ETMTD0PEN */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD1PEN (0x1UL << 18) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_SHIFT 18 /**< Shift value for GPIO_ETMTD1PEN */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_MASK 0x40000UL /**< Bit mask for GPIO_ETMTD1PEN */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD2PEN (0x1UL << 19) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_SHIFT 19 /**< Shift value for GPIO_ETMTD2PEN */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_MASK 0x80000UL /**< Bit mask for GPIO_ETMTD2PEN */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD3PEN (0x1UL << 20) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_SHIFT 20 /**< Shift value for GPIO_ETMTD3PEN */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_MASK 0x100000UL /**< Bit mask for GPIO_ETMTD3PEN */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ + +/* Bit fields for GPIO ROUTELOC0 */ +#define _GPIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_MASK 0x000001C3UL /**< Mask for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_SHIFT 0 /**< Shift value for GPIO_SWVLOC */ +#define _GPIO_ROUTELOC0_SWVLOC_MASK 0x3UL /**< Bit mask for GPIO_SWVLOC */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC0 (_GPIO_ROUTELOC0_SWVLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_DEFAULT (_GPIO_ROUTELOC0_SWVLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC1 (_GPIO_ROUTELOC0_SWVLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC2 (_GPIO_ROUTELOC0_SWVLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC3 (_GPIO_ROUTELOC0_SWVLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_ETMLOC_SHIFT 6 /**< Shift value for GPIO_ETMLOC */ +#define _GPIO_ROUTELOC0_ETMLOC_MASK 0x1C0UL /**< Bit mask for GPIO_ETMLOC */ +#define _GPIO_ROUTELOC0_ETMLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_ETMLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_ETMLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_ETMLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_ETMLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_ETMLOC_LOC4 0x00000004UL /**< Mode LOC4 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_ETMLOC_LOC5 0x00000005UL /**< Mode LOC5 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_ETMLOC_LOC0 (_GPIO_ROUTELOC0_ETMLOC_LOC0 << 6) /**< Shifted mode LOC0 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_ETMLOC_DEFAULT (_GPIO_ROUTELOC0_ETMLOC_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_ETMLOC_LOC1 (_GPIO_ROUTELOC0_ETMLOC_LOC1 << 6) /**< Shifted mode LOC1 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_ETMLOC_LOC2 (_GPIO_ROUTELOC0_ETMLOC_LOC2 << 6) /**< Shifted mode LOC2 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_ETMLOC_LOC3 (_GPIO_ROUTELOC0_ETMLOC_LOC3 << 6) /**< Shifted mode LOC3 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_ETMLOC_LOC4 (_GPIO_ROUTELOC0_ETMLOC_LOC4 << 6) /**< Shifted mode LOC4 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_ETMLOC_LOC5 (_GPIO_ROUTELOC0_ETMLOC_LOC5 << 6) /**< Shifted mode LOC5 for GPIO_ROUTELOC0 */ + +/* Bit fields for GPIO INSENSE */ +#define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */ +#define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */ +#define GPIO_INSENSE_INT (0x1UL << 0) /**< Interrupt Sense Enable */ +#define _GPIO_INSENSE_INT_SHIFT 0 /**< Shift value for GPIO_INT */ +#define _GPIO_INSENSE_INT_MASK 0x1UL /**< Bit mask for GPIO_INT */ +#define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_EM4WU (0x1UL << 1) /**< EM4WU Interrupt Sense Enable */ +#define _GPIO_INSENSE_EM4WU_SHIFT 1 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_INSENSE_EM4WU_MASK 0x2UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_INSENSE_EM4WU_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_EM4WU_DEFAULT (_GPIO_INSENSE_EM4WU_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/** @} */ +/** @} End of group EFM32GG11B_GPIO */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio_p.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio_p.h new file mode 100644 index 0000000000000..732b49e734ded --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio_p.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_GPIO_P register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief GPIO_P GPIO P Register + * @ingroup EFM32GG11B_GPIO + ******************************************************************************/ +typedef struct { + __IOM uint32_t CTRL; /**< Port Control Register */ + __IOM uint32_t MODEL; /**< Port Pin Mode Low Register */ + __IOM uint32_t MODEH; /**< Port Pin Mode High Register */ + __IOM uint32_t DOUT; /**< Port Data Out Register */ + uint32_t RESERVED0[2U]; /**< Reserved for future use **/ + __IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */ + __IM uint32_t DIN; /**< Port Data in Register */ + __IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t OVTDIS; /**< Over Voltage Disable for All Modes */ + uint32_t RESERVED2[1U]; /**< Reserved future */ +} GPIO_P_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_i2c.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_i2c.h new file mode 100644 index 0000000000000..b501929c6da77 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_i2c.h @@ -0,0 +1,841 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_I2C register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_I2C I2C + * @{ + * @brief EFM32GG11B_I2C Register Declaration + ******************************************************************************/ +/** I2C Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Slave Address Register */ + __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ +} I2C_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_I2C + * @{ + * @defgroup EFM32GG11B_I2C_BitFields I2C Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */ +#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP When Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send Start Condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send Stop Condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue Transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort Transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending Continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending Abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START Condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START Condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP Condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IFS */ +#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */ +#define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */ +#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */ +#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */ +#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */ +#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */ +#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */ +#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */ +#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */ +#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */ +#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */ +#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */ +#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */ +#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */ +#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */ +#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */ +#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */ +#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */ +#define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */ +#define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */ + +/* Bit fields for I2C IFC */ +#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */ +#define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */ +#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */ +#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */ +#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */ +#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */ +#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */ +#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */ +#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */ +#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */ +#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */ +#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */ +#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */ +#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */ +#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */ +#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */ +#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */ +#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */ +#define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */ +#define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ + +/* Bit fields for I2C ROUTEPEN */ +#define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */ +#define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */ +#define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */ +#define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */ +#define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */ +#define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */ +#define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */ +#define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ + +/* Bit fields for I2C ROUTELOC0 */ +#define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_MASK 0x00000707UL /**< Mask for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */ +#define _I2C_ROUTELOC0_SDALOC_MASK 0x7UL /**< Bit mask for I2C_SDALOC */ +#define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */ +#define _I2C_ROUTELOC0_SCLLOC_MASK 0x700UL /**< Bit mask for I2C_SCLLOC */ +#define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ + +/** @} */ +/** @} End of group EFM32GG11B_I2C */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_idac.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_idac.h new file mode 100644 index 0000000000000..b0f9dc7284f65 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_idac.h @@ -0,0 +1,392 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_IDAC register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_IDAC IDAC + * @{ + * @brief EFM32GG11B_IDAC Register Declaration + ******************************************************************************/ +/** IDAC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CURPROG; /**< Current Programming Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */ + + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ +} IDAC_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_IDAC + * @{ + * @defgroup EFM32GG11B_IDAC_BitFields IDAC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for IDAC CTRL */ +#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */ +#define _IDAC_CTRL_MASK 0x01FD7FFFUL /**< Mask for IDAC_CTRL */ +#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */ +#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */ +#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */ +#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */ +#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */ +#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */ +#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */ +#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */ +#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */ +#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */ +#define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */ +#define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */ +#define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */ +#define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */ +#define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */ +#define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */ +#define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */ +#define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */ +#define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */ +#define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */ +#define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */ +#define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */ +#define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */ +#define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */ +#define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */ +#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */ +#define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */ +#define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */ +#define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTEN (0x1UL << 18) /**< Output Enable */ +#define _IDAC_CTRL_MAINOUTEN_SHIFT 18 /**< Shift value for IDAC_MAINOUTEN */ +#define _IDAC_CTRL_MAINOUTEN_MASK 0x40000UL /**< Bit mask for IDAC_MAINOUTEN */ +#define _IDAC_CTRL_MAINOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTEN_DEFAULT (_IDAC_CTRL_MAINOUTEN_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTENPRS (0x1UL << 19) /**< PRS Controlled Main Pad Output Enable */ +#define _IDAC_CTRL_MAINOUTENPRS_SHIFT 19 /**< Shift value for IDAC_MAINOUTENPRS */ +#define _IDAC_CTRL_MAINOUTENPRS_MASK 0x80000UL /**< Bit mask for IDAC_MAINOUTENPRS */ +#define _IDAC_CTRL_MAINOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTENPRS_DEFAULT (_IDAC_CTRL_MAINOUTENPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */ +#define _IDAC_CTRL_PRSSEL_MASK 0x1F00000UL /**< Bit mask for IDAC_PRSSEL */ +#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH12 (_IDAC_CTRL_PRSSEL_PRSCH12 << 20) /**< Shifted mode PRSCH12 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH13 (_IDAC_CTRL_PRSSEL_PRSCH13 << 20) /**< Shifted mode PRSCH13 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH14 (_IDAC_CTRL_PRSSEL_PRSCH14 << 20) /**< Shifted mode PRSCH14 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH15 (_IDAC_CTRL_PRSSEL_PRSCH15 << 20) /**< Shifted mode PRSCH15 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH16 (_IDAC_CTRL_PRSSEL_PRSCH16 << 20) /**< Shifted mode PRSCH16 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH17 (_IDAC_CTRL_PRSSEL_PRSCH17 << 20) /**< Shifted mode PRSCH17 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH18 (_IDAC_CTRL_PRSSEL_PRSCH18 << 20) /**< Shifted mode PRSCH18 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH19 (_IDAC_CTRL_PRSSEL_PRSCH19 << 20) /**< Shifted mode PRSCH19 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH20 (_IDAC_CTRL_PRSSEL_PRSCH20 << 20) /**< Shifted mode PRSCH20 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH21 (_IDAC_CTRL_PRSSEL_PRSCH21 << 20) /**< Shifted mode PRSCH21 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH22 (_IDAC_CTRL_PRSSEL_PRSCH22 << 20) /**< Shifted mode PRSCH22 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH23 (_IDAC_CTRL_PRSSEL_PRSCH23 << 20) /**< Shifted mode PRSCH23 for IDAC_CTRL */ + +/* Bit fields for IDAC CURPROG */ +#define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */ +#define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */ +#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */ +#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */ +#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */ +#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */ +#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */ +#define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */ +#define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */ +#define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */ + +/* Bit fields for IDAC DUTYCONFIG */ +#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */ +#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */ +#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */ +#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */ + +/* Bit fields for IDAC STATUS */ +#define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */ +#define _IDAC_STATUS_MASK 0x00000003UL /**< Mask for IDAC_STATUS */ +#define IDAC_STATUS_CURSTABLE (0x1UL << 0) /**< IDAC Output Current Stable */ +#define _IDAC_STATUS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_STATUS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_STATUS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_CURSTABLE_DEFAULT (_IDAC_STATUS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */ +#define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */ + +/* Bit fields for IDAC IF */ +#define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */ +#define _IDAC_IF_MASK 0x00000003UL /**< Mask for IDAC_IF */ +#define IDAC_IF_CURSTABLE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ +#define _IDAC_IF_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IF_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IF_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ +#define IDAC_IF_CURSTABLE_DEFAULT (_IDAC_IF_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IF */ +#define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */ +#define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ +#define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */ + +/* Bit fields for IDAC IFS */ +#define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */ +#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */ +#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */ +#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */ +#define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */ + +/* Bit fields for IDAC IFC */ +#define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */ +#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */ +#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */ +#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */ + +/* Bit fields for IDAC IEN */ +#define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */ +#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */ +#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */ +#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */ +#define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */ + +/* Bit fields for IDAC APORTREQ */ +#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */ +#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the APORT Bus Connected to APORT1X is Requested */ +#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */ +#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */ +#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */ +#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */ +#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */ +#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ + +/* Bit fields for IDAC APORTCONFLICT */ +#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */ +#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ + +/** @} */ +/** @} End of group EFM32GG11B_IDAC */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lcd.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lcd.h new file mode 100644 index 0000000000000..b4739d414b543 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lcd.h @@ -0,0 +1,636 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_LCD register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_LCD LCD + * @{ + * @brief EFM32GG11B_LCD Register Declaration + ******************************************************************************/ +/** LCD Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DISPCTRL; /**< Display Control Register */ + __IOM uint32_t SEGEN; /**< Segment Enable Register */ + __IOM uint32_t BACTRL; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t AREGA; /**< Animation Register a */ + __IOM uint32_t AREGB; /**< Animation Register B */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t BIASCTRL; /**< Analog BIAS Control */ + + uint32_t RESERVED1[3U]; /**< Reserved for future use **/ + __IOM uint32_t SEGD0L; /**< Segment Data Low Register 0 */ + __IOM uint32_t SEGD1L; /**< Segment Data Low Register 1 */ + __IOM uint32_t SEGD2L; /**< Segment Data Low Register 2 */ + __IOM uint32_t SEGD3L; /**< Segment Data Low Register 3 */ + __IOM uint32_t SEGD0H; /**< Segment Data High Register 0 */ + __IOM uint32_t SEGD1H; /**< Segment Data High Register 1 */ + __IOM uint32_t SEGD2H; /**< Segment Data High Register 2 */ + __IOM uint32_t SEGD3H; /**< Segment Data High Register 3 */ + __IOM uint32_t SEGD4L; /**< Segment Data Low Register 4 */ + __IOM uint32_t SEGD5L; /**< Segment Data Low Register 5 */ + __IOM uint32_t SEGD6L; /**< Segment Data Low Register 6 */ + __IOM uint32_t SEGD7L; /**< Segment Data Low Register 7 */ + __IOM uint32_t SEGD4H; /**< Segment Data High Register 4 */ + __IOM uint32_t SEGD5H; /**< Segment Data High Register 5 */ + __IOM uint32_t SEGD6H; /**< Segment Data High Register 6 */ + __IOM uint32_t SEGD7H; /**< Segment Data High Register 7 */ + uint32_t RESERVED2[16U]; /**< Reserved for future use **/ + __IOM uint32_t FREEZE; /**< Freeze Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED3[10U]; /**< Reserved for future use **/ + __IOM uint32_t FRAMERATE; /**< Frame Rate */ + __IOM uint32_t SEGEN2; /**< Segment Enable (32 to 39) */ +} LCD_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_LCD + * @{ + * @defgroup EFM32GG11B_LCD_BitFields LCD Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for LCD CTRL */ +#define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */ +#define _LCD_CTRL_MASK 0x00800007UL /**< Mask for LCD_CTRL */ +#define LCD_CTRL_EN (0x1UL << 0) /**< LCD Enable */ +#define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */ +#define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */ +#define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */ +#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */ +#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /**< Mode FCEVENT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */ +#define LCD_CTRL_DSC (0x1UL << 23) /**< Direct Segment Control */ +#define _LCD_CTRL_DSC_SHIFT 23 /**< Shift value for LCD_DSC */ +#define _LCD_CTRL_DSC_MASK 0x800000UL /**< Bit mask for LCD_DSC */ +#define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 23) /**< Shifted mode DEFAULT for LCD_CTRL */ + +/* Bit fields for LCD DISPCTRL */ +#define _LCD_DISPCTRL_RESETVALUE 0x00103F00UL /**< Default value for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MASK 0x33703F17UL /**< Mask for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */ +#define _LCD_DISPCTRL_MUX_MASK 0x7UL /**< Bit mask for LCD_MUX */ +#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_SEXTAPLEX 0x00000005UL /**< Mode SEXTAPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_OCTAPLEX 0x00000007UL /**< Mode OCTAPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_SEXTAPLEX (_LCD_DISPCTRL_MUX_SEXTAPLEX << 0) /**< Shifted mode SEXTAPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_OCTAPLEX (_LCD_DISPCTRL_MUX_OCTAPLEX << 0) /**< Shifted mode OCTAPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */ +#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */ +#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */ +#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONTRAST_SHIFT 8 /**< Shift value for LCD_CONTRAST */ +#define _LCD_DISPCTRL_CONTRAST_MASK 0x3F00UL /**< Bit mask for LCD_CONTRAST */ +#define _LCD_DISPCTRL_CONTRAST_DEFAULT 0x0000003FUL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONTRAST_DEFAULT (_LCD_DISPCTRL_CONTRAST_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_SHIFT 20 /**< Shift value for LCD_CHGRDST */ +#define _LCD_DISPCTRL_CHGRDST_MASK 0x700000UL /**< Bit mask for LCD_CHGRDST */ +#define _LCD_DISPCTRL_CHGRDST_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_DEFAULT 0x00000001UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_ONE 0x00000001UL /**< Mode ONE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_TWO 0x00000002UL /**< Mode TWO for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_THREE 0x00000003UL /**< Mode THREE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_FOUR 0x00000004UL /**< Mode FOUR for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_DISABLE (_LCD_DISPCTRL_CHGRDST_DISABLE << 20) /**< Shifted mode DISABLE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_DEFAULT (_LCD_DISPCTRL_CHGRDST_DEFAULT << 20) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_ONE (_LCD_DISPCTRL_CHGRDST_ONE << 20) /**< Shifted mode ONE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_TWO (_LCD_DISPCTRL_CHGRDST_TWO << 20) /**< Shifted mode TWO for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_THREE (_LCD_DISPCTRL_CHGRDST_THREE << 20) /**< Shifted mode THREE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_FOUR (_LCD_DISPCTRL_CHGRDST_FOUR << 20) /**< Shifted mode FOUR for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_SHIFT 24 /**< Shift value for LCD_BIAS */ +#define _LCD_DISPCTRL_BIAS_MASK 0x3000000UL /**< Bit mask for LCD_BIAS */ +#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 24) /**< Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 24) /**< Shifted mode ONEHALF for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 24) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 24) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MODE_SHIFT 28 /**< Shift value for LCD_MODE */ +#define _LCD_DISPCTRL_MODE_MASK 0x30000000UL /**< Bit mask for LCD_MODE */ +#define _LCD_DISPCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MODE_NOEXTCAP 0x00000000UL /**< Mode NOEXTCAP for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MODE_STEPDOWN 0x00000001UL /**< Mode STEPDOWN for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MODE_CPINTOSC 0x00000002UL /**< Mode CPINTOSC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MODE_DEFAULT (_LCD_DISPCTRL_MODE_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MODE_NOEXTCAP (_LCD_DISPCTRL_MODE_NOEXTCAP << 28) /**< Shifted mode NOEXTCAP for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MODE_STEPDOWN (_LCD_DISPCTRL_MODE_STEPDOWN << 28) /**< Shifted mode STEPDOWN for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MODE_CPINTOSC (_LCD_DISPCTRL_MODE_CPINTOSC << 28) /**< Shifted mode CPINTOSC for LCD_DISPCTRL */ + +/* Bit fields for LCD SEGEN */ +#define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */ +#define _LCD_SEGEN_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGEN */ +#define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */ +#define _LCD_SEGEN_SEGEN_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGEN */ +#define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */ +#define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */ + +/* Bit fields for LCD BACTRL */ +#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */ +#define _LCD_BACTRL_MASK 0x10FF01FFUL /**< Mask for LCD_BACTRL */ +#define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */ +#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */ +#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */ +#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */ +#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */ +#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */ +#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */ +#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */ +#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */ +#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */ +#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */ +#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */ +#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */ +#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */ +#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */ +#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */ +#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */ +#define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */ +#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */ +#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */ +#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */ +#define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */ +#define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACTRL */ +#define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */ +#define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */ +#define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */ +#define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */ +#define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */ +#define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */ +#define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */ + +/* Bit fields for LCD STATUS */ +#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */ +#define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */ +#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */ +#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */ +#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */ +#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */ +#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */ +#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */ + +/* Bit fields for LCD AREGA */ +#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */ +#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */ +#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */ +#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */ +#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */ +#define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */ + +/* Bit fields for LCD AREGB */ +#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */ +#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */ +#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */ +#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */ +#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */ +#define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */ + +/* Bit fields for LCD IF */ +#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */ +#define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */ +#define LCD_IF_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag */ +#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ +#define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */ + +/* Bit fields for LCD IFS */ +#define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */ +#define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */ +#define LCD_IFS_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Set */ +#define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */ +#define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFS */ + +/* Bit fields for LCD IFC */ +#define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */ +#define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */ +#define LCD_IFC_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Clear */ +#define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */ +#define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFC */ + +/* Bit fields for LCD IEN */ +#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */ +#define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */ +#define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter Interrupt Enable */ +#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ +#define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */ + +/* Bit fields for LCD BIASCTRL */ +#define _LCD_BIASCTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_MASK 0x00001CF7UL /**< Mask for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_SPEED_SHIFT 0 /**< Shift value for LCD_SPEED */ +#define _LCD_BIASCTRL_SPEED_MASK 0x7UL /**< Bit mask for LCD_SPEED */ +#define _LCD_BIASCTRL_SPEED_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_SPEED_DEFAULT (_LCD_BIASCTRL_SPEED_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_BUFDRV_SHIFT 4 /**< Shift value for LCD_BUFDRV */ +#define _LCD_BIASCTRL_BUFDRV_MASK 0xF0UL /**< Bit mask for LCD_BUFDRV */ +#define _LCD_BIASCTRL_BUFDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_BUFDRV_DEFAULT (_LCD_BIASCTRL_BUFDRV_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_BUFBIAS_SHIFT 10 /**< Shift value for LCD_BUFBIAS */ +#define _LCD_BIASCTRL_BUFBIAS_MASK 0x1C00UL /**< Bit mask for LCD_BUFBIAS */ +#define _LCD_BIASCTRL_BUFBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_BUFBIAS_DEFAULT (_LCD_BIASCTRL_BUFBIAS_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ + +/* Bit fields for LCD SEGD0L */ +#define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */ +#define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */ +#define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */ +#define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */ +#define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */ +#define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */ + +/* Bit fields for LCD SEGD1L */ +#define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */ +#define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */ +#define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */ +#define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */ +#define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */ +#define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */ + +/* Bit fields for LCD SEGD2L */ +#define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */ +#define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */ +#define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */ +#define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */ +#define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */ +#define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */ + +/* Bit fields for LCD SEGD3L */ +#define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */ +#define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */ +#define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */ +#define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */ +#define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */ +#define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */ + +/* Bit fields for LCD SEGD0H */ +#define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */ +#define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */ +#define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */ +#define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */ +#define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */ +#define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */ + +/* Bit fields for LCD SEGD1H */ +#define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */ +#define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */ +#define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */ +#define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */ +#define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */ +#define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */ + +/* Bit fields for LCD SEGD2H */ +#define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */ +#define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */ +#define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */ +#define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */ +#define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */ +#define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */ + +/* Bit fields for LCD SEGD3H */ +#define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */ +#define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */ +#define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */ +#define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */ +#define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */ +#define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */ + +/* Bit fields for LCD SEGD4L */ +#define _LCD_SEGD4L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4L */ +#define _LCD_SEGD4L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD4L */ +#define _LCD_SEGD4L_SEGD4L_SHIFT 0 /**< Shift value for LCD_SEGD4L */ +#define _LCD_SEGD4L_SEGD4L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD4L */ +#define _LCD_SEGD4L_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4L */ +#define LCD_SEGD4L_SEGD4L_DEFAULT (_LCD_SEGD4L_SEGD4L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4L */ + +/* Bit fields for LCD SEGD5L */ +#define _LCD_SEGD5L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5L */ +#define _LCD_SEGD5L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD5L */ +#define _LCD_SEGD5L_SEGD5L_SHIFT 0 /**< Shift value for LCD_SEGD5L */ +#define _LCD_SEGD5L_SEGD5L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD5L */ +#define _LCD_SEGD5L_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5L */ +#define LCD_SEGD5L_SEGD5L_DEFAULT (_LCD_SEGD5L_SEGD5L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5L */ + +/* Bit fields for LCD SEGD6L */ +#define _LCD_SEGD6L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6L */ +#define _LCD_SEGD6L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD6L */ +#define _LCD_SEGD6L_SEGD6L_SHIFT 0 /**< Shift value for LCD_SEGD6L */ +#define _LCD_SEGD6L_SEGD6L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD6L */ +#define _LCD_SEGD6L_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6L */ +#define LCD_SEGD6L_SEGD6L_DEFAULT (_LCD_SEGD6L_SEGD6L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6L */ + +/* Bit fields for LCD SEGD7L */ +#define _LCD_SEGD7L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7L */ +#define _LCD_SEGD7L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD7L */ +#define _LCD_SEGD7L_SEGD7L_SHIFT 0 /**< Shift value for LCD_SEGD7L */ +#define _LCD_SEGD7L_SEGD7L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD7L */ +#define _LCD_SEGD7L_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7L */ +#define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */ + +/* Bit fields for LCD SEGD4H */ +#define _LCD_SEGD4H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4H */ +#define _LCD_SEGD4H_MASK 0x000000FFUL /**< Mask for LCD_SEGD4H */ +#define _LCD_SEGD4H_SEGD4H_SHIFT 0 /**< Shift value for LCD_SEGD4H */ +#define _LCD_SEGD4H_SEGD4H_MASK 0xFFUL /**< Bit mask for LCD_SEGD4H */ +#define _LCD_SEGD4H_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4H */ +#define LCD_SEGD4H_SEGD4H_DEFAULT (_LCD_SEGD4H_SEGD4H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4H */ + +/* Bit fields for LCD SEGD5H */ +#define _LCD_SEGD5H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5H */ +#define _LCD_SEGD5H_MASK 0x000000FFUL /**< Mask for LCD_SEGD5H */ +#define _LCD_SEGD5H_SEGD5H_SHIFT 0 /**< Shift value for LCD_SEGD5H */ +#define _LCD_SEGD5H_SEGD5H_MASK 0xFFUL /**< Bit mask for LCD_SEGD5H */ +#define _LCD_SEGD5H_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5H */ +#define LCD_SEGD5H_SEGD5H_DEFAULT (_LCD_SEGD5H_SEGD5H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5H */ + +/* Bit fields for LCD SEGD6H */ +#define _LCD_SEGD6H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6H */ +#define _LCD_SEGD6H_MASK 0x000000FFUL /**< Mask for LCD_SEGD6H */ +#define _LCD_SEGD6H_SEGD6H_SHIFT 0 /**< Shift value for LCD_SEGD6H */ +#define _LCD_SEGD6H_SEGD6H_MASK 0xFFUL /**< Bit mask for LCD_SEGD6H */ +#define _LCD_SEGD6H_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6H */ +#define LCD_SEGD6H_SEGD6H_DEFAULT (_LCD_SEGD6H_SEGD6H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6H */ + +/* Bit fields for LCD SEGD7H */ +#define _LCD_SEGD7H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7H */ +#define _LCD_SEGD7H_MASK 0x000000FFUL /**< Mask for LCD_SEGD7H */ +#define _LCD_SEGD7H_SEGD7H_SHIFT 0 /**< Shift value for LCD_SEGD7H */ +#define _LCD_SEGD7H_SEGD7H_MASK 0xFFUL /**< Bit mask for LCD_SEGD7H */ +#define _LCD_SEGD7H_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7H */ +#define LCD_SEGD7H_SEGD7H_DEFAULT (_LCD_SEGD7H_SEGD7H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7H */ + +/* Bit fields for LCD FREEZE */ +#define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */ +#define _LCD_FREEZE_MASK 0x00000003UL /**< Mask for LCD_FREEZE */ +#define LCD_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */ +#define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */ +#define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */ +#define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */ +#define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */ +#define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */ +#define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LCD_FREEZE */ +#define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LCD_FREEZE */ +#define LCD_FREEZE_LCDGATE (0x1UL << 1) /**< LCD Gate */ +#define _LCD_FREEZE_LCDGATE_SHIFT 1 /**< Shift value for LCD_LCDGATE */ +#define _LCD_FREEZE_LCDGATE_MASK 0x2UL /**< Bit mask for LCD_LCDGATE */ +#define _LCD_FREEZE_LCDGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */ +#define _LCD_FREEZE_LCDGATE_UNGATE 0x00000000UL /**< Mode UNGATE for LCD_FREEZE */ +#define _LCD_FREEZE_LCDGATE_GATE 0x00000001UL /**< Mode GATE for LCD_FREEZE */ +#define LCD_FREEZE_LCDGATE_DEFAULT (_LCD_FREEZE_LCDGATE_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_FREEZE */ +#define LCD_FREEZE_LCDGATE_UNGATE (_LCD_FREEZE_LCDGATE_UNGATE << 1) /**< Shifted mode UNGATE for LCD_FREEZE */ +#define LCD_FREEZE_LCDGATE_GATE (_LCD_FREEZE_LCDGATE_GATE << 1) /**< Shifted mode GATE for LCD_FREEZE */ + +/* Bit fields for LCD SYNCBUSY */ +#define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_MASK 0x000FFFFFUL /**< Mask for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */ +#define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */ +#define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /**< BACTRL Register Busy */ +#define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */ +#define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */ +#define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_AREGA (0x1UL << 2) /**< AREGA Register Busy */ +#define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */ +#define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */ +#define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_AREGB (0x1UL << 3) /**< AREGB Register Busy */ +#define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */ +#define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */ +#define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /**< SEGD0L Register Busy */ +#define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */ +#define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */ +#define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /**< SEGD1L Register Busy */ +#define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */ +#define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */ +#define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /**< SEGD2L Register Busy */ +#define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */ +#define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */ +#define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /**< SEGD3L Register Busy */ +#define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */ +#define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */ +#define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /**< SEGD0H Register Busy */ +#define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */ +#define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */ +#define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /**< SEGD1H Register Busy */ +#define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */ +#define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */ +#define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /**< SEGD2H Register Busy */ +#define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */ +#define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */ +#define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /**< SEGD3H Register Busy */ +#define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */ +#define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */ +#define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD4L (0x1UL << 12) /**< SEGD4L Register Busy */ +#define _LCD_SYNCBUSY_SEGD4L_SHIFT 12 /**< Shift value for LCD_SEGD4L */ +#define _LCD_SYNCBUSY_SEGD4L_MASK 0x1000UL /**< Bit mask for LCD_SEGD4L */ +#define _LCD_SYNCBUSY_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD4L_DEFAULT (_LCD_SYNCBUSY_SEGD4L_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD5L (0x1UL << 13) /**< SEGD5L Register Busy */ +#define _LCD_SYNCBUSY_SEGD5L_SHIFT 13 /**< Shift value for LCD_SEGD5L */ +#define _LCD_SYNCBUSY_SEGD5L_MASK 0x2000UL /**< Bit mask for LCD_SEGD5L */ +#define _LCD_SYNCBUSY_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD5L_DEFAULT (_LCD_SYNCBUSY_SEGD5L_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD6L (0x1UL << 14) /**< SEGD6L Register Busy */ +#define _LCD_SYNCBUSY_SEGD6L_SHIFT 14 /**< Shift value for LCD_SEGD6L */ +#define _LCD_SYNCBUSY_SEGD6L_MASK 0x4000UL /**< Bit mask for LCD_SEGD6L */ +#define _LCD_SYNCBUSY_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD6L_DEFAULT (_LCD_SYNCBUSY_SEGD6L_DEFAULT << 14) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD7L (0x1UL << 15) /**< SEGD7L Register Busy */ +#define _LCD_SYNCBUSY_SEGD7L_SHIFT 15 /**< Shift value for LCD_SEGD7L */ +#define _LCD_SYNCBUSY_SEGD7L_MASK 0x8000UL /**< Bit mask for LCD_SEGD7L */ +#define _LCD_SYNCBUSY_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD7L_DEFAULT (_LCD_SYNCBUSY_SEGD7L_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD4H (0x1UL << 16) /**< SEGD4H Register Busy */ +#define _LCD_SYNCBUSY_SEGD4H_SHIFT 16 /**< Shift value for LCD_SEGD4H */ +#define _LCD_SYNCBUSY_SEGD4H_MASK 0x10000UL /**< Bit mask for LCD_SEGD4H */ +#define _LCD_SYNCBUSY_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD4H_DEFAULT (_LCD_SYNCBUSY_SEGD4H_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD5H (0x1UL << 17) /**< SEGD5H Register Busy */ +#define _LCD_SYNCBUSY_SEGD5H_SHIFT 17 /**< Shift value for LCD_SEGD5H */ +#define _LCD_SYNCBUSY_SEGD5H_MASK 0x20000UL /**< Bit mask for LCD_SEGD5H */ +#define _LCD_SYNCBUSY_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD5H_DEFAULT (_LCD_SYNCBUSY_SEGD5H_DEFAULT << 17) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD6H (0x1UL << 18) /**< SEGD6H Register Busy */ +#define _LCD_SYNCBUSY_SEGD6H_SHIFT 18 /**< Shift value for LCD_SEGD6H */ +#define _LCD_SYNCBUSY_SEGD6H_MASK 0x40000UL /**< Bit mask for LCD_SEGD6H */ +#define _LCD_SYNCBUSY_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD6H_DEFAULT (_LCD_SYNCBUSY_SEGD6H_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD7H (0x1UL << 19) /**< SEGD7H Register Busy */ +#define _LCD_SYNCBUSY_SEGD7H_SHIFT 19 /**< Shift value for LCD_SEGD7H */ +#define _LCD_SYNCBUSY_SEGD7H_MASK 0x80000UL /**< Bit mask for LCD_SEGD7H */ +#define _LCD_SYNCBUSY_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD7H_DEFAULT (_LCD_SYNCBUSY_SEGD7H_DEFAULT << 19) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ + +/* Bit fields for LCD FRAMERATE */ +#define _LCD_FRAMERATE_RESETVALUE 0x00000000UL /**< Default value for LCD_FRAMERATE */ +#define _LCD_FRAMERATE_MASK 0x000001FFUL /**< Mask for LCD_FRAMERATE */ +#define _LCD_FRAMERATE_FRDIV_SHIFT 0 /**< Shift value for LCD_FRDIV */ +#define _LCD_FRAMERATE_FRDIV_MASK 0x1FFUL /**< Bit mask for LCD_FRDIV */ +#define _LCD_FRAMERATE_FRDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FRAMERATE */ +#define LCD_FRAMERATE_FRDIV_DEFAULT (_LCD_FRAMERATE_FRDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FRAMERATE */ + +/* Bit fields for LCD SEGEN2 */ +#define _LCD_SEGEN2_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN2 */ +#define _LCD_SEGEN2_MASK 0x000000FFUL /**< Mask for LCD_SEGEN2 */ +#define _LCD_SEGEN2_SEGEN2_SHIFT 0 /**< Shift value for LCD_SEGEN2 */ +#define _LCD_SEGEN2_SEGEN2_MASK 0xFFUL /**< Bit mask for LCD_SEGEN2 */ +#define _LCD_SEGEN2_SEGEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN2 */ +#define LCD_SEGEN2_SEGEN2_DEFAULT (_LCD_SEGEN2_SEGEN2_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN2 */ + +/** @} */ +/** @} End of group EFM32GG11B_LCD */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma.h new file mode 100644 index 0000000000000..5e7d87200d4d1 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma.h @@ -0,0 +1,781 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_LDMA register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_LDMA LDMA + * @{ + * @brief EFM32GG11B_LDMA Register Declaration + ******************************************************************************/ +/** LDMA Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */ + uint32_t RESERVED0[5U]; /**< Reserved for future use **/ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + uint32_t RESERVED1[7U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED2[4U]; /**< Reserved registers */ + LDMA_CH_TypeDef CH[24U]; /**< DMA Channel Registers */ +} LDMA_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_LDMA + * @{ + * @defgroup EFM32GG11B_LDMA_BitFields LDMA Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x17000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x1F00FFFFUL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */ +#define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */ +#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */ +#define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */ +#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000017UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x18100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000018UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNC */ +#define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */ +#define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */ +#define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */ +#define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFFFFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFFFFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x00FFFFFFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x00FFFFFFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFFFFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x00FFFFFFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFFFFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x80FFFFFFUL /**< Mask for LDMA_IF */ +#define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IF_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IFS */ +#define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */ +#define _LDMA_IFS_MASK 0x80FFFFFFUL /**< Mask for LDMA_IFS */ +#define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IFS_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */ +#define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */ + +/* Bit fields for LDMA IFC */ +#define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */ +#define _LDMA_IFC_MASK 0x80FFFFFFUL /**< Mask for LDMA_IFC */ +#define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IFC_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */ +#define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x80FFFFFFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IEN_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_REQSEL */ +#define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV 0x00000000UL /**< Mode USART3RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV 0x00000000UL /**< Mode USART4RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV 0x00000000UL /**< Mode USART5RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV 0x00000000UL /**< Mode UART0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV 0x00000000UL /**< Mode UART1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV 0x00000000UL /**< Mode I2C2RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000000UL /**< Mode TIMER4UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF 0x00000000UL /**< Mode TIMER5UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF 0x00000000UL /**< Mode TIMER6UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF 0x00000000UL /**< Mode WTIMER1UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF 0x00000000UL /**< Mode WTIMER2UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF 0x00000000UL /**< Mode WTIMER3UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY 0x00000000UL /**< Mode EBIPXL0EMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBL 0x00000001UL /**< Mode USART3TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART4TXBL 0x00000001UL /**< Mode USART4TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART5TXBL 0x00000001UL /**< Mode USART5TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_UART0TXBL 0x00000001UL /**< Mode UART0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_UART1TXBL 0x00000001UL /**< Mode UART1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C2TXBL 0x00000001UL /**< Mode I2C2TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000001UL /**< Mode TIMER4CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 0x00000001UL /**< Mode TIMER5CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 0x00000001UL /**< Mode TIMER6CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 0x00000001UL /**< Mode WTIMER1CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 0x00000001UL /**< Mode WTIMER2CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 0x00000001UL /**< Mode WTIMER3CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY 0x00000001UL /**< Mode EBIPXL1EMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY 0x00000002UL /**< Mode USART3TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY 0x00000002UL /**< Mode USART4TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY 0x00000002UL /**< Mode USART5TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY 0x00000002UL /**< Mode UART0TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY 0x00000002UL /**< Mode UART1TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000002UL /**< Mode TIMER4CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 0x00000002UL /**< Mode TIMER5CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 0x00000002UL /**< Mode TIMER6CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 0x00000002UL /**< Mode WTIMER1CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 0x00000002UL /**< Mode WTIMER2CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 0x00000002UL /**< Mode WTIMER3CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL 0x00000002UL /**< Mode EBIPXLFULL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT 0x00000003UL /**< Mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT 0x00000003UL /**< Mode USART4RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000003UL /**< Mode TIMER4CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 0x00000003UL /**< Mode TIMER5CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 0x00000003UL /**< Mode TIMER6CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 0x00000003UL /**< Mode WTIMER1CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 0x00000003UL /**< Mode WTIMER2CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 0x00000003UL /**< Mode WTIMER3CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY 0x00000003UL /**< Mode EBIDDEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT 0x00000004UL /**< Mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT 0x00000004UL /**< Mode USART4TXBLRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 0x00000004UL /**< Mode WTIMER1CC3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_EBIVSYNC 0x00000004UL /**< Mode EBIVSYNC for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_EBIHSYNC 0x00000005UL /**< Mode EBIHSYNC for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV << 0) /**< Shifted mode I2C2RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /**< Shifted mode TIMER4UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF << 0) /**< Shifted mode TIMER5UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF << 0) /**< Shifted mode TIMER6UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF << 0) /**< Shifted mode WTIMER1UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF << 0) /**< Shifted mode WTIMER2UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF << 0) /**< Shifted mode WTIMER3UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY << 0) /**< Shifted mode EBIPXL0EMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC1SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXBL (_LDMA_CH_REQSEL_SIGSEL_USART3TXBL << 0) /**< Shifted mode USART3TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART4TXBL (_LDMA_CH_REQSEL_SIGSEL_USART4TXBL << 0) /**< Shifted mode USART4TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART5TXBL (_LDMA_CH_REQSEL_SIGSEL_USART5TXBL << 0) /**< Shifted mode USART5TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_UART0TXBL (_LDMA_CH_REQSEL_SIGSEL_UART0TXBL << 0) /**< Shifted mode UART0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_UART1TXBL (_LDMA_CH_REQSEL_SIGSEL_UART1TXBL << 0) /**< Shifted mode UART1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C2TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C2TXBL << 0) /**< Shifted mode I2C2TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY << 0) /**< Shifted mode EBIPXL1EMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY << 0) /**< Shifted mode USART3TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY << 0) /**< Shifted mode USART4TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY << 0) /**< Shifted mode USART5TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY << 0) /**< Shifted mode UART0TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY << 0) /**< Shifted mode UART1TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL (_LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL << 0) /**< Shifted mode EBIPXLFULL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT << 0) /**< Shifted mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT << 0) /**< Shifted mode USART4RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY << 0) /**< Shifted mode EBIDDEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT << 0) /**< Shifted mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT << 0) /**< Shifted mode USART4TXBLRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_EBIVSYNC (_LDMA_CH_REQSEL_SIGSEL_EBIVSYNC << 0) /**< Shifted mode EBIVSYNC for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_EBIHSYNC (_LDMA_CH_REQSEL_SIGSEL_EBIHSYNC << 0) /**< Shifted mode EBIHSYNC for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_ADC1 0x00000009UL /**< Mode ADC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART3 0x0000000FUL /**< Mode USART3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART4 0x00000010UL /**< Mode USART4 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART5 0x00000011UL /**< Mode USART5 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_UART0 0x00000012UL /**< Mode UART0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_UART1 0x00000013UL /**< Mode UART1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000014UL /**< Mode LEUART0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_LEUART1 0x00000015UL /**< Mode LEUART1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000016UL /**< Mode I2C0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000017UL /**< Mode I2C1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_I2C2 0x00000018UL /**< Mode I2C2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000019UL /**< Mode TIMER0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x0000001AUL /**< Mode TIMER1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER2 0x0000001BUL /**< Mode TIMER2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER3 0x0000001CUL /**< Mode TIMER3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER4 0x0000001DUL /**< Mode TIMER4 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER5 0x0000001EUL /**< Mode TIMER5 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER6 0x0000001FUL /**< Mode TIMER6 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x00000020UL /**< Mode WTIMER0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER1 0x00000021UL /**< Mode WTIMER1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER2 0x00000022UL /**< Mode WTIMER2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER3 0x00000023UL /**< Mode WTIMER3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_EBI 0x00000032UL /**< Mode EBI for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x0000003DUL /**< Mode CSEN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x0000003EUL /**< Mode LESENSE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_ADC1 (_LDMA_CH_REQSEL_SOURCESEL_ADC1 << 16) /**< Shifted mode ADC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART3 (_LDMA_CH_REQSEL_SOURCESEL_USART3 << 16) /**< Shifted mode USART3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART4 (_LDMA_CH_REQSEL_SOURCESEL_USART4 << 16) /**< Shifted mode USART4 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART5 (_LDMA_CH_REQSEL_SOURCESEL_USART5 << 16) /**< Shifted mode USART5 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_UART0 (_LDMA_CH_REQSEL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_UART1 (_LDMA_CH_REQSEL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_LEUART1 (_LDMA_CH_REQSEL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_I2C2 (_LDMA_CH_REQSEL_SOURCESEL_I2C2 << 16) /**< Shifted mode I2C2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER2 (_LDMA_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER3 (_LDMA_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER4 (_LDMA_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted mode TIMER4 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER5 (_LDMA_CH_REQSEL_SOURCESEL_TIMER5 << 16) /**< Shifted mode TIMER5 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER6 (_LDMA_CH_REQSEL_SOURCESEL_TIMER6 << 16) /**< Shifted mode TIMER6 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER1 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER1 << 16) /**< Shifted mode WTIMER1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER2 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER2 << 16) /**< Shifted mode WTIMER2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER3 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER3 << 16) /**< Shifted mode WTIMER3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_EBI (_LDMA_CH_REQSEL_SOURCESEL_EBI << 16) /**< Shifted mode EBI for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */ +#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */ +#define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */ +#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} */ +/** @} End of group EFM32GG11B_LDMA */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma_ch.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma_ch.h new file mode 100644 index 0000000000000..625e713a349b0 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma_ch.h @@ -0,0 +1,65 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_LDMA_CH register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief LDMA_CH LDMA CH Register + * @ingroup EFM32GG11B_LDMA + ******************************************************************************/ +typedef struct { + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */ + uint32_t RESERVED0[5U]; /**< Reserved future */ +} LDMA_CH_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense.h new file mode 100644 index 0000000000000..8949df3c65784 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense.h @@ -0,0 +1,2003 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_LESENSE register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_LESENSE LESENSE + * @{ + * @brief EFM32GG11B_LESENSE Register Declaration + ******************************************************************************/ +/** LESENSE Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t TIMCTRL; /**< Timing Control Register */ + __IOM uint32_t PERCTRL; /**< Peripheral Control Register */ + __IOM uint32_t DECCTRL; /**< Decoder Control Register */ + __IOM uint32_t BIASCTRL; /**< Bias Control Register */ + __IOM uint32_t EVALCTRL; /**< LESENSE Evaluation Control */ + __IOM uint32_t PRSCTRL; /**< PRS Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t CHEN; /**< Channel Enable Register */ + __IOM uint32_t SCANRES; /**< Scan Result Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t PTR; /**< Result Buffer Pointers */ + __IM uint32_t BUFDATA; /**< Result Buffer Data Register */ + __IM uint32_t CURCH; /**< Current Channel Index */ + __IOM uint32_t DECSTATE; /**< Current Decoder State */ + __IOM uint32_t SENSORSTATE; /**< Decoder Input Register */ + __IOM uint32_t IDLECONF; /**< GPIO Idle Phase Configuration */ + __IOM uint32_t ALTEXCONF; /**< Alternative Excite Pin Configuration */ + uint32_t RESERVED0[2U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Register */ + + uint32_t RESERVED1[38U]; /**< Reserved registers */ + LESENSE_ST_TypeDef ST[32U]; /**< Decoding states */ + + LESENSE_BUF_TypeDef BUF[16U]; /**< Scanresult */ + + LESENSE_CH_TypeDef CH[16U]; /**< Scanconfig */ +} LESENSE_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_LESENSE + * @{ + * @defgroup EFM32GG11B_LESENSE_BitFields LESENSE Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for LESENSE CTRL */ +#define _LESENSE_CTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CTRL */ +#define _LESENSE_CTRL_MASK 0x007B29FFUL /**< Mask for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_DEFAULT (_LESENSE_CTRL_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PERIODIC (_LESENSE_CTRL_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_ONESHOT (_LESENSE_CTRL_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PRS (_LESENSE_CTRL_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_SHIFT 2 /**< Shift value for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_MASK 0x7CUL /**< Bit mask for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_DEFAULT (_LESENSE_CTRL_PRSSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH0 (_LESENSE_CTRL_PRSSEL_PRSCH0 << 2) /**< Shifted mode PRSCH0 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH1 (_LESENSE_CTRL_PRSSEL_PRSCH1 << 2) /**< Shifted mode PRSCH1 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH2 (_LESENSE_CTRL_PRSSEL_PRSCH2 << 2) /**< Shifted mode PRSCH2 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH3 (_LESENSE_CTRL_PRSSEL_PRSCH3 << 2) /**< Shifted mode PRSCH3 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH4 (_LESENSE_CTRL_PRSSEL_PRSCH4 << 2) /**< Shifted mode PRSCH4 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH5 (_LESENSE_CTRL_PRSSEL_PRSCH5 << 2) /**< Shifted mode PRSCH5 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH6 (_LESENSE_CTRL_PRSSEL_PRSCH6 << 2) /**< Shifted mode PRSCH6 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH7 (_LESENSE_CTRL_PRSSEL_PRSCH7 << 2) /**< Shifted mode PRSCH7 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH8 (_LESENSE_CTRL_PRSSEL_PRSCH8 << 2) /**< Shifted mode PRSCH8 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH9 (_LESENSE_CTRL_PRSSEL_PRSCH9 << 2) /**< Shifted mode PRSCH9 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH10 (_LESENSE_CTRL_PRSSEL_PRSCH10 << 2) /**< Shifted mode PRSCH10 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH11 (_LESENSE_CTRL_PRSSEL_PRSCH11 << 2) /**< Shifted mode PRSCH11 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH12 (_LESENSE_CTRL_PRSSEL_PRSCH12 << 2) /**< Shifted mode PRSCH12 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH13 (_LESENSE_CTRL_PRSSEL_PRSCH13 << 2) /**< Shifted mode PRSCH13 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH14 (_LESENSE_CTRL_PRSSEL_PRSCH14 << 2) /**< Shifted mode PRSCH14 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH15 (_LESENSE_CTRL_PRSSEL_PRSCH15 << 2) /**< Shifted mode PRSCH15 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH16 (_LESENSE_CTRL_PRSSEL_PRSCH16 << 2) /**< Shifted mode PRSCH16 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH17 (_LESENSE_CTRL_PRSSEL_PRSCH17 << 2) /**< Shifted mode PRSCH17 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH18 (_LESENSE_CTRL_PRSSEL_PRSCH18 << 2) /**< Shifted mode PRSCH18 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH19 (_LESENSE_CTRL_PRSSEL_PRSCH19 << 2) /**< Shifted mode PRSCH19 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH20 (_LESENSE_CTRL_PRSSEL_PRSCH20 << 2) /**< Shifted mode PRSCH20 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH21 (_LESENSE_CTRL_PRSSEL_PRSCH21 << 2) /**< Shifted mode PRSCH21 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH22 (_LESENSE_CTRL_PRSSEL_PRSCH22 << 2) /**< Shifted mode PRSCH22 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH23 (_LESENSE_CTRL_PRSSEL_PRSCH23 << 2) /**< Shifted mode PRSCH23 for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_SHIFT 7 /**< Shift value for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_MASK 0x180UL /**< Bit mask for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DEFAULT (_LESENSE_CTRL_SCANCONF_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DIRMAP (_LESENSE_CTRL_SCANCONF_DIRMAP << 7) /**< Shifted mode DIRMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_INVMAP (_LESENSE_CTRL_SCANCONF_INVMAP << 7) /**< Shifted mode INVMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_TOGGLE (_LESENSE_CTRL_SCANCONF_TOGGLE << 7) /**< Shifted mode TOGGLE for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DECDEF (_LESENSE_CTRL_SCANCONF_DECDEF << 7) /**< Shifted mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP (0x1UL << 11) /**< Alternative Excitation Map */ +#define _LESENSE_CTRL_ALTEXMAP_SHIFT 11 /**< Shift value for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_MASK 0x800UL /**< Bit mask for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_ALTEX 0x00000000UL /**< Mode ALTEX for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_CH 0x00000001UL /**< Mode CH for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_DEFAULT (_LESENSE_CTRL_ALTEXMAP_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_ALTEX (_LESENSE_CTRL_ALTEXMAP_ALTEX << 11) /**< Shifted mode ALTEX for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_CH (_LESENSE_CTRL_ALTEXMAP_CH << 11) /**< Shifted mode CH for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE (0x1UL << 13) /**< Enable Dual Sample Mode */ +#define _LESENSE_CTRL_DUALSAMPLE_SHIFT 13 /**< Shift value for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_MASK 0x2000UL /**< Bit mask for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE_DEFAULT (_LESENSE_CTRL_DUALSAMPLE_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW (0x1UL << 16) /**< Result Buffer Overwrite */ +#define _LESENSE_CTRL_BUFOW_SHIFT 16 /**< Shift value for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_MASK 0x10000UL /**< Bit mask for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW_DEFAULT (_LESENSE_CTRL_BUFOW_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES (0x1UL << 17) /**< Enable Storing of SCANRES */ +#define _LESENSE_CTRL_STRSCANRES_SHIFT 17 /**< Shift value for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_MASK 0x20000UL /**< Bit mask for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES_DEFAULT (_LESENSE_CTRL_STRSCANRES_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL (0x1UL << 19) /**< Result Buffer Interrupt and DMA Trigger Level */ +#define _LESENSE_CTRL_BUFIDL_SHIFT 19 /**< Shift value for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_MASK 0x80000UL /**< Bit mask for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_HALFFULL 0x00000000UL /**< Mode HALFFULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_FULL 0x00000001UL /**< Mode FULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_DEFAULT (_LESENSE_CTRL_BUFIDL_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_HALFFULL (_LESENSE_CTRL_BUFIDL_HALFFULL << 19) /**< Shifted mode HALFFULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_FULL (_LESENSE_CTRL_BUFIDL_FULL << 19) /**< Shifted mode FULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_SHIFT 20 /**< Shift value for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_MASK 0x300000UL /**< Bit mask for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFDATAV 0x00000001UL /**< Mode BUFDATAV for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFLEVEL 0x00000002UL /**< Mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DEFAULT (_LESENSE_CTRL_DMAWU_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DISABLE (_LESENSE_CTRL_DMAWU_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFDATAV (_LESENSE_CTRL_DMAWU_BUFDATAV << 20) /**< Shifted mode BUFDATAV for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFLEVEL (_LESENSE_CTRL_DMAWU_BUFLEVEL << 20) /**< Shifted mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN (0x1UL << 22) /**< Debug Mode Run Enable */ +#define _LESENSE_CTRL_DEBUGRUN_SHIFT 22 /**< Shift value for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_MASK 0x400000UL /**< Bit mask for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN_DEFAULT (_LESENSE_CTRL_DEBUGRUN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_CTRL */ + +/* Bit fields for LESENSE TIMCTRL */ +#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUXHFRCO Startup Configuration */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */ + +/* Bit fields for LESENSE PERCTRL */ +#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_MASK 0x3FF0014FUL /**< Mask for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0EN (0x1UL << 0) /**< VDAC CH0 Enable */ +#define _LESENSE_PERCTRL_DACCH0EN_SHIFT 0 /**< Shift value for LESENSE_DACCH0EN */ +#define _LESENSE_PERCTRL_DACCH0EN_MASK 0x1UL /**< Bit mask for LESENSE_DACCH0EN */ +#define _LESENSE_PERCTRL_DACCH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0EN_DEFAULT (_LESENSE_PERCTRL_DACCH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1EN (0x1UL << 1) /**< VDAC CH1 Enable */ +#define _LESENSE_PERCTRL_DACCH1EN_SHIFT 1 /**< Shift value for LESENSE_DACCH1EN */ +#define _LESENSE_PERCTRL_DACCH1EN_MASK 0x2UL /**< Bit mask for LESENSE_DACCH1EN */ +#define _LESENSE_PERCTRL_DACCH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1EN_DEFAULT (_LESENSE_PERCTRL_DACCH1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< VDAC CH0 Data Selection */ +#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA (0x1UL << 3) /**< VDAC CH1 Data Selection */ +#define _LESENSE_PERCTRL_DACCH1DATA_SHIFT 3 /**< Shift value for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_MASK 0x8UL /**< Bit mask for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DEFAULT (_LESENSE_PERCTRL_DACCH1DATA_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DACDATA (_LESENSE_PERCTRL_DACCH1DATA_DACDATA << 3) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_THRES (_LESENSE_PERCTRL_DACCH1DATA_THRES << 3) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< VDAC Startup Configuration */ +#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< VDAC Conversion Trigger Configuration */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x300000UL /**< Bit mask for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DISABLE (_LESENSE_PERCTRL_ACMP0MODE_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0xC00000UL /**< Bit mask for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DISABLE (_LESENSE_PERCTRL_ACMP1MODE_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert Analog Comparator 0 Output */ +#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert Analog Comparator 1 Output */ +#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0HYSTEN (0x1UL << 26) /**< ACMP0 Hysteresis Enable */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_SHIFT 26 /**< Shift value for LESENSE_ACMP0HYSTEN */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_MASK 0x4000000UL /**< Bit mask for LESENSE_ACMP0HYSTEN */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1HYSTEN (0x1UL << 27) /**< ACMP1 Hysteresis Enable */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_SHIFT 27 /**< Shift value for LESENSE_ACMP1HYSTEN */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_MASK 0x8000000UL /**< Bit mask for LESENSE_ACMP1HYSTEN */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT << 27) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_SHIFT 28 /**< Shift value for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_MASK 0x30000000UL /**< Bit mask for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM 0x00000001UL /**< Mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM 0x00000002UL /**< Mode KEEPDACWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM 0x00000003UL /**< Mode KEEPACMPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_DEFAULT (_LESENSE_PERCTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_NORMAL (_LESENSE_PERCTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM << 28) /**< Shifted mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM << 28) /**< Shifted mode KEEPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM << 28) /**< Shifted mode KEEPACMPDACWARM for LESENSE_PERCTRL */ + +/* Bit fields for LESENSE DECCTRL */ +#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_MASK 0x3FFFFDFFUL /**< Mask for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DISABLE (0x1UL << 0) /**< Disable the Decoder */ +#define _LESENSE_DECCTRL_DISABLE_SHIFT 0 /**< Shift value for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_MASK 0x1UL /**< Bit mask for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DISABLE_DEFAULT (_LESENSE_DECCTRL_DISABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK (0x1UL << 1) /**< Enable Check of Current State */ +#define _LESENSE_DECCTRL_ERRCHK_SHIFT 1 /**< Shift value for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_MASK 0x2UL /**< Bit mask for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK_DEFAULT (_LESENSE_DECCTRL_ERRCHK_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable Decoder to Channel Interrupt Mapping */ +#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable Decoder Hysteresis on PRS0 Output */ +#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable Decoder Hysteresis on PRS1 Output */ +#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable Decoder Hysteresis on PRS2 Output */ +#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable Decoder Hysteresis on Interrupt Requests */ +#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable Count Mode on Decoder PRS Channels 0 and 1 */ +#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT (0x1UL << 8) /**< LESENSE Decoder Input Configuration */ +#define _LESENSE_DECCTRL_INPUT_SHIFT 8 /**< Shift value for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_MASK 0x100UL /**< Bit mask for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_SENSORSTATE 0x00000000UL /**< Mode SENSORSTATE for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_PRS 0x00000001UL /**< Mode PRS for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_DEFAULT (_LESENSE_DECCTRL_INPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_SENSORSTATE (_LESENSE_DECCTRL_INPUT_SENSORSTATE << 8) /**< Shifted mode SENSORSTATE for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_PRS (_LESENSE_DECCTRL_INPUT_PRS << 8) /**< Shifted mode PRS for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_SHIFT 10 /**< Shift value for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_MASK 0x7C00UL /**< Bit mask for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_DEFAULT (_LESENSE_DECCTRL_PRSSEL0_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH0 (_LESENSE_DECCTRL_PRSSEL0_PRSCH0 << 10) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH1 (_LESENSE_DECCTRL_PRSSEL0_PRSCH1 << 10) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH2 (_LESENSE_DECCTRL_PRSSEL0_PRSCH2 << 10) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH3 (_LESENSE_DECCTRL_PRSSEL0_PRSCH3 << 10) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH4 (_LESENSE_DECCTRL_PRSSEL0_PRSCH4 << 10) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH5 (_LESENSE_DECCTRL_PRSSEL0_PRSCH5 << 10) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH6 (_LESENSE_DECCTRL_PRSSEL0_PRSCH6 << 10) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH7 (_LESENSE_DECCTRL_PRSSEL0_PRSCH7 << 10) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH8 (_LESENSE_DECCTRL_PRSSEL0_PRSCH8 << 10) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH9 (_LESENSE_DECCTRL_PRSSEL0_PRSCH9 << 10) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH10 (_LESENSE_DECCTRL_PRSSEL0_PRSCH10 << 10) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH11 (_LESENSE_DECCTRL_PRSSEL0_PRSCH11 << 10) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH12 (_LESENSE_DECCTRL_PRSSEL0_PRSCH12 << 10) /**< Shifted mode PRSCH12 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH13 (_LESENSE_DECCTRL_PRSSEL0_PRSCH13 << 10) /**< Shifted mode PRSCH13 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH14 (_LESENSE_DECCTRL_PRSSEL0_PRSCH14 << 10) /**< Shifted mode PRSCH14 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH15 (_LESENSE_DECCTRL_PRSSEL0_PRSCH15 << 10) /**< Shifted mode PRSCH15 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH16 (_LESENSE_DECCTRL_PRSSEL0_PRSCH16 << 10) /**< Shifted mode PRSCH16 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH17 (_LESENSE_DECCTRL_PRSSEL0_PRSCH17 << 10) /**< Shifted mode PRSCH17 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH18 (_LESENSE_DECCTRL_PRSSEL0_PRSCH18 << 10) /**< Shifted mode PRSCH18 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH19 (_LESENSE_DECCTRL_PRSSEL0_PRSCH19 << 10) /**< Shifted mode PRSCH19 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH20 (_LESENSE_DECCTRL_PRSSEL0_PRSCH20 << 10) /**< Shifted mode PRSCH20 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH21 (_LESENSE_DECCTRL_PRSSEL0_PRSCH21 << 10) /**< Shifted mode PRSCH21 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH22 (_LESENSE_DECCTRL_PRSSEL0_PRSCH22 << 10) /**< Shifted mode PRSCH22 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH23 (_LESENSE_DECCTRL_PRSSEL0_PRSCH23 << 10) /**< Shifted mode PRSCH23 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_SHIFT 15 /**< Shift value for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_MASK 0xF8000UL /**< Bit mask for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_DEFAULT (_LESENSE_DECCTRL_PRSSEL1_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH0 (_LESENSE_DECCTRL_PRSSEL1_PRSCH0 << 15) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH1 (_LESENSE_DECCTRL_PRSSEL1_PRSCH1 << 15) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH2 (_LESENSE_DECCTRL_PRSSEL1_PRSCH2 << 15) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH3 (_LESENSE_DECCTRL_PRSSEL1_PRSCH3 << 15) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH4 (_LESENSE_DECCTRL_PRSSEL1_PRSCH4 << 15) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH5 (_LESENSE_DECCTRL_PRSSEL1_PRSCH5 << 15) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH6 (_LESENSE_DECCTRL_PRSSEL1_PRSCH6 << 15) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH7 (_LESENSE_DECCTRL_PRSSEL1_PRSCH7 << 15) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH8 (_LESENSE_DECCTRL_PRSSEL1_PRSCH8 << 15) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH9 (_LESENSE_DECCTRL_PRSSEL1_PRSCH9 << 15) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH10 (_LESENSE_DECCTRL_PRSSEL1_PRSCH10 << 15) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH11 (_LESENSE_DECCTRL_PRSSEL1_PRSCH11 << 15) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH12 (_LESENSE_DECCTRL_PRSSEL1_PRSCH12 << 15) /**< Shifted mode PRSCH12 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH13 (_LESENSE_DECCTRL_PRSSEL1_PRSCH13 << 15) /**< Shifted mode PRSCH13 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH14 (_LESENSE_DECCTRL_PRSSEL1_PRSCH14 << 15) /**< Shifted mode PRSCH14 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH15 (_LESENSE_DECCTRL_PRSSEL1_PRSCH15 << 15) /**< Shifted mode PRSCH15 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH16 (_LESENSE_DECCTRL_PRSSEL1_PRSCH16 << 15) /**< Shifted mode PRSCH16 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH17 (_LESENSE_DECCTRL_PRSSEL1_PRSCH17 << 15) /**< Shifted mode PRSCH17 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH18 (_LESENSE_DECCTRL_PRSSEL1_PRSCH18 << 15) /**< Shifted mode PRSCH18 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH19 (_LESENSE_DECCTRL_PRSSEL1_PRSCH19 << 15) /**< Shifted mode PRSCH19 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH20 (_LESENSE_DECCTRL_PRSSEL1_PRSCH20 << 15) /**< Shifted mode PRSCH20 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH21 (_LESENSE_DECCTRL_PRSSEL1_PRSCH21 << 15) /**< Shifted mode PRSCH21 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH22 (_LESENSE_DECCTRL_PRSSEL1_PRSCH22 << 15) /**< Shifted mode PRSCH22 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH23 (_LESENSE_DECCTRL_PRSSEL1_PRSCH23 << 15) /**< Shifted mode PRSCH23 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_SHIFT 20 /**< Shift value for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_MASK 0x1F00000UL /**< Bit mask for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_DEFAULT (_LESENSE_DECCTRL_PRSSEL2_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH0 (_LESENSE_DECCTRL_PRSSEL2_PRSCH0 << 20) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH1 (_LESENSE_DECCTRL_PRSSEL2_PRSCH1 << 20) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH2 (_LESENSE_DECCTRL_PRSSEL2_PRSCH2 << 20) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH3 (_LESENSE_DECCTRL_PRSSEL2_PRSCH3 << 20) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH4 (_LESENSE_DECCTRL_PRSSEL2_PRSCH4 << 20) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH5 (_LESENSE_DECCTRL_PRSSEL2_PRSCH5 << 20) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH6 (_LESENSE_DECCTRL_PRSSEL2_PRSCH6 << 20) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH7 (_LESENSE_DECCTRL_PRSSEL2_PRSCH7 << 20) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH8 (_LESENSE_DECCTRL_PRSSEL2_PRSCH8 << 20) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH9 (_LESENSE_DECCTRL_PRSSEL2_PRSCH9 << 20) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH10 (_LESENSE_DECCTRL_PRSSEL2_PRSCH10 << 20) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH11 (_LESENSE_DECCTRL_PRSSEL2_PRSCH11 << 20) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH12 (_LESENSE_DECCTRL_PRSSEL2_PRSCH12 << 20) /**< Shifted mode PRSCH12 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH13 (_LESENSE_DECCTRL_PRSSEL2_PRSCH13 << 20) /**< Shifted mode PRSCH13 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH14 (_LESENSE_DECCTRL_PRSSEL2_PRSCH14 << 20) /**< Shifted mode PRSCH14 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH15 (_LESENSE_DECCTRL_PRSSEL2_PRSCH15 << 20) /**< Shifted mode PRSCH15 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH16 (_LESENSE_DECCTRL_PRSSEL2_PRSCH16 << 20) /**< Shifted mode PRSCH16 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH17 (_LESENSE_DECCTRL_PRSSEL2_PRSCH17 << 20) /**< Shifted mode PRSCH17 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH18 (_LESENSE_DECCTRL_PRSSEL2_PRSCH18 << 20) /**< Shifted mode PRSCH18 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH19 (_LESENSE_DECCTRL_PRSSEL2_PRSCH19 << 20) /**< Shifted mode PRSCH19 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH20 (_LESENSE_DECCTRL_PRSSEL2_PRSCH20 << 20) /**< Shifted mode PRSCH20 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH21 (_LESENSE_DECCTRL_PRSSEL2_PRSCH21 << 20) /**< Shifted mode PRSCH21 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH22 (_LESENSE_DECCTRL_PRSSEL2_PRSCH22 << 20) /**< Shifted mode PRSCH22 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH23 (_LESENSE_DECCTRL_PRSSEL2_PRSCH23 << 20) /**< Shifted mode PRSCH23 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_SHIFT 25 /**< Shift value for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_MASK 0x3E000000UL /**< Bit mask for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_DEFAULT (_LESENSE_DECCTRL_PRSSEL3_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH0 (_LESENSE_DECCTRL_PRSSEL3_PRSCH0 << 25) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH1 (_LESENSE_DECCTRL_PRSSEL3_PRSCH1 << 25) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH2 (_LESENSE_DECCTRL_PRSSEL3_PRSCH2 << 25) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH3 (_LESENSE_DECCTRL_PRSSEL3_PRSCH3 << 25) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH4 (_LESENSE_DECCTRL_PRSSEL3_PRSCH4 << 25) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH5 (_LESENSE_DECCTRL_PRSSEL3_PRSCH5 << 25) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH6 (_LESENSE_DECCTRL_PRSSEL3_PRSCH6 << 25) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH7 (_LESENSE_DECCTRL_PRSSEL3_PRSCH7 << 25) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH8 (_LESENSE_DECCTRL_PRSSEL3_PRSCH8 << 25) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH9 (_LESENSE_DECCTRL_PRSSEL3_PRSCH9 << 25) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH10 (_LESENSE_DECCTRL_PRSSEL3_PRSCH10 << 25) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH11 (_LESENSE_DECCTRL_PRSSEL3_PRSCH11 << 25) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH12 (_LESENSE_DECCTRL_PRSSEL3_PRSCH12 << 25) /**< Shifted mode PRSCH12 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH13 (_LESENSE_DECCTRL_PRSSEL3_PRSCH13 << 25) /**< Shifted mode PRSCH13 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH14 (_LESENSE_DECCTRL_PRSSEL3_PRSCH14 << 25) /**< Shifted mode PRSCH14 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH15 (_LESENSE_DECCTRL_PRSSEL3_PRSCH15 << 25) /**< Shifted mode PRSCH15 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH16 (_LESENSE_DECCTRL_PRSSEL3_PRSCH16 << 25) /**< Shifted mode PRSCH16 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH17 (_LESENSE_DECCTRL_PRSSEL3_PRSCH17 << 25) /**< Shifted mode PRSCH17 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH18 (_LESENSE_DECCTRL_PRSSEL3_PRSCH18 << 25) /**< Shifted mode PRSCH18 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH19 (_LESENSE_DECCTRL_PRSSEL3_PRSCH19 << 25) /**< Shifted mode PRSCH19 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH20 (_LESENSE_DECCTRL_PRSSEL3_PRSCH20 << 25) /**< Shifted mode PRSCH20 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH21 (_LESENSE_DECCTRL_PRSSEL3_PRSCH21 << 25) /**< Shifted mode PRSCH21 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH22 (_LESENSE_DECCTRL_PRSSEL3_PRSCH22 << 25) /**< Shifted mode PRSCH22 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH23 (_LESENSE_DECCTRL_PRSSEL3_PRSCH23 << 25) /**< Shifted mode PRSCH23 for LESENSE_DECCTRL */ + +/* Bit fields for LESENSE BIASCTRL */ +#define _LESENSE_BIASCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_MASK 0x00000003UL /**< Mask for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_SHIFT 0 /**< Shift value for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_MASK 0x3UL /**< Bit mask for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DONTTOUCH 0x00000000UL /**< Mode DONTTOUCH for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE 0x00000001UL /**< Mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_HIGHACC 0x00000002UL /**< Mode HIGHACC for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DEFAULT (_LESENSE_BIASCTRL_BIASMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DONTTOUCH (_LESENSE_BIASCTRL_BIASMODE_DONTTOUCH << 0) /**< Shifted mode DONTTOUCH for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE (_LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE << 0) /**< Shifted mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_HIGHACC (_LESENSE_BIASCTRL_BIASMODE_HIGHACC << 0) /**< Shifted mode HIGHACC for LESENSE_BIASCTRL */ + +/* Bit fields for LESENSE EVALCTRL */ +#define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */ +#define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */ + +/* Bit fields for LESENSE PRSCTRL */ +#define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS Output DECCMP */ +#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ + +/* Bit fields for LESENSE CMD */ +#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */ +#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */ +#define LESENSE_CMD_START (0x1UL << 0) /**< Start Scanning of Sensors */ +#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */ +#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */ +#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop Scanning of Sensors */ +#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start Decoder */ +#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear Result Buffer */ +#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */ + +/* Bit fields for LESENSE CHEN */ +#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */ +#define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */ +#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */ + +/* Bit fields for LESENSE SCANRES */ +#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ + +/* Bit fields for LESENSE STATUS */ +#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */ +#define _LESENSE_STATUS_MASK 0x0000003FUL /**< Mask for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFDATAV (0x1UL << 0) /**< Result Data Valid */ +#define _LESENSE_STATUS_BUFDATAV_SHIFT 0 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_MASK 0x1UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFDATAV_DEFAULT (_LESENSE_STATUS_BUFDATAV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL (0x1UL << 1) /**< Result Buffer Half Full */ +#define _LESENSE_STATUS_BUFHALFFULL_SHIFT 1 /**< Shift value for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_MASK 0x2UL /**< Bit mask for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL_DEFAULT (_LESENSE_STATUS_BUFHALFFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL (0x1UL << 2) /**< Result Buffer Full */ +#define _LESENSE_STATUS_BUFFULL_SHIFT 2 /**< Shift value for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_MASK 0x4UL /**< Bit mask for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL_DEFAULT (_LESENSE_STATUS_BUFFULL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING (0x1UL << 3) /**< LESENSE Periodic Counter Running */ +#define _LESENSE_STATUS_RUNNING_SHIFT 3 /**< Shift value for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_MASK 0x8UL /**< Bit mask for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE (0x1UL << 4) /**< LESENSE Scan Active */ +#define _LESENSE_STATUS_SCANACTIVE_SHIFT 4 /**< Shift value for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_MASK 0x10UL /**< Bit mask for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE (0x1UL << 5) /**< LESENSE VDAC Interface is Active */ +#define _LESENSE_STATUS_DACACTIVE_SHIFT 5 /**< Shift value for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_MASK 0x20UL /**< Bit mask for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE_DEFAULT (_LESENSE_STATUS_DACACTIVE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */ + +/* Bit fields for LESENSE PTR */ +#define _LESENSE_PTR_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PTR */ +#define _LESENSE_PTR_MASK 0x000000FFUL /**< Mask for LESENSE_PTR */ +#define _LESENSE_PTR_RD_SHIFT 0 /**< Shift value for LESENSE_RD */ +#define _LESENSE_PTR_RD_MASK 0xFUL /**< Bit mask for LESENSE_RD */ +#define _LESENSE_PTR_RD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_RD_DEFAULT (_LESENSE_PTR_RD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PTR */ +#define _LESENSE_PTR_WR_SHIFT 4 /**< Shift value for LESENSE_WR */ +#define _LESENSE_PTR_WR_MASK 0xF0UL /**< Bit mask for LESENSE_WR */ +#define _LESENSE_PTR_WR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_WR_DEFAULT (_LESENSE_PTR_WR_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_PTR */ + +/* Bit fields for LESENSE BUFDATA */ +#define _LESENSE_BUFDATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_SHIFT 0 /**< Shift value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ +#define LESENSE_BUFDATA_BUFDATA_DEFAULT (_LESENSE_BUFDATA_BUFDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATASRC_SHIFT 16 /**< Shift value for LESENSE_BUFDATASRC */ +#define _LESENSE_BUFDATA_BUFDATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_BUFDATASRC */ +#define _LESENSE_BUFDATA_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ +#define LESENSE_BUFDATA_BUFDATASRC_DEFAULT (_LESENSE_BUFDATA_BUFDATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ + +/* Bit fields for LESENSE CURCH */ +#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */ +#define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */ +#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */ + +/* Bit fields for LESENSE DECSTATE */ +#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */ +#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */ + +/* Bit fields for LESENSE SENSORSTATE */ +#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */ +#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE */ + +/* Bit fields for LESENSE IDLECONF */ +#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_MASK 0x3UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DEFAULT (_LESENSE_IDLECONF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DISABLE (_LESENSE_IDLECONF_CH0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_HIGH (_LESENSE_IDLECONF_CH0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_LOW (_LESENSE_IDLECONF_CH0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DAC (_LESENSE_IDLECONF_CH0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_SHIFT 2 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_MASK 0xCUL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DEFAULT (_LESENSE_IDLECONF_CH1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DISABLE (_LESENSE_IDLECONF_CH1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_HIGH (_LESENSE_IDLECONF_CH1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_LOW (_LESENSE_IDLECONF_CH1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DAC (_LESENSE_IDLECONF_CH1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_SHIFT 4 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_MASK 0x30UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DEFAULT (_LESENSE_IDLECONF_CH2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DISABLE (_LESENSE_IDLECONF_CH2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_HIGH (_LESENSE_IDLECONF_CH2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_LOW (_LESENSE_IDLECONF_CH2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DAC (_LESENSE_IDLECONF_CH2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_SHIFT 6 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_MASK 0xC0UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DEFAULT (_LESENSE_IDLECONF_CH3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DISABLE (_LESENSE_IDLECONF_CH3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_HIGH (_LESENSE_IDLECONF_CH3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_LOW (_LESENSE_IDLECONF_CH3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DAC (_LESENSE_IDLECONF_CH3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_SHIFT 8 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_MASK 0x300UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DEFAULT (_LESENSE_IDLECONF_CH4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DISABLE (_LESENSE_IDLECONF_CH4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_HIGH (_LESENSE_IDLECONF_CH4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_LOW (_LESENSE_IDLECONF_CH4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DAC (_LESENSE_IDLECONF_CH4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_SHIFT 10 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_MASK 0xC00UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DEFAULT (_LESENSE_IDLECONF_CH5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DISABLE (_LESENSE_IDLECONF_CH5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_HIGH (_LESENSE_IDLECONF_CH5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_LOW (_LESENSE_IDLECONF_CH5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DAC (_LESENSE_IDLECONF_CH5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_SHIFT 12 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_MASK 0x3000UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DEFAULT (_LESENSE_IDLECONF_CH6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DISABLE (_LESENSE_IDLECONF_CH6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_HIGH (_LESENSE_IDLECONF_CH6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_LOW (_LESENSE_IDLECONF_CH6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DAC (_LESENSE_IDLECONF_CH6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_SHIFT 14 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_MASK 0xC000UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DEFAULT (_LESENSE_IDLECONF_CH7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DISABLE (_LESENSE_IDLECONF_CH7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_HIGH (_LESENSE_IDLECONF_CH7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_LOW (_LESENSE_IDLECONF_CH7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DAC (_LESENSE_IDLECONF_CH7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_SHIFT 16 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_MASK 0x30000UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DEFAULT (_LESENSE_IDLECONF_CH8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DISABLE (_LESENSE_IDLECONF_CH8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_HIGH (_LESENSE_IDLECONF_CH8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_LOW (_LESENSE_IDLECONF_CH8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DAC (_LESENSE_IDLECONF_CH8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_SHIFT 18 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_MASK 0xC0000UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DEFAULT (_LESENSE_IDLECONF_CH9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DISABLE (_LESENSE_IDLECONF_CH9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_HIGH (_LESENSE_IDLECONF_CH9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_LOW (_LESENSE_IDLECONF_CH9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DAC (_LESENSE_IDLECONF_CH9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_SHIFT 20 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_MASK 0x300000UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DEFAULT (_LESENSE_IDLECONF_CH10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DISABLE (_LESENSE_IDLECONF_CH10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_HIGH (_LESENSE_IDLECONF_CH10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_LOW (_LESENSE_IDLECONF_CH10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DAC (_LESENSE_IDLECONF_CH10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_SHIFT 22 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_MASK 0xC00000UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DEFAULT (_LESENSE_IDLECONF_CH11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DISABLE (_LESENSE_IDLECONF_CH11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_HIGH (_LESENSE_IDLECONF_CH11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_LOW (_LESENSE_IDLECONF_CH11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DAC (_LESENSE_IDLECONF_CH11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_SHIFT 24 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_MASK 0x3000000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DEFAULT (_LESENSE_IDLECONF_CH12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DISABLE (_LESENSE_IDLECONF_CH12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_HIGH (_LESENSE_IDLECONF_CH12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_LOW (_LESENSE_IDLECONF_CH12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DAC (_LESENSE_IDLECONF_CH12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_SHIFT 26 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_MASK 0xC000000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DEFAULT (_LESENSE_IDLECONF_CH13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DISABLE (_LESENSE_IDLECONF_CH13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_HIGH (_LESENSE_IDLECONF_CH13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_LOW (_LESENSE_IDLECONF_CH13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DAC (_LESENSE_IDLECONF_CH13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_SHIFT 28 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_MASK 0x30000000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DEFAULT (_LESENSE_IDLECONF_CH14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DISABLE (_LESENSE_IDLECONF_CH14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_HIGH (_LESENSE_IDLECONF_CH14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_LOW (_LESENSE_IDLECONF_CH14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DAC (_LESENSE_IDLECONF_CH14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_SHIFT 30 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DEFAULT (_LESENSE_IDLECONF_CH15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DISABLE (_LESENSE_IDLECONF_CH15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_HIGH (_LESENSE_IDLECONF_CH15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_LOW (_LESENSE_IDLECONF_CH15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DAC (_LESENSE_IDLECONF_CH15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */ + +/* Bit fields for LESENSE ALTEXCONF */ +#define _LESENSE_ALTEXCONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_SHIFT 0 /**< Shift value for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_MASK 0x3UL /**< Bit mask for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DISABLE (_LESENSE_ALTEXCONF_IDLECONF0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_HIGH (_LESENSE_ALTEXCONF_IDLECONF0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_LOW (_LESENSE_ALTEXCONF_IDLECONF0_LOW << 0) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_SHIFT 2 /**< Shift value for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_MASK 0xCUL /**< Bit mask for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DISABLE (_LESENSE_ALTEXCONF_IDLECONF1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_HIGH (_LESENSE_ALTEXCONF_IDLECONF1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_LOW (_LESENSE_ALTEXCONF_IDLECONF1_LOW << 2) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_SHIFT 4 /**< Shift value for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_MASK 0x30UL /**< Bit mask for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DISABLE (_LESENSE_ALTEXCONF_IDLECONF2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_HIGH (_LESENSE_ALTEXCONF_IDLECONF2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_LOW (_LESENSE_ALTEXCONF_IDLECONF2_LOW << 4) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_SHIFT 6 /**< Shift value for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_MASK 0xC0UL /**< Bit mask for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DISABLE (_LESENSE_ALTEXCONF_IDLECONF3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_HIGH (_LESENSE_ALTEXCONF_IDLECONF3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_LOW (_LESENSE_ALTEXCONF_IDLECONF3_LOW << 6) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_SHIFT 8 /**< Shift value for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_MASK 0x300UL /**< Bit mask for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DISABLE (_LESENSE_ALTEXCONF_IDLECONF4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_HIGH (_LESENSE_ALTEXCONF_IDLECONF4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_LOW (_LESENSE_ALTEXCONF_IDLECONF4_LOW << 8) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_SHIFT 10 /**< Shift value for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_MASK 0xC00UL /**< Bit mask for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DISABLE (_LESENSE_ALTEXCONF_IDLECONF5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_HIGH (_LESENSE_ALTEXCONF_IDLECONF5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_LOW (_LESENSE_ALTEXCONF_IDLECONF5_LOW << 10) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_SHIFT 12 /**< Shift value for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_MASK 0x3000UL /**< Bit mask for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DISABLE (_LESENSE_ALTEXCONF_IDLECONF6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_HIGH (_LESENSE_ALTEXCONF_IDLECONF6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_LOW (_LESENSE_ALTEXCONF_IDLECONF6_LOW << 12) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_SHIFT 14 /**< Shift value for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_MASK 0xC000UL /**< Bit mask for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DISABLE (_LESENSE_ALTEXCONF_IDLECONF7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_HIGH (_LESENSE_ALTEXCONF_IDLECONF7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_LOW (_LESENSE_ALTEXCONF_IDLECONF7_LOW << 14) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0 (0x1UL << 16) /**< ALTEX0 Always Excite Enable */ +#define _LESENSE_ALTEXCONF_AEX0_SHIFT 16 /**< Shift value for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_MASK 0x10000UL /**< Bit mask for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0_DEFAULT (_LESENSE_ALTEXCONF_AEX0_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1 (0x1UL << 17) /**< ALTEX1 Always Excite Enable */ +#define _LESENSE_ALTEXCONF_AEX1_SHIFT 17 /**< Shift value for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_MASK 0x20000UL /**< Bit mask for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1_DEFAULT (_LESENSE_ALTEXCONF_AEX1_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2 (0x1UL << 18) /**< ALTEX2 Always Excite Enable */ +#define _LESENSE_ALTEXCONF_AEX2_SHIFT 18 /**< Shift value for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_MASK 0x40000UL /**< Bit mask for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2_DEFAULT (_LESENSE_ALTEXCONF_AEX2_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3 (0x1UL << 19) /**< ALTEX3 Always Excite Enable */ +#define _LESENSE_ALTEXCONF_AEX3_SHIFT 19 /**< Shift value for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_MASK 0x80000UL /**< Bit mask for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3_DEFAULT (_LESENSE_ALTEXCONF_AEX3_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4 (0x1UL << 20) /**< ALTEX4 Always Excite Enable */ +#define _LESENSE_ALTEXCONF_AEX4_SHIFT 20 /**< Shift value for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_MASK 0x100000UL /**< Bit mask for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4_DEFAULT (_LESENSE_ALTEXCONF_AEX4_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5 (0x1UL << 21) /**< ALTEX5 Always Excite Enable */ +#define _LESENSE_ALTEXCONF_AEX5_SHIFT 21 /**< Shift value for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_MASK 0x200000UL /**< Bit mask for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5_DEFAULT (_LESENSE_ALTEXCONF_AEX5_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6 (0x1UL << 22) /**< ALTEX6 Always Excite Enable */ +#define _LESENSE_ALTEXCONF_AEX6_SHIFT 22 /**< Shift value for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_MASK 0x400000UL /**< Bit mask for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6_DEFAULT (_LESENSE_ALTEXCONF_AEX6_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7 (0x1UL << 23) /**< ALTEX7 Always Excite Enable */ +#define _LESENSE_ALTEXCONF_AEX7_SHIFT 23 /**< Shift value for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_MASK 0x800000UL /**< Bit mask for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7_DEFAULT (_LESENSE_ALTEXCONF_AEX7_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ + +/* Bit fields for LESENSE IF */ +#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */ +#define _LESENSE_IF_MASK 0x007FFFFFUL /**< Mask for LESENSE_IF */ +#define LESENSE_IF_CH0 (0x1UL << 0) /**< CH0 Interrupt Flag */ +#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1 (0x1UL << 1) /**< CH1 Interrupt Flag */ +#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2 (0x1UL << 2) /**< CH2 Interrupt Flag */ +#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3 (0x1UL << 3) /**< CH3 Interrupt Flag */ +#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4 (0x1UL << 4) /**< CH4 Interrupt Flag */ +#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5 (0x1UL << 5) /**< CH5 Interrupt Flag */ +#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6 (0x1UL << 6) /**< CH6 Interrupt Flag */ +#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7 (0x1UL << 7) /**< CH7 Interrupt Flag */ +#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8 (0x1UL << 8) /**< CH8 Interrupt Flag */ +#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9 (0x1UL << 9) /**< CH9 Interrupt Flag */ +#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10 (0x1UL << 10) /**< CH10 Interrupt Flag */ +#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11 (0x1UL << 11) /**< CH11 Interrupt Flag */ +#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12 (0x1UL << 12) /**< CH12 Interrupt Flag */ +#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13 (0x1UL << 13) /**< CH13 Interrupt Flag */ +#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14 (0x1UL << 14) /**< CH14 Interrupt Flag */ +#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15 (0x1UL << 15) /**< CH15 Interrupt Flag */ +#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE Interrupt Flag */ +#define _LESENSE_IF_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE_DEFAULT (_LESENSE_IF_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC (0x1UL << 17) /**< DEC Interrupt Flag */ +#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR (0x1UL << 18) /**< DECERR Interrupt Flag */ +#define _LESENSE_IF_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR_DEFAULT (_LESENSE_IF_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV (0x1UL << 19) /**< BUFDATAV Interrupt Flag */ +#define _LESENSE_IF_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV_DEFAULT (_LESENSE_IF_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL Interrupt Flag */ +#define _LESENSE_IF_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL_DEFAULT (_LESENSE_IF_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF (0x1UL << 21) /**< BUFOF Interrupt Flag */ +#define _LESENSE_IF_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF_DEFAULT (_LESENSE_IF_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF (0x1UL << 22) /**< CNTOF Interrupt Flag */ +#define _LESENSE_IF_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IF */ + +/* Bit fields for LESENSE IFS */ +#define _LESENSE_IFS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFS */ +#define _LESENSE_IFS_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFS */ +#define LESENSE_IFS_CH0 (0x1UL << 0) /**< Set CH0 Interrupt Flag */ +#define _LESENSE_IFS_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH0_DEFAULT (_LESENSE_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1 (0x1UL << 1) /**< Set CH1 Interrupt Flag */ +#define _LESENSE_IFS_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1_DEFAULT (_LESENSE_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2 (0x1UL << 2) /**< Set CH2 Interrupt Flag */ +#define _LESENSE_IFS_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2_DEFAULT (_LESENSE_IFS_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3 (0x1UL << 3) /**< Set CH3 Interrupt Flag */ +#define _LESENSE_IFS_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3_DEFAULT (_LESENSE_IFS_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4 (0x1UL << 4) /**< Set CH4 Interrupt Flag */ +#define _LESENSE_IFS_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4_DEFAULT (_LESENSE_IFS_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5 (0x1UL << 5) /**< Set CH5 Interrupt Flag */ +#define _LESENSE_IFS_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5_DEFAULT (_LESENSE_IFS_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6 (0x1UL << 6) /**< Set CH6 Interrupt Flag */ +#define _LESENSE_IFS_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6_DEFAULT (_LESENSE_IFS_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7 (0x1UL << 7) /**< Set CH7 Interrupt Flag */ +#define _LESENSE_IFS_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7_DEFAULT (_LESENSE_IFS_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8 (0x1UL << 8) /**< Set CH8 Interrupt Flag */ +#define _LESENSE_IFS_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8_DEFAULT (_LESENSE_IFS_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9 (0x1UL << 9) /**< Set CH9 Interrupt Flag */ +#define _LESENSE_IFS_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9_DEFAULT (_LESENSE_IFS_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10 (0x1UL << 10) /**< Set CH10 Interrupt Flag */ +#define _LESENSE_IFS_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10_DEFAULT (_LESENSE_IFS_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11 (0x1UL << 11) /**< Set CH11 Interrupt Flag */ +#define _LESENSE_IFS_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11_DEFAULT (_LESENSE_IFS_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12 (0x1UL << 12) /**< Set CH12 Interrupt Flag */ +#define _LESENSE_IFS_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12_DEFAULT (_LESENSE_IFS_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13 (0x1UL << 13) /**< Set CH13 Interrupt Flag */ +#define _LESENSE_IFS_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13_DEFAULT (_LESENSE_IFS_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14 (0x1UL << 14) /**< Set CH14 Interrupt Flag */ +#define _LESENSE_IFS_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14_DEFAULT (_LESENSE_IFS_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15 (0x1UL << 15) /**< Set CH15 Interrupt Flag */ +#define _LESENSE_IFS_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15_DEFAULT (_LESENSE_IFS_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE (0x1UL << 16) /**< Set SCANCOMPLETE Interrupt Flag */ +#define _LESENSE_IFS_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE_DEFAULT (_LESENSE_IFS_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC (0x1UL << 17) /**< Set DEC Interrupt Flag */ +#define _LESENSE_IFS_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC_DEFAULT (_LESENSE_IFS_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR (0x1UL << 18) /**< Set DECERR Interrupt Flag */ +#define _LESENSE_IFS_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR_DEFAULT (_LESENSE_IFS_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV (0x1UL << 19) /**< Set BUFDATAV Interrupt Flag */ +#define _LESENSE_IFS_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV_DEFAULT (_LESENSE_IFS_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL (0x1UL << 20) /**< Set BUFLEVEL Interrupt Flag */ +#define _LESENSE_IFS_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL_DEFAULT (_LESENSE_IFS_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF (0x1UL << 21) /**< Set BUFOF Interrupt Flag */ +#define _LESENSE_IFS_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF_DEFAULT (_LESENSE_IFS_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF (0x1UL << 22) /**< Set CNTOF Interrupt Flag */ +#define _LESENSE_IFS_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF_DEFAULT (_LESENSE_IFS_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFS */ + +/* Bit fields for LESENSE IFC */ +#define _LESENSE_IFC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFC */ +#define _LESENSE_IFC_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFC */ +#define LESENSE_IFC_CH0 (0x1UL << 0) /**< Clear CH0 Interrupt Flag */ +#define _LESENSE_IFC_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH0_DEFAULT (_LESENSE_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1 (0x1UL << 1) /**< Clear CH1 Interrupt Flag */ +#define _LESENSE_IFC_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1_DEFAULT (_LESENSE_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2 (0x1UL << 2) /**< Clear CH2 Interrupt Flag */ +#define _LESENSE_IFC_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2_DEFAULT (_LESENSE_IFC_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3 (0x1UL << 3) /**< Clear CH3 Interrupt Flag */ +#define _LESENSE_IFC_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3_DEFAULT (_LESENSE_IFC_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4 (0x1UL << 4) /**< Clear CH4 Interrupt Flag */ +#define _LESENSE_IFC_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4_DEFAULT (_LESENSE_IFC_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5 (0x1UL << 5) /**< Clear CH5 Interrupt Flag */ +#define _LESENSE_IFC_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5_DEFAULT (_LESENSE_IFC_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6 (0x1UL << 6) /**< Clear CH6 Interrupt Flag */ +#define _LESENSE_IFC_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6_DEFAULT (_LESENSE_IFC_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7 (0x1UL << 7) /**< Clear CH7 Interrupt Flag */ +#define _LESENSE_IFC_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7_DEFAULT (_LESENSE_IFC_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8 (0x1UL << 8) /**< Clear CH8 Interrupt Flag */ +#define _LESENSE_IFC_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8_DEFAULT (_LESENSE_IFC_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9 (0x1UL << 9) /**< Clear CH9 Interrupt Flag */ +#define _LESENSE_IFC_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9_DEFAULT (_LESENSE_IFC_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10 (0x1UL << 10) /**< Clear CH10 Interrupt Flag */ +#define _LESENSE_IFC_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10_DEFAULT (_LESENSE_IFC_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11 (0x1UL << 11) /**< Clear CH11 Interrupt Flag */ +#define _LESENSE_IFC_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11_DEFAULT (_LESENSE_IFC_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12 (0x1UL << 12) /**< Clear CH12 Interrupt Flag */ +#define _LESENSE_IFC_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12_DEFAULT (_LESENSE_IFC_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13 (0x1UL << 13) /**< Clear CH13 Interrupt Flag */ +#define _LESENSE_IFC_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13_DEFAULT (_LESENSE_IFC_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14 (0x1UL << 14) /**< Clear CH14 Interrupt Flag */ +#define _LESENSE_IFC_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14_DEFAULT (_LESENSE_IFC_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15 (0x1UL << 15) /**< Clear CH15 Interrupt Flag */ +#define _LESENSE_IFC_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15_DEFAULT (_LESENSE_IFC_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE (0x1UL << 16) /**< Clear SCANCOMPLETE Interrupt Flag */ +#define _LESENSE_IFC_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE_DEFAULT (_LESENSE_IFC_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC (0x1UL << 17) /**< Clear DEC Interrupt Flag */ +#define _LESENSE_IFC_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC_DEFAULT (_LESENSE_IFC_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR (0x1UL << 18) /**< Clear DECERR Interrupt Flag */ +#define _LESENSE_IFC_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR_DEFAULT (_LESENSE_IFC_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV (0x1UL << 19) /**< Clear BUFDATAV Interrupt Flag */ +#define _LESENSE_IFC_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV_DEFAULT (_LESENSE_IFC_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL (0x1UL << 20) /**< Clear BUFLEVEL Interrupt Flag */ +#define _LESENSE_IFC_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL_DEFAULT (_LESENSE_IFC_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF (0x1UL << 21) /**< Clear BUFOF Interrupt Flag */ +#define _LESENSE_IFC_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF_DEFAULT (_LESENSE_IFC_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF (0x1UL << 22) /**< Clear CNTOF Interrupt Flag */ +#define _LESENSE_IFC_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF_DEFAULT (_LESENSE_IFC_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFC */ + +/* Bit fields for LESENSE IEN */ +#define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */ +#define _LESENSE_IEN_MASK 0x007FFFFFUL /**< Mask for LESENSE_IEN */ +#define LESENSE_IEN_CH0 (0x1UL << 0) /**< CH0 Interrupt Enable */ +#define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1 (0x1UL << 1) /**< CH1 Interrupt Enable */ +#define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2 (0x1UL << 2) /**< CH2 Interrupt Enable */ +#define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3 (0x1UL << 3) /**< CH3 Interrupt Enable */ +#define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4 (0x1UL << 4) /**< CH4 Interrupt Enable */ +#define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5 (0x1UL << 5) /**< CH5 Interrupt Enable */ +#define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6 (0x1UL << 6) /**< CH6 Interrupt Enable */ +#define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7 (0x1UL << 7) /**< CH7 Interrupt Enable */ +#define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8 (0x1UL << 8) /**< CH8 Interrupt Enable */ +#define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9 (0x1UL << 9) /**< CH9 Interrupt Enable */ +#define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10 (0x1UL << 10) /**< CH10 Interrupt Enable */ +#define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11 (0x1UL << 11) /**< CH11 Interrupt Enable */ +#define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12 (0x1UL << 12) /**< CH12 Interrupt Enable */ +#define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13 (0x1UL << 13) /**< CH13 Interrupt Enable */ +#define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14 (0x1UL << 14) /**< CH14 Interrupt Enable */ +#define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15 (0x1UL << 15) /**< CH15 Interrupt Enable */ +#define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE Interrupt Enable */ +#define _LESENSE_IEN_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE_DEFAULT (_LESENSE_IEN_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC (0x1UL << 17) /**< DEC Interrupt Enable */ +#define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR (0x1UL << 18) /**< DECERR Interrupt Enable */ +#define _LESENSE_IEN_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR_DEFAULT (_LESENSE_IEN_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV (0x1UL << 19) /**< BUFDATAV Interrupt Enable */ +#define _LESENSE_IEN_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV_DEFAULT (_LESENSE_IEN_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL Interrupt Enable */ +#define _LESENSE_IEN_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL_DEFAULT (_LESENSE_IEN_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF (0x1UL << 21) /**< BUFOF Interrupt Enable */ +#define _LESENSE_IEN_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF_DEFAULT (_LESENSE_IEN_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF (0x1UL << 22) /**< CNTOF Interrupt Enable */ +#define _LESENSE_IEN_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IEN */ + +/* Bit fields for LESENSE SYNCBUSY */ +#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */ +#define _LESENSE_SYNCBUSY_MASK 0x00000080UL /**< Mask for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD (0x1UL << 7) /**< CMD Register Busy */ +#define _LESENSE_SYNCBUSY_CMD_SHIFT 7 /**< Shift value for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_MASK 0x80UL /**< Bit mask for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */ + +/* Bit fields for LESENSE ROUTEPEN */ +#define _LESENSE_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ROUTEPEN */ +#define _LESENSE_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for LESENSE_CH0PEN */ +#define _LESENSE_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for LESENSE_CH0PEN */ +#define _LESENSE_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH0PEN_DEFAULT (_LESENSE_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for LESENSE_CH1PEN */ +#define _LESENSE_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for LESENSE_CH1PEN */ +#define _LESENSE_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH1PEN_DEFAULT (_LESENSE_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for LESENSE_CH2PEN */ +#define _LESENSE_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for LESENSE_CH2PEN */ +#define _LESENSE_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH2PEN_DEFAULT (_LESENSE_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for LESENSE_CH3PEN */ +#define _LESENSE_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for LESENSE_CH3PEN */ +#define _LESENSE_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH3PEN_DEFAULT (_LESENSE_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for LESENSE_CH4PEN */ +#define _LESENSE_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for LESENSE_CH4PEN */ +#define _LESENSE_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH4PEN_DEFAULT (_LESENSE_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for LESENSE_CH5PEN */ +#define _LESENSE_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for LESENSE_CH5PEN */ +#define _LESENSE_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH5PEN_DEFAULT (_LESENSE_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for LESENSE_CH6PEN */ +#define _LESENSE_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for LESENSE_CH6PEN */ +#define _LESENSE_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH6PEN_DEFAULT (_LESENSE_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for LESENSE_CH7PEN */ +#define _LESENSE_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for LESENSE_CH7PEN */ +#define _LESENSE_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH7PEN_DEFAULT (_LESENSE_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for LESENSE_CH8PEN */ +#define _LESENSE_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for LESENSE_CH8PEN */ +#define _LESENSE_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH8PEN_DEFAULT (_LESENSE_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for LESENSE_CH9PEN */ +#define _LESENSE_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for LESENSE_CH9PEN */ +#define _LESENSE_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH9PEN_DEFAULT (_LESENSE_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for LESENSE_CH10PEN */ +#define _LESENSE_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for LESENSE_CH10PEN */ +#define _LESENSE_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH10PEN_DEFAULT (_LESENSE_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for LESENSE_CH11PEN */ +#define _LESENSE_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for LESENSE_CH11PEN */ +#define _LESENSE_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH11PEN_DEFAULT (_LESENSE_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for LESENSE_CH12PEN */ +#define _LESENSE_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for LESENSE_CH12PEN */ +#define _LESENSE_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH12PEN_DEFAULT (_LESENSE_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for LESENSE_CH13PEN */ +#define _LESENSE_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for LESENSE_CH13PEN */ +#define _LESENSE_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH13PEN_DEFAULT (_LESENSE_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for LESENSE_CH14PEN */ +#define _LESENSE_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for LESENSE_CH14PEN */ +#define _LESENSE_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH14PEN_DEFAULT (_LESENSE_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for LESENSE_CH15PEN */ +#define _LESENSE_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for LESENSE_CH15PEN */ +#define _LESENSE_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH15PEN_DEFAULT (_LESENSE_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX0PEN (0x1UL << 16) /**< ALTEX0 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_SHIFT 16 /**< Shift value for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_MASK 0x10000UL /**< Bit mask for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX1PEN (0x1UL << 17) /**< ALTEX1 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_SHIFT 17 /**< Shift value for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_MASK 0x20000UL /**< Bit mask for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX2PEN (0x1UL << 18) /**< ALTEX2 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_SHIFT 18 /**< Shift value for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX3PEN (0x1UL << 19) /**< ALTEX3 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_SHIFT 19 /**< Shift value for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_MASK 0x80000UL /**< Bit mask for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX4PEN (0x1UL << 20) /**< ALTEX4 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_SHIFT 20 /**< Shift value for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_MASK 0x100000UL /**< Bit mask for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX5PEN (0x1UL << 21) /**< ALTEX5 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_SHIFT 21 /**< Shift value for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX6PEN (0x1UL << 22) /**< ALTEX6 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_SHIFT 22 /**< Shift value for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_MASK 0x400000UL /**< Bit mask for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX7PEN (0x1UL << 23) /**< ALTEX7 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_SHIFT 23 /**< Shift value for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_MASK 0x800000UL /**< Bit mask for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ + +/* Bit fields for LESENSE ST_TCONFA */ +#define _LESENSE_ST_TCONFA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK 0x0007DFFFUL /**< Mask for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_COMP_DEFAULT (_LESENSE_ST_TCONFA_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_MASK_DEFAULT (_LESENSE_ST_TCONFA_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN (0x1UL << 14) /**< Enable State Descriptor Chaining */ +#define _LESENSE_ST_TCONFA_CHAIN_SHIFT 14 /**< Shift value for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_MASK 0x4000UL /**< Bit mask for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN_DEFAULT (_LESENSE_ST_TCONFA_CHAIN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF (0x1UL << 15) /**< Set Interrupt Flag Enable */ +#define _LESENSE_ST_TCONFA_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF_DEFAULT (_LESENSE_ST_TCONFA_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */ + +/* Bit fields for LESENSE ST_TCONFB */ +#define _LESENSE_ST_TCONFB_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK 0x00079FFFUL /**< Mask for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_COMP_DEFAULT (_LESENSE_ST_TCONFB_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_MASK_DEFAULT (_LESENSE_ST_TCONFB_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF (0x1UL << 15) /**< Set Interrupt Flag */ +#define _LESENSE_ST_TCONFB_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF_DEFAULT (_LESENSE_ST_TCONFB_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */ + +/* Bit fields for LESENSE BUF_DATA */ +#define _LESENSE_BUF_DATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_DATA_SHIFT 0 /**< Shift value for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ +#define LESENSE_BUF_DATA_DATA_DEFAULT (_LESENSE_BUF_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_DATASRC_SHIFT 16 /**< Shift value for LESENSE_DATASRC */ +#define _LESENSE_BUF_DATA_DATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_DATASRC */ +#define _LESENSE_BUF_DATA_DATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ +#define LESENSE_BUF_DATA_DATASRC_DEFAULT (_LESENSE_BUF_DATA_DATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ + +/* Bit fields for LESENSE CH_TIMING */ +#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ + +/* Bit fields for LESENSE CH_INTERACT */ +#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_MASK 0x003FFFFFUL /**< Mask for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 12 /**< Shift value for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x3000UL /**< Bit mask for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 12) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 12) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 12) /**< Shifted mode ADC for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 12) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_SHIFT 14 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_MASK 0x1C000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 14) /**< Shifted mode NONE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 14) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 14) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 14) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 14) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 17 /**< Shift value for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x60000UL /**< Bit mask for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 17) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 17) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 17) /**< Shifted mode LOW for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 17) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 19) /**< Select Clock Used for Excitation Timing */ +#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 19 /**< Shift value for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x80000UL /**< Bit mask for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 20) /**< Select Clock Used for Timing of Sample Delay */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 20 /**< Shift value for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x100000UL /**< Bit mask for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 21) /**< Use Alternative Excite Pin */ +#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 21 /**< Shift value for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ + +/* Bit fields for LESENSE CH_EVAL */ +#define _LESENSE_CH_EVAL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MASK 0x007FFFFFUL /**< Mask for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMPTHRES_SHIFT 0 /**< Shift value for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMPTHRES_DEFAULT (_LESENSE_CH_EVAL_COMPTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP (0x1UL << 16) /**< Select Mode for Threshold Comparison */ +#define _LESENSE_CH_EVAL_COMP_SHIFT 16 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_MASK 0x10000UL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_DEFAULT (_LESENSE_CH_EVAL_COMP_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_LESS (_LESENSE_CH_EVAL_COMP_LESS << 16) /**< Shifted mode LESS for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_GE (_LESENSE_CH_EVAL_COMP_GE << 16) /**< Shifted mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE (0x1UL << 17) /**< Send Result to Decoder */ +#define _LESENSE_CH_EVAL_DECODE_SHIFT 17 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_MASK 0x20000UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE_DEFAULT (_LESENSE_CH_EVAL_DECODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_SHIFT 18 /**< Shift value for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_MASK 0xC0000UL /**< Bit mask for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DEFAULT (_LESENSE_CH_EVAL_STRSAMPLE_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DISABLE (_LESENSE_CH_EVAL_STRSAMPLE_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DATA (_LESENSE_CH_EVAL_STRSAMPLE_DATA << 18) /**< Shifted mode DATA for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DATASRC (_LESENSE_CH_EVAL_STRSAMPLE_DATASRC << 18) /**< Shifted mode DATASRC for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV (0x1UL << 20) /**< Enable Inversion of Result */ +#define _LESENSE_CH_EVAL_SCANRESINV_SHIFT 20 /**< Shift value for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_MASK 0x100000UL /**< Bit mask for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV_DEFAULT (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_SHIFT 21 /**< Shift value for LESENSE_MODE */ +#define _LESENSE_CH_EVAL_MODE_MASK 0x600000UL /**< Bit mask for LESENSE_MODE */ +#define _LESENSE_CH_EVAL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_DEFAULT (_LESENSE_CH_EVAL_MODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_THRES (_LESENSE_CH_EVAL_MODE_THRES << 21) /**< Shifted mode THRES for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_SLIDINGWIN (_LESENSE_CH_EVAL_MODE_SLIDINGWIN << 21) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_STEPDET (_LESENSE_CH_EVAL_MODE_STEPDET << 21) /**< Shifted mode STEPDET for LESENSE_CH_EVAL */ + +/** @} */ +/** @} End of group EFM32GG11B_LESENSE */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_buf.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_buf.h new file mode 100644 index 0000000000000..b774f9581dc50 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_buf.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_LESENSE_BUF register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief LESENSE_BUF LESENSE BUF Register + * @ingroup EFM32GG11B_LESENSE + ******************************************************************************/ +typedef struct { + __IOM uint32_t DATA; /**< Scan Results */ +} LESENSE_BUF_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_ch.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_ch.h new file mode 100644 index 0000000000000..a5b667899d9b5 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_ch.h @@ -0,0 +1,61 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_LESENSE_CH register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief LESENSE_CH LESENSE CH Register + * @ingroup EFM32GG11B_LESENSE + ******************************************************************************/ +typedef struct { + __IOM uint32_t TIMING; /**< Scan Configuration */ + __IOM uint32_t INTERACT; /**< Scan Configuration */ + __IOM uint32_t EVAL; /**< Scan Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved future */ +} LESENSE_CH_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_st.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_st.h new file mode 100644 index 0000000000000..f5cb65dd34944 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_st.h @@ -0,0 +1,59 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_LESENSE_ST register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief LESENSE_ST LESENSE ST Register + * @ingroup EFM32GG11B_LESENSE + ******************************************************************************/ +typedef struct { + __IOM uint32_t TCONFA; /**< State Transition Configuration a */ + __IOM uint32_t TCONFB; /**< State Transition Configuration B */ +} LESENSE_ST_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_letimer.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_letimer.h new file mode 100644 index 0000000000000..26e65c055bbb2 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_letimer.h @@ -0,0 +1,612 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_LETIMER register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_LETIMER LETIMER + * @{ + * @brief EFM32GG11B_LETIMER Register Declaration + ******************************************************************************/ +/** LETIMER Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + + uint32_t RESERVED2[2U]; /**< Reserved for future use **/ + __IOM uint32_t PRSSEL; /**< PRS Input Select Register */ +} LETIMER_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_LETIMER + * @{ + * @defgroup EFM32GG11B_LETIMER_BitFields LETIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000013FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 is Top Value */ +#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IFS */ +#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */ +#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */ +#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set COMP0 Interrupt Flag */ +#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set COMP1 Interrupt Flag */ +#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF (0x1UL << 2) /**< Set UF Interrupt Flag */ +#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set REP0 Interrupt Flag */ +#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set REP1 Interrupt Flag */ +#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */ + +/* Bit fields for LETIMER IFC */ +#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */ +#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */ +#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear COMP0 Interrupt Flag */ +#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear COMP1 Interrupt Flag */ +#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear UF Interrupt Flag */ +#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear REP0 Interrupt Flag */ +#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear REP1 Interrupt Flag */ +#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< COMP0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< COMP1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< UF Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< REP0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< REP1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x00000002UL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER ROUTEPEN */ +#define _LETIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTEPEN */ +#define _LETIMER_ROUTEPEN_MASK 0x00000003UL /**< Mask for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */ +#define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTEPEN_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */ +#define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTEPEN_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ + +/* Bit fields for LETIMER ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_MASK 0x00000707UL /**< Mask for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT 0 /**< Shift value for LETIMER_OUT0LOC */ +#define _LETIMER_ROUTELOC0_OUT0LOC_MASK 0x7UL /**< Bit mask for LETIMER_OUT0LOC */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC0 (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC1 (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC2 (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC3 (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC4 (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC5 (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC6 (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC7 (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT 8 /**< Shift value for LETIMER_OUT1LOC */ +#define _LETIMER_ROUTELOC0_OUT1LOC_MASK 0x700UL /**< Bit mask for LETIMER_OUT1LOC */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC0 (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC1 (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC2 (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC3 (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC4 (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC5 (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC6 (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC7 (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ + +/* Bit fields for LETIMER PRSSEL */ +#define _LETIMER_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_MASK 0x0CCDF7DFUL /**< Mask for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT 0 /**< Shift value for LETIMER_PRSSTARTSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_MASK 0x1FUL /**< Bit mask for LETIMER_PRSSTARTSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH12 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH13 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH14 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH15 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH16 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH17 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH18 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH19 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH20 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH21 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH22 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH23 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT 6 /**< Shift value for LETIMER_PRSSTOPSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_MASK 0x7C0UL /**< Bit mask for LETIMER_PRSSTOPSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH12 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH13 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH14 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH15 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH16 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH17 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH18 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH19 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH20 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH21 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH22 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH23 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT 12 /**< Shift value for LETIMER_PRSCLEARSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_MASK 0x1F000UL /**< Bit mask for LETIMER_PRSCLEARSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH12 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH12 << 12) /**< Shifted mode PRSCH12 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH13 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH13 << 12) /**< Shifted mode PRSCH13 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH14 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH14 << 12) /**< Shifted mode PRSCH14 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH15 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH15 << 12) /**< Shifted mode PRSCH15 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH16 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH16 << 12) /**< Shifted mode PRSCH16 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH17 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH17 << 12) /**< Shifted mode PRSCH17 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH18 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH18 << 12) /**< Shifted mode PRSCH18 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH19 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH19 << 12) /**< Shifted mode PRSCH19 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH20 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH20 << 12) /**< Shifted mode PRSCH20 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH21 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH21 << 12) /**< Shifted mode PRSCH21 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH22 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH22 << 12) /**< Shifted mode PRSCH22 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH23 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH23 << 12) /**< Shifted mode PRSCH23 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_NONE (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_RISING (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_FALLING (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_BOTH (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_NONE (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_RISING (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_FALLING (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_BOTH (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_NONE (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_RISING (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */ + +/** @} */ +/** @} End of group EFM32GG11B_LETIMER */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_leuart.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_leuart.h new file mode 100644 index 0000000000000..08b12079673ff --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_leuart.h @@ -0,0 +1,771 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_LEUART register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_LEUART LEUART + * @{ + * @brief EFM32GG11B_LEUART Register Declaration + ******************************************************************************/ +/** LEUART Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IOM uint32_t STARTFRAME; /**< Start Frame Register */ + __IOM uint32_t SIGFRAME; /**< Signal Frame Register */ + __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */ + __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PULSECTRL; /**< Pulse Control Register */ + + __IOM uint32_t FREEZE; /**< Freeze Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t INPUT; /**< LEUART Input Register */ +} LEUART_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_LEUART + * @{ + * @defgroup EFM32GG11B_LEUART_BitFields LEUART Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for LEUART CTRL */ +#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */ +#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */ +#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */ +#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */ +#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */ +#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */ +#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */ +#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */ +#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */ +#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */ +#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */ +#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */ +#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */ +#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */ +#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input and Output */ +#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */ +#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */ +#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA on Error */ +#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */ +#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */ +#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */ +#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */ +#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */ +#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */ +#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */ +#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */ +#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */ +#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */ +#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */ +#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */ +#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */ +#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */ +#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */ +#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */ +#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */ +#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */ +#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */ +#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */ +#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */ +#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */ +#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */ +#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */ +#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */ +#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */ + +/* Bit fields for LEUART CMD */ +#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */ +#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */ +#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */ +#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */ +#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */ +#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */ +#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */ +#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */ +#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */ +#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */ +#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */ +#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */ +#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */ +#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */ +#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */ +#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */ +#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */ +#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */ +#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */ +#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */ + +/* Bit fields for LEUART STATUS */ +#define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */ +#define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */ +#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */ +#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */ +#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */ +#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */ +#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */ +#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */ +#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */ +#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */ +#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */ +#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */ +#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */ +#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */ +#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */ +#define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */ +#define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */ +#define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */ + +/* Bit fields for LEUART CLKDIV */ +#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */ +#define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */ +#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */ +#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */ + +/* Bit fields for LEUART STARTFRAME */ +#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */ +#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */ + +/* Bit fields for LEUART SIGFRAME */ +#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */ +#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */ + +/* Bit fields for LEUART RXDATAX */ +#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */ +#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */ +#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */ +#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */ +#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */ +#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ + +/* Bit fields for LEUART RXDATA */ +#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */ +#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */ +#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */ + +/* Bit fields for LEUART RXDATAXP */ +#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */ +#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */ +#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */ +#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */ +#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */ +#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */ +#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */ +#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */ +#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ + +/* Bit fields for LEUART TXDATAX */ +#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */ +#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */ +#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */ +#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */ +#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */ +#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */ +#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */ +#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */ +#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ + +/* Bit fields for LEUART TXDATA */ +#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */ +#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */ +#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */ + +/* Bit fields for LEUART IF */ +#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */ +#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */ +#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */ +#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */ +#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */ +#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */ +#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */ +#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */ +#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */ +#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */ + +/* Bit fields for LEUART IFS */ +#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */ +#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */ +#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ +#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */ +#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */ +#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */ +#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */ +#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */ +#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */ +#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */ +#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */ +#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */ + +/* Bit fields for LEUART IFC */ +#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */ +#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */ +#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ +#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */ +#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */ +#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */ +#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */ +#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */ +#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */ +#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */ +#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */ +#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */ + +/* Bit fields for LEUART IEN */ +#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */ +#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */ +#define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ +#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ +#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ +#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */ +#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */ +#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */ +#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */ +#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */ +#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */ +#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */ +#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */ +#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */ + +/* Bit fields for LEUART PULSECTRL */ +#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */ +#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */ +#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */ +#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */ +#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */ +#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */ +#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */ +#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */ +#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ + +/* Bit fields for LEUART FREEZE */ +#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */ +#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */ +#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */ +#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */ + +/* Bit fields for LEUART SYNCBUSY */ +#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */ +#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */ +#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */ +#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */ +#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */ +#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */ +#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */ +#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */ +#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */ +#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */ +#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */ +#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */ +#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */ +#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */ +#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */ +#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */ +#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */ +#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */ +#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ + +/* Bit fields for LEUART ROUTEPEN */ +#define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */ +#define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ +#define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */ +#define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */ +#define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ +#define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */ +#define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */ +#define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ + +/* Bit fields for LEUART ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_MASK 0x00000707UL /**< Mask for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */ +#define _LEUART_ROUTELOC0_RXLOC_MASK 0x7UL /**< Bit mask for LEUART_RXLOC */ +#define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */ +#define _LEUART_ROUTELOC0_TXLOC_MASK 0x700UL /**< Bit mask for LEUART_TXLOC */ +#define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ + +/* Bit fields for LEUART INPUT */ +#define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */ +#define _LEUART_INPUT_MASK 0x0000003FUL /**< Mask for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */ +#define _LEUART_INPUT_RXPRSSEL_MASK 0x1FUL /**< Bit mask for LEUART_RXPRSSEL */ +#define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH12 (_LEUART_INPUT_RXPRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH13 (_LEUART_INPUT_RXPRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH14 (_LEUART_INPUT_RXPRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH15 (_LEUART_INPUT_RXPRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH16 (_LEUART_INPUT_RXPRSSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH17 (_LEUART_INPUT_RXPRSSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH18 (_LEUART_INPUT_RXPRSSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH19 (_LEUART_INPUT_RXPRSSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH20 (_LEUART_INPUT_RXPRSSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH21 (_LEUART_INPUT_RXPRSSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH22 (_LEUART_INPUT_RXPRSSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH23 (_LEUART_INPUT_RXPRSSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */ +#define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */ +#define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */ +#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ +#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */ + +/** @} */ +/** @} End of group EFM32GG11B_LEUART */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_msc.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_msc.h new file mode 100644 index 0000000000000..96910f352eeed --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_msc.h @@ -0,0 +1,847 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_MSC register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_MSC MSC + * @{ + * @brief EFM32GG11B_MSC Register Declaration + ******************************************************************************/ +/** MSC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1U]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4U]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6U]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25U]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ + __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ + __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ + __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ +} MSC_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_MSC + * @{ + * @defgroup EFM32GG11B_MSC_BitFields MSC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ +#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ +#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ +#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ +#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ +#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ +#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ +#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ +#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000778UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ +#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ +#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_QSPICDIS (0x1UL << 10) /**< QSPI Cache Disable */ +#define _MSC_READCTRL_QSPICDIS_SHIFT 10 /**< Shift value for MSC_QSPICDIS */ +#define _MSC_READCTRL_QSPICDIS_MASK 0x400UL /**< Bit mask for MSC_QSPICDIS */ +#define _MSC_READCTRL_QSPICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_QSPICDIS_DEFAULT (_MSC_READCTRL_QSPICDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ +#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ +#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ +#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ +#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ +#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ +#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ +#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ +#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ +#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ +#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ +#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ +#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ +#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ +#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ +#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ +#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ +#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ +#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ +#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ +#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ +#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/* Bit fields for MSC ECCCTRL */ +#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ +#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ +#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ +#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ +#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ +#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ +#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ +#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ +#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ + +/* Bit fields for MSC RAMECCADDR */ +#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ +#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ +#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ + +/* Bit fields for MSC RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ +#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ +#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ + +/** @} */ +/** @} End of group EFM32GG11B_MSC */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_pcnt.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_pcnt.h new file mode 100644 index 0000000000000..533e860b8f92a --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_pcnt.h @@ -0,0 +1,698 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_PCNT register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_PCNT PCNT + * @{ + * @brief EFM32GG11B_PCNT Register Declaration + ******************************************************************************/ +/** PCNT Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t TOP; /**< Top Value Register */ + __IOM uint32_t TOPB; /**< Top Value Buffer Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + + uint32_t RESERVED1[4U]; /**< Reserved for future use **/ + __IOM uint32_t FREEZE; /**< Freeze Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED2[7U]; /**< Reserved for future use **/ + __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ + __IOM uint32_t INPUT; /**< PCNT Input Register */ + __IOM uint32_t OVSCFG; /**< Oversampling Config Register */ +} PCNT_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_PCNT + * @{ + * @defgroup EFM32GG11B_PCNT_BitFields PCNT Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PCNT CTRL */ +#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ +#define _PCNT_CTRL_MASK 0xFFDBFFFFUL /**< Mask for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ +#define _PCNT_CTRL_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ +#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD1X 0x00000004UL /**< Mode OVSQUAD1X for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD2X 0x00000005UL /**< Mode OVSQUAD2X for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD4X 0x00000006UL /**< Mode OVSQUAD4X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD1X (_PCNT_CTRL_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD2X (_PCNT_CTRL_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD4X (_PCNT_CTRL_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CTRL */ +#define PCNT_CTRL_FILT (0x1UL << 3) /**< Enable Digital Pulse Width Filter */ +#define _PCNT_CTRL_FILT_SHIFT 3 /**< Shift value for PCNT_FILT */ +#define _PCNT_CTRL_FILT_MASK 0x8UL /**< Bit mask for PCNT_FILT */ +#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN (0x1UL << 4) /**< Enable PCNT Clock Domain Reset */ +#define _PCNT_CTRL_RSTEN_SHIFT 4 /**< Shift value for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_MASK 0x10UL /**< Bit mask for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTRSTEN (0x1UL << 5) /**< Enable CNT Reset */ +#define _PCNT_CTRL_CNTRSTEN_SHIFT 5 /**< Shift value for PCNT_CNTRSTEN */ +#define _PCNT_CTRL_CNTRSTEN_MASK 0x20UL /**< Bit mask for PCNT_CNTRSTEN */ +#define _PCNT_CTRL_CNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTRSTEN_DEFAULT (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTRSTEN (0x1UL << 6) /**< Enable AUXCNT Reset */ +#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT 6 /**< Shift value for PCNT_AUXCNTRSTEN */ +#define _PCNT_CTRL_AUXCNTRSTEN_MASK 0x40UL /**< Bit mask for PCNT_AUXCNTRSTEN */ +#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_DEBUGHALT (0x1UL << 7) /**< Debug Mode Halt Enable */ +#define _PCNT_CTRL_DEBUGHALT_SHIFT 7 /**< Shift value for PCNT_DEBUGHALT */ +#define _PCNT_CTRL_DEBUGHALT_MASK 0x80UL /**< Bit mask for PCNT_DEBUGHALT */ +#define _PCNT_CTRL_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_DEBUGHALT_DEFAULT (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */ +#define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */ +#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */ +#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count Direction Determined By S1 */ +#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_SHIFT 12 /**< Shift value for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_MASK 0x3000UL /**< Bit mask for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 12) /**< Shifted mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 12) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 12) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 12) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR (0x1UL << 14) /**< Non-Quadrature Mode Counter Direction Control */ +#define _PCNT_CTRL_CNTDIR_SHIFT 14 /**< Shift value for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_MASK 0x4000UL /**< Bit mask for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 14) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_EDGE (0x1UL << 15) /**< Edge Select */ +#define _PCNT_CTRL_EDGE_SHIFT 15 /**< Shift value for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_MASK 0x8000UL /**< Bit mask for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 15) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 15) /**< Shifted mode POS for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 15) /**< Shifted mode NEG for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_SHIFT 16 /**< Shift value for PCNT_TCCMODE */ +#define _PCNT_CTRL_TCCMODE_MASK 0x30000UL /**< Bit mask for PCNT_TCCMODE */ +#define _PCNT_CTRL_TCCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_DISABLED 0x00000000UL /**< Mode DISABLED for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_LFA 0x00000001UL /**< Mode LFA for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_PRS 0x00000002UL /**< Mode PRS for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_DEFAULT (_PCNT_CTRL_TCCMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_DISABLED (_PCNT_CTRL_TCCMODE_DISABLED << 16) /**< Shifted mode DISABLED for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_LFA (_PCNT_CTRL_TCCMODE_LFA << 16) /**< Shifted mode LFA for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_PRS (_PCNT_CTRL_TCCMODE_PRS << 16) /**< Shifted mode PRS for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_SHIFT 19 /**< Shift value for PCNT_TCCPRESC */ +#define _PCNT_CTRL_TCCPRESC_MASK 0x180000UL /**< Bit mask for PCNT_TCCPRESC */ +#define _PCNT_CTRL_TCCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DEFAULT (_PCNT_CTRL_TCCPRESC_DEFAULT << 19) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV1 (_PCNT_CTRL_TCCPRESC_DIV1 << 19) /**< Shifted mode DIV1 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV2 (_PCNT_CTRL_TCCPRESC_DIV2 << 19) /**< Shifted mode DIV2 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV4 (_PCNT_CTRL_TCCPRESC_DIV4 << 19) /**< Shifted mode DIV4 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV8 (_PCNT_CTRL_TCCPRESC_DIV8 << 19) /**< Shifted mode DIV8 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_SHIFT 22 /**< Shift value for PCNT_TCCCOMP */ +#define _PCNT_CTRL_TCCCOMP_MASK 0xC00000UL /**< Bit mask for PCNT_TCCCOMP */ +#define _PCNT_CTRL_TCCCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_LTOE 0x00000000UL /**< Mode LTOE for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_GTOE 0x00000001UL /**< Mode GTOE for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_RANGE 0x00000002UL /**< Mode RANGE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_DEFAULT (_PCNT_CTRL_TCCCOMP_DEFAULT << 22) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */ +#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS Gate Enable */ +#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */ +#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */ +#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS Polarity Select */ +#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */ +#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */ +#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSPOL_RISING 0x00000000UL /**< Mode RISING for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSPOL_FALLING 0x00000001UL /**< Mode FALLING for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_DEFAULT (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_RISING (_PCNT_CTRL_TCCPRSPOL_RISING << 25) /**< Shifted mode RISING for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_FALLING (_PCNT_CTRL_TCCPRSPOL_FALLING << 25) /**< Shifted mode FALLING for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_SHIFT 26 /**< Shift value for PCNT_TCCPRSSEL */ +#define _PCNT_CTRL_TCCPRSSEL_MASK 0x7C000000UL /**< Bit mask for PCNT_TCCPRSSEL */ +#define _PCNT_CTRL_TCCPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_DEFAULT (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH0 (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26) /**< Shifted mode PRSCH0 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH1 (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26) /**< Shifted mode PRSCH1 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH2 (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26) /**< Shifted mode PRSCH2 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH3 (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26) /**< Shifted mode PRSCH3 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH4 (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26) /**< Shifted mode PRSCH4 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH5 (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26) /**< Shifted mode PRSCH5 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH6 (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26) /**< Shifted mode PRSCH6 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH7 (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26) /**< Shifted mode PRSCH7 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH8 (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26) /**< Shifted mode PRSCH8 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH12 (_PCNT_CTRL_TCCPRSSEL_PRSCH12 << 26) /**< Shifted mode PRSCH12 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH13 (_PCNT_CTRL_TCCPRSSEL_PRSCH13 << 26) /**< Shifted mode PRSCH13 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH14 (_PCNT_CTRL_TCCPRSSEL_PRSCH14 << 26) /**< Shifted mode PRSCH14 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH15 (_PCNT_CTRL_TCCPRSSEL_PRSCH15 << 26) /**< Shifted mode PRSCH15 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH16 (_PCNT_CTRL_TCCPRSSEL_PRSCH16 << 26) /**< Shifted mode PRSCH16 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH17 (_PCNT_CTRL_TCCPRSSEL_PRSCH17 << 26) /**< Shifted mode PRSCH17 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH18 (_PCNT_CTRL_TCCPRSSEL_PRSCH18 << 26) /**< Shifted mode PRSCH18 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH19 (_PCNT_CTRL_TCCPRSSEL_PRSCH19 << 26) /**< Shifted mode PRSCH19 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH20 (_PCNT_CTRL_TCCPRSSEL_PRSCH20 << 26) /**< Shifted mode PRSCH20 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH21 (_PCNT_CTRL_TCCPRSSEL_PRSCH21 << 26) /**< Shifted mode PRSCH21 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH22 (_PCNT_CTRL_TCCPRSSEL_PRSCH22 << 26) /**< Shifted mode PRSCH22 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH23 (_PCNT_CTRL_TCCPRSSEL_PRSCH23 << 26) /**< Shifted mode PRSCH23 for PCNT_CTRL */ +#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High Frequency Value Select */ +#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */ +#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */ +#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TOPBHFSEL_DEFAULT (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31) /**< Shifted mode DEFAULT for PCNT_CTRL */ + +/* Bit fields for PCNT CMD */ +#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ +#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */ +#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */ +#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */ +#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ + +/* Bit fields for PCNT STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ + +/* Bit fields for PCNT CNT */ +#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ +#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ +#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ +#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ + +/* Bit fields for PCNT TOP */ +#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ +#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ +#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ +#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ + +/* Bit fields for PCNT TOPB */ +#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ +#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ +#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ + +/* Bit fields for PCNT IF */ +#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ +#define _PCNT_IF_MASK 0x0000003FUL /**< Mask for PCNT_IF */ +#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered Compare Interrupt Read Flag */ +#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_TCC_DEFAULT (_PCNT_IF_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR (0x1UL << 5) /**< Oversampling Quadrature State Error Interrupt */ +#define _PCNT_IF_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */ + +/* Bit fields for PCNT IFS */ +#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */ +#define _PCNT_IFS_MASK 0x0000003FUL /**< Mask for PCNT_IFS */ +#define PCNT_IFS_UF (0x1UL << 0) /**< Set UF Interrupt Flag */ +#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF (0x1UL << 1) /**< Set OF Interrupt Flag */ +#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Set DIRCNG Interrupt Flag */ +#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF (0x1UL << 3) /**< Set AUXOF Interrupt Flag */ +#define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_TCC (0x1UL << 4) /**< Set TCC Interrupt Flag */ +#define _PCNT_IFS_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IFS_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IFS_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_TCC_DEFAULT (_PCNT_IFS_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OQSTERR (0x1UL << 5) /**< Set OQSTERR Interrupt Flag */ +#define _PCNT_IFS_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IFS_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IFS_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OQSTERR_DEFAULT (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */ + +/* Bit fields for PCNT IFC */ +#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */ +#define _PCNT_IFC_MASK 0x0000003FUL /**< Mask for PCNT_IFC */ +#define PCNT_IFC_UF (0x1UL << 0) /**< Clear UF Interrupt Flag */ +#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF (0x1UL << 1) /**< Clear OF Interrupt Flag */ +#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Clear DIRCNG Interrupt Flag */ +#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF (0x1UL << 3) /**< Clear AUXOF Interrupt Flag */ +#define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_TCC (0x1UL << 4) /**< Clear TCC Interrupt Flag */ +#define _PCNT_IFC_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IFC_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IFC_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_TCC_DEFAULT (_PCNT_IFC_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OQSTERR (0x1UL << 5) /**< Clear OQSTERR Interrupt Flag */ +#define _PCNT_IFC_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IFC_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IFC_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OQSTERR_DEFAULT (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */ + +/* Bit fields for PCNT IEN */ +#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ +#define _PCNT_IEN_MASK 0x0000003FUL /**< Mask for PCNT_IEN */ +#define PCNT_IEN_UF (0x1UL << 0) /**< UF Interrupt Enable */ +#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF (0x1UL << 1) /**< OF Interrupt Enable */ +#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< DIRCNG Interrupt Enable */ +#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF (0x1UL << 3) /**< AUXOF Interrupt Enable */ +#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_TCC (0x1UL << 4) /**< TCC Interrupt Enable */ +#define _PCNT_IEN_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IEN_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IEN_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_TCC_DEFAULT (_PCNT_IEN_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR (0x1UL << 5) /**< OQSTERR Interrupt Enable */ +#define _PCNT_IEN_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */ + +/* Bit fields for PCNT ROUTELOC0 */ +#define _PCNT_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_MASK 0x00000707UL /**< Mask for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_SHIFT 0 /**< Shift value for PCNT_S0INLOC */ +#define _PCNT_ROUTELOC0_S0INLOC_MASK 0x7UL /**< Bit mask for PCNT_S0INLOC */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC0 (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_DEFAULT (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC1 (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC2 (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC3 (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC4 (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC5 (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC6 (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC7 (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_SHIFT 8 /**< Shift value for PCNT_S1INLOC */ +#define _PCNT_ROUTELOC0_S1INLOC_MASK 0x700UL /**< Bit mask for PCNT_S1INLOC */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC0 (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_DEFAULT (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC1 (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC2 (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC3 (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC4 (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC5 (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC6 (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC7 (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ + +/* Bit fields for PCNT FREEZE */ +#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */ +#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */ + +/* Bit fields for PCNT SYNCBUSY */ +#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_MASK 0x0000000FUL /**< Mask for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */ +#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCFG (0x1UL << 3) /**< OVSCFG Register Busy */ +#define _PCNT_SYNCBUSY_OVSCFG_SHIFT 3 /**< Shift value for PCNT_OVSCFG */ +#define _PCNT_SYNCBUSY_OVSCFG_MASK 0x8UL /**< Bit mask for PCNT_OVSCFG */ +#define _PCNT_SYNCBUSY_OVSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCFG_DEFAULT (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ + +/* Bit fields for PCNT AUXCNT */ +#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ +#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ + +/* Bit fields for PCNT INPUT */ +#define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */ +#define _PCNT_INPUT_MASK 0x00000FFFUL /**< Mask for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_MASK 0x1FUL /**< Bit mask for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH12 (_PCNT_INPUT_S0PRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH13 (_PCNT_INPUT_S0PRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH14 (_PCNT_INPUT_S0PRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH15 (_PCNT_INPUT_S0PRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH16 (_PCNT_INPUT_S0PRSSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH17 (_PCNT_INPUT_S0PRSSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH18 (_PCNT_INPUT_S0PRSSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH19 (_PCNT_INPUT_S0PRSSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH20 (_PCNT_INPUT_S0PRSSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH21 (_PCNT_INPUT_S0PRSSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH22 (_PCNT_INPUT_S0PRSSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH23 (_PCNT_INPUT_S0PRSSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN (0x1UL << 5) /**< S0IN PRS Enable */ +#define _PCNT_INPUT_S0PRSEN_SHIFT 5 /**< Shift value for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_MASK 0x20UL /**< Bit mask for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_MASK 0x7C0UL /**< Bit mask for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH12 (_PCNT_INPUT_S1PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH13 (_PCNT_INPUT_S1PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH14 (_PCNT_INPUT_S1PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH15 (_PCNT_INPUT_S1PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH16 (_PCNT_INPUT_S1PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH17 (_PCNT_INPUT_S1PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH18 (_PCNT_INPUT_S1PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH19 (_PCNT_INPUT_S1PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH20 (_PCNT_INPUT_S1PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH21 (_PCNT_INPUT_S1PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH22 (_PCNT_INPUT_S1PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH23 (_PCNT_INPUT_S1PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN (0x1UL << 11) /**< S1IN PRS Enable */ +#define _PCNT_INPUT_S1PRSEN_SHIFT 11 /**< Shift value for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_MASK 0x800UL /**< Bit mask for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */ + +/* Bit fields for PCNT OVSCFG */ +#define _PCNT_OVSCFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCFG */ +#define _PCNT_OVSCFG_MASK 0x000010FFUL /**< Mask for PCNT_OVSCFG */ +#define _PCNT_OVSCFG_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ +#define _PCNT_OVSCFG_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ +#define _PCNT_OVSCFG_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FILTLEN_DEFAULT (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ +#define _PCNT_OVSCFG_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ +#define _PCNT_OVSCFG_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ +#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ + +/** @} */ +/** @} End of group EFM32GG11B_PCNT */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs.h new file mode 100644 index 0000000000000..e730c056c4cfe --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs.h @@ -0,0 +1,1579 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_PRS register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_PRS PRS + * @{ + * @brief EFM32GG11B_PRS Register Declaration + ******************************************************************************/ +/** PRS Register Declaration */ +typedef struct { + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3U]; /**< Reserved registers */ + PRS_CH_TypeDef CH[24U]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_PRS + * @{ + * @defgroup EFM32GG11B_PRS_BitFields PRS Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ +#define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ +#define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ +#define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ +#define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ +#define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ +#define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ +#define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ +#define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ +#define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ +#define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ +#define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ +#define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ +#define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ +#define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ +#define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ +#define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ +#define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ +#define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ +#define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ +#define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ +#define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ +#define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ +#define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ +#define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ +#define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ +#define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ +#define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ +#define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ +#define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ +#define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ +#define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ +#define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ +#define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ +#define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ +#define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ +#define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ +#define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ +#define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ +#define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ +#define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ +#define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ +#define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ +#define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ +#define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ +#define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ +#define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ +#define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ +#define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ +#define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ +#define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ +#define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ +#define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ +#define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ +#define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ +#define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ +#define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ +#define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ +#define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ +#define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ +#define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS ROUTELOC3 */ +#define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ +#define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ +#define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ +#define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ +#define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ +#define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ +#define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ + +/* Bit fields for PRS ROUTELOC4 */ +#define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ +#define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ +#define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ +#define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ +#define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ +#define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ +#define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ + +/* Bit fields for PRS ROUTELOC5 */ +#define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ +#define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ +#define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ +#define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ +#define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ +#define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ +#define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ +#define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ +#define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ +#define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ +#define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ +#define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ +#define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ +#define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ +#define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ +#define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ +#define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ +#define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ +#define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ +#define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ +#define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ +#define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ +#define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ +#define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ +#define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ +#define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USB 0x00000040UL /**< Mode USB for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 8) /**< Shifted mode USB for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} */ +/** @} End of group EFM32GG11B_PRS */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs_ch.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs_ch.h new file mode 100644 index 0000000000000..d9d1f3cb2fd8d --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs_ch.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_PRS_CH register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief PRS_CH PRS CH Register + * @ingroup EFM32GG11B_PRS + ******************************************************************************/ +typedef struct { + __IOM uint32_t CTRL; /**< Channel Control Register */ +} PRS_CH_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs_signals.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs_signals.h new file mode 100644 index 0000000000000..889ec93e6f528 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs_signals.h @@ -0,0 +1,266 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_PRS_SIGNALS register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup EFM32GG11B_PRS + * @{ + * @addtogroup EFM32GG11B_PRS_Signals PRS Signals + * @{ + * @brief PRS Signal names + ******************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ +#define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ +#define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ +#define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ +#define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ +#define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ +#define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ +#define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ +#define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ +#define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ +#define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ +#define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ +#define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ +#define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ +#define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ +#define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ +#define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ +#define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ +#define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ +#define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ +#define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ +#define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ +#define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ +#define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ +#define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ +#define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ +#define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ +#define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ +#define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ +#define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ +#define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ +#define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ +#define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ +#define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ +#define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ +#define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ +#define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ +#define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ +#define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ +#define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ +#define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ +#define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ +#define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ +#define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ +#define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ +#define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ +#define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ +#define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ +#define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ +#define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ +#define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ +#define PRS_USB_SOF ((64 << 8) + 0) /**< PRS USB Start of Frame */ +#define PRS_USB_SOFSR ((64 << 8) + 1) /**< PRS USB Start of Frame Sent/Received */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ +#define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ +#define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ +#define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ +#define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ +#define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ +#define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ +#define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ +#define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ +#define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ +#define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ +#define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ +#define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ +#define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ +#define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ +#define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ +#define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ +#define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ +#define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ +#define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ +#define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ +#define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ +#define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ +#define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ +#define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ +#define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ +#define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ +#define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ +#define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ +#define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ +#define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ +#define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ +#define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ +#define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ +#define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ +#define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ +#define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ +#define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ +#define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ +#define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ + +/** @} */ +/** @} End of group EFM32GG11B_PRS */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_qspi.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_qspi.h new file mode 100644 index 0000000000000..127cc5cd9dea3 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_qspi.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_QSPI register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_QSPI QSPI + * @{ + * @brief EFM32GG11B_QSPI Register Declaration + ******************************************************************************/ +/** QSPI Register Declaration */ +typedef struct { + __IOM uint32_t CONFIG; /**< Octal-SPI Configuration Register */ + __IOM uint32_t DEVINSTRRDCONFIG; /**< Device Read Instruction Configuration Register */ + __IOM uint32_t DEVINSTRWRCONFIG; /**< Device Write Instruction Configuration Register */ + __IOM uint32_t DEVDELAY; /**< Device Delay Register */ + __IOM uint32_t RDDATACAPTURE; /**< Read Data Capture Register */ + __IOM uint32_t DEVSIZECONFIG; /**< Device Size Configuration Register */ + __IOM uint32_t SRAMPARTITIONCFG; /**< SRAM Partition Configuration Register */ + __IOM uint32_t INDAHBADDRTRIGGER; /**< Indirect Address Trigger Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t REMAPADDR; /**< Remap Address Register */ + __IOM uint32_t MODEBITCONFIG; /**< Mode Bit Configuration Register */ + __IM uint32_t SRAMFILL; /**< SRAM Fill Register */ + __IOM uint32_t TXTHRESH; /**< TX Threshold Register */ + __IOM uint32_t RXTHRESH; /**< RX Threshold Register */ + __IOM uint32_t WRITECOMPLETIONCTRL; /**< Write Completion Control Register */ + __IOM uint32_t NOOFPOLLSBEFEXP; /**< Polling Expiration Register */ + __IOM uint32_t IRQSTATUS; /**< Interrupt Status Register */ + __IOM uint32_t IRQMASK; /**< Interrupt Mask */ + uint32_t RESERVED1[2U]; /**< Reserved for future use **/ + __IOM uint32_t LOWERWRPROT; /**< Lower Write Protection Register */ + __IOM uint32_t UPPERWRPROT; /**< Upper Write Protection Register */ + __IOM uint32_t WRPROTCTRL; /**< Write Protection Control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use **/ + __IOM uint32_t INDIRECTREADXFERCTRL; /**< Indirect Read Transfer Control Register */ + __IOM uint32_t INDIRECTREADXFERWATERMARK; /**< Indirect Read Transfer Watermark Register */ + __IOM uint32_t INDIRECTREADXFERSTART; /**< Indirect Read Transfer Start Address Register */ + __IOM uint32_t INDIRECTREADXFERNUMBYTES; /**< Indirect Read Transfer Number Bytes Register */ + __IOM uint32_t INDIRECTWRITEXFERCTRL; /**< Indirect Write Transfer Control Register */ + __IOM uint32_t INDIRECTWRITEXFERWATERMARK; /**< Indirect Write Transfer Watermark Register */ + __IOM uint32_t INDIRECTWRITEXFERSTART; /**< Indirect Write Transfer Start Address Register */ + __IOM uint32_t INDIRECTWRITEXFERNUMBYTES; /**< Indirect Write Transfer Number Bytes Register */ + __IOM uint32_t INDIRECTTRIGGERADDRRANGE; /**< Indirect Trigger Address Range Register */ + uint32_t RESERVED3[2U]; /**< Reserved for future use **/ + __IOM uint32_t FLASHCOMMANDCTRLMEM; /**< Flash Command Control Memory Register (STIG) */ + __IOM uint32_t FLASHCMDCTRL; /**< Flash Command Control Register (STIG) */ + __IOM uint32_t FLASHCMDADDR; /**< Flash Command Address Register (STIG) */ + uint32_t RESERVED4[2U]; /**< Reserved for future use **/ + __IM uint32_t FLASHRDDATALOWER; /**< Flash Command Read Data Register (Lower) (STIG) */ + __IM uint32_t FLASHRDDATAUPPER; /**< Flash Command Read Data Register (Upper) (STIG) */ + __IOM uint32_t FLASHWRDATALOWER; /**< Flash Command Write Data Register (Lower) (STIG) */ + __IOM uint32_t FLASHWRDATAUPPER; /**< Flash Command Write Data Register (Upper) (STIG) */ + __IOM uint32_t POLLINGFLASHSTATUS; /**< Polling Flash Status Register */ + __IOM uint32_t PHYCONFIGURATION; /**< PHY Configuration Register */ + + uint32_t RESERVED5[10U]; /**< Reserved for future use **/ + __IOM uint32_t OPCODEEXTLOWER; /**< Opcode Extension Register (Lower) */ + __IOM uint32_t OPCODEEXTUPPER; /**< Opcode Extension Register (Upper) */ + uint32_t RESERVED6[5U]; /**< Reserved for future use **/ + __IM uint32_t MODULEID; /**< Module ID Register */ + + uint32_t RESERVED7[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Route Location Register 0 */ +} QSPI_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_QSPI + * @{ + * @defgroup EFM32GG11B_QSPI_BitFields QSPI Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for QSPI CONFIG */ +#define _QSPI_CONFIG_RESETVALUE 0x80780081UL /**< Default value for QSPI_CONFIG */ +#define _QSPI_CONFIG_MASK 0xE3FF4F8FUL /**< Mask for QSPI_CONFIG */ +#define QSPI_CONFIG_ENBSPI (0x1UL << 0) /**< QSPI Enable */ +#define _QSPI_CONFIG_ENBSPI_SHIFT 0 /**< Shift value for QSPI_ENBSPI */ +#define _QSPI_CONFIG_ENBSPI_MASK 0x1UL /**< Bit mask for QSPI_ENBSPI */ +#define _QSPI_CONFIG_ENBSPI_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENBSPI_DEFAULT (_QSPI_CONFIG_ENBSPI_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_SELCLKPOL (0x1UL << 1) /**< Clock Polarity, CPOL */ +#define _QSPI_CONFIG_SELCLKPOL_SHIFT 1 /**< Shift value for QSPI_SELCLKPOL */ +#define _QSPI_CONFIG_SELCLKPOL_MASK 0x2UL /**< Bit mask for QSPI_SELCLKPOL */ +#define _QSPI_CONFIG_SELCLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_SELCLKPOL_DEFAULT (_QSPI_CONFIG_SELCLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_SELCLKPHASE (0x1UL << 2) /**< Clock Phase, CPHA */ +#define _QSPI_CONFIG_SELCLKPHASE_SHIFT 2 /**< Shift value for QSPI_SELCLKPHASE */ +#define _QSPI_CONFIG_SELCLKPHASE_MASK 0x4UL /**< Bit mask for QSPI_SELCLKPHASE */ +#define _QSPI_CONFIG_SELCLKPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_SELCLKPHASE_DEFAULT (_QSPI_CONFIG_SELCLKPHASE_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_PHYMODEENABLE (0x1UL << 3) /**< PHY Mode Enable */ +#define _QSPI_CONFIG_PHYMODEENABLE_SHIFT 3 /**< Shift value for QSPI_PHYMODEENABLE */ +#define _QSPI_CONFIG_PHYMODEENABLE_MASK 0x8UL /**< Bit mask for QSPI_PHYMODEENABLE */ +#define _QSPI_CONFIG_PHYMODEENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_PHYMODEENABLE_DEFAULT (_QSPI_CONFIG_PHYMODEENABLE_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENBDIRACCCTLR (0x1UL << 7) /**< Enable Direct Access Controller */ +#define _QSPI_CONFIG_ENBDIRACCCTLR_SHIFT 7 /**< Shift value for QSPI_ENBDIRACCCTLR */ +#define _QSPI_CONFIG_ENBDIRACCCTLR_MASK 0x80UL /**< Bit mask for QSPI_ENBDIRACCCTLR */ +#define _QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT (_QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENBLEGACYIPMODE (0x1UL << 8) /**< Legacy IP Mode Enable */ +#define _QSPI_CONFIG_ENBLEGACYIPMODE_SHIFT 8 /**< Shift value for QSPI_ENBLEGACYIPMODE */ +#define _QSPI_CONFIG_ENBLEGACYIPMODE_MASK 0x100UL /**< Bit mask for QSPI_ENBLEGACYIPMODE */ +#define _QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT (_QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_PERIPHSELDEC (0x1UL << 9) /**< Peripheral Select Decode */ +#define _QSPI_CONFIG_PERIPHSELDEC_SHIFT 9 /**< Shift value for QSPI_PERIPHSELDEC */ +#define _QSPI_CONFIG_PERIPHSELDEC_MASK 0x200UL /**< Bit mask for QSPI_PERIPHSELDEC */ +#define _QSPI_CONFIG_PERIPHSELDEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_PERIPHSELDEC_DEFAULT (_QSPI_CONFIG_PERIPHSELDEC_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define _QSPI_CONFIG_PERIPHCSLINES_SHIFT 10 /**< Shift value for QSPI_PERIPHCSLINES */ +#define _QSPI_CONFIG_PERIPHCSLINES_MASK 0xC00UL /**< Bit mask for QSPI_PERIPHCSLINES */ +#define _QSPI_CONFIG_PERIPHCSLINES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_PERIPHCSLINES_DEFAULT (_QSPI_CONFIG_PERIPHCSLINES_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_WRPROTFLASH (0x1UL << 14) /**< Write Protect Flash Pin */ +#define _QSPI_CONFIG_WRPROTFLASH_SHIFT 14 /**< Shift value for QSPI_WRPROTFLASH */ +#define _QSPI_CONFIG_WRPROTFLASH_MASK 0x4000UL /**< Bit mask for QSPI_WRPROTFLASH */ +#define _QSPI_CONFIG_WRPROTFLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_WRPROTFLASH_DEFAULT (_QSPI_CONFIG_WRPROTFLASH_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENBAHBADDRREMAP (0x1UL << 16) /**< Enable Address Remapping */ +#define _QSPI_CONFIG_ENBAHBADDRREMAP_SHIFT 16 /**< Shift value for QSPI_ENBAHBADDRREMAP */ +#define _QSPI_CONFIG_ENBAHBADDRREMAP_MASK 0x10000UL /**< Bit mask for QSPI_ENBAHBADDRREMAP */ +#define _QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT (_QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENTERXIPMODE (0x1UL << 17) /**< Enter XIP Mode on Next READ */ +#define _QSPI_CONFIG_ENTERXIPMODE_SHIFT 17 /**< Shift value for QSPI_ENTERXIPMODE */ +#define _QSPI_CONFIG_ENTERXIPMODE_MASK 0x20000UL /**< Bit mask for QSPI_ENTERXIPMODE */ +#define _QSPI_CONFIG_ENTERXIPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENTERXIPMODE_DEFAULT (_QSPI_CONFIG_ENTERXIPMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENTERXIPMODEIMM (0x1UL << 18) /**< Enter XIP Mode Immediately */ +#define _QSPI_CONFIG_ENTERXIPMODEIMM_SHIFT 18 /**< Shift value for QSPI_ENTERXIPMODEIMM */ +#define _QSPI_CONFIG_ENTERXIPMODEIMM_MASK 0x40000UL /**< Bit mask for QSPI_ENTERXIPMODEIMM */ +#define _QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT (_QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define _QSPI_CONFIG_MSTRBAUDDIV_SHIFT 19 /**< Shift value for QSPI_MSTRBAUDDIV */ +#define _QSPI_CONFIG_MSTRBAUDDIV_MASK 0x780000UL /**< Bit mask for QSPI_MSTRBAUDDIV */ +#define _QSPI_CONFIG_MSTRBAUDDIV_DEFAULT 0x0000000FUL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_MSTRBAUDDIV_DEFAULT (_QSPI_CONFIG_MSTRBAUDDIV_DEFAULT << 19) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENABLEAHBDECODER (0x1UL << 23) /**< Enable Address Decoder */ +#define _QSPI_CONFIG_ENABLEAHBDECODER_SHIFT 23 /**< Shift value for QSPI_ENABLEAHBDECODER */ +#define _QSPI_CONFIG_ENABLEAHBDECODER_MASK 0x800000UL /**< Bit mask for QSPI_ENABLEAHBDECODER */ +#define _QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT (_QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT << 23) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENABLEDTRPROTOCOL (0x1UL << 24) /**< Enable DTR Protocol */ +#define _QSPI_CONFIG_ENABLEDTRPROTOCOL_SHIFT 24 /**< Shift value for QSPI_ENABLEDTRPROTOCOL */ +#define _QSPI_CONFIG_ENABLEDTRPROTOCOL_MASK 0x1000000UL /**< Bit mask for QSPI_ENABLEDTRPROTOCOL */ +#define _QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT (_QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_PIPELINEPHY (0x1UL << 25) /**< Pipeline PHY Mode Enable */ +#define _QSPI_CONFIG_PIPELINEPHY_SHIFT 25 /**< Shift value for QSPI_PIPELINEPHY */ +#define _QSPI_CONFIG_PIPELINEPHY_MASK 0x2000000UL /**< Bit mask for QSPI_PIPELINEPHY */ +#define _QSPI_CONFIG_PIPELINEPHY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_PIPELINEPHY_DEFAULT (_QSPI_CONFIG_PIPELINEPHY_DEFAULT << 25) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_CRCENABLE (0x1UL << 29) /**< CRC Enable Bit */ +#define _QSPI_CONFIG_CRCENABLE_SHIFT 29 /**< Shift value for QSPI_CRCENABLE */ +#define _QSPI_CONFIG_CRCENABLE_MASK 0x20000000UL /**< Bit mask for QSPI_CRCENABLE */ +#define _QSPI_CONFIG_CRCENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_CRCENABLE_DEFAULT (_QSPI_CONFIG_CRCENABLE_DEFAULT << 29) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_DUALBYTEOPCODEEN (0x1UL << 30) /**< Dual-byte Opcode Mode Enable Bit */ +#define _QSPI_CONFIG_DUALBYTEOPCODEEN_SHIFT 30 /**< Shift value for QSPI_DUALBYTEOPCODEEN */ +#define _QSPI_CONFIG_DUALBYTEOPCODEEN_MASK 0x40000000UL /**< Bit mask for QSPI_DUALBYTEOPCODEEN */ +#define _QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT (_QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT << 30) /**< Shifted mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_IDLE (0x1UL << 31) /**< Serial Interface and Low Level SPI Pipeline is IDLE */ +#define _QSPI_CONFIG_IDLE_SHIFT 31 /**< Shift value for QSPI_IDLE */ +#define _QSPI_CONFIG_IDLE_MASK 0x80000000UL /**< Bit mask for QSPI_IDLE */ +#define _QSPI_CONFIG_IDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_CONFIG */ +#define QSPI_CONFIG_IDLE_DEFAULT (_QSPI_CONFIG_IDLE_DEFAULT << 31) /**< Shifted mode DEFAULT for QSPI_CONFIG */ + +/* Bit fields for QSPI DEVINSTRRDCONFIG */ +#define _QSPI_DEVINSTRRDCONFIG_RESETVALUE 0x00000003UL /**< Default value for QSPI_DEVINSTRRDCONFIG */ +#define _QSPI_DEVINSTRRDCONFIG_MASK 0x1F1337FFUL /**< Mask for QSPI_DEVINSTRRDCONFIG */ +#define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_SHIFT 0 /**< Shift value for QSPI_RDOPCODENONXIP */ +#define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_MASK 0xFFUL /**< Bit mask for QSPI_RDOPCODENONXIP */ +#define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT 0x00000003UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT (_QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_SHIFT 8 /**< Shift value for QSPI_INSTRTYPE */ +#define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_MASK 0x300UL /**< Bit mask for QSPI_INSTRTYPE */ +#define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define QSPI_DEVINSTRRDCONFIG_DDREN (0x1UL << 10) /**< DDR Enable */ +#define _QSPI_DEVINSTRRDCONFIG_DDREN_SHIFT 10 /**< Shift value for QSPI_DDREN */ +#define _QSPI_DEVINSTRRDCONFIG_DDREN_MASK 0x400UL /**< Bit mask for QSPI_DDREN */ +#define _QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT (_QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_SHIFT 12 /**< Shift value for QSPI_ADDRXFERTYPESTDMODE */ +#define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_MASK 0x3000UL /**< Bit mask for QSPI_ADDRXFERTYPESTDMODE */ +#define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_SHIFT 16 /**< Shift value for QSPI_DATAXFERTYPEEXTMODE */ +#define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_MASK 0x30000UL /**< Bit mask for QSPI_DATAXFERTYPEEXTMODE */ +#define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define QSPI_DEVINSTRRDCONFIG_MODEBITENABLE (0x1UL << 20) /**< Mode Bit Enable */ +#define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_SHIFT 20 /**< Shift value for QSPI_MODEBITENABLE */ +#define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_MASK 0x100000UL /**< Bit mask for QSPI_MODEBITENABLE */ +#define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT << 20) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_SHIFT 24 /**< Shift value for QSPI_DUMMYRDCLKCYCLES */ +#define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_MASK 0x1F000000UL /**< Bit mask for QSPI_DUMMYRDCLKCYCLES */ +#define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ +#define QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT (_QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ + +/* Bit fields for QSPI DEVINSTRWRCONFIG */ +#define _QSPI_DEVINSTRWRCONFIG_RESETVALUE 0x00000002UL /**< Default value for QSPI_DEVINSTRWRCONFIG */ +#define _QSPI_DEVINSTRWRCONFIG_MASK 0x1F0331FFUL /**< Mask for QSPI_DEVINSTRWRCONFIG */ +#define _QSPI_DEVINSTRWRCONFIG_WROPCODE_SHIFT 0 /**< Shift value for QSPI_WROPCODE */ +#define _QSPI_DEVINSTRWRCONFIG_WROPCODE_MASK 0xFFUL /**< Bit mask for QSPI_WROPCODE */ +#define _QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ +#define QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT (_QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ +#define QSPI_DEVINSTRWRCONFIG_WELDIS (0x1UL << 8) /**< WEL Disable */ +#define _QSPI_DEVINSTRWRCONFIG_WELDIS_SHIFT 8 /**< Shift value for QSPI_WELDIS */ +#define _QSPI_DEVINSTRWRCONFIG_WELDIS_MASK 0x100UL /**< Bit mask for QSPI_WELDIS */ +#define _QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ +#define QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT (_QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ +#define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_SHIFT 12 /**< Shift value for QSPI_ADDRXFERTYPESTDMODE */ +#define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_MASK 0x3000UL /**< Bit mask for QSPI_ADDRXFERTYPESTDMODE */ +#define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ +#define QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT (_QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ +#define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_SHIFT 16 /**< Shift value for QSPI_DATAXFERTYPEEXTMODE */ +#define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_MASK 0x30000UL /**< Bit mask for QSPI_DATAXFERTYPEEXTMODE */ +#define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ +#define QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT (_QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ +#define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_SHIFT 24 /**< Shift value for QSPI_DUMMYWRCLKCYCLES */ +#define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_MASK 0x1F000000UL /**< Bit mask for QSPI_DUMMYWRCLKCYCLES */ +#define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ +#define QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT (_QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ + +/* Bit fields for QSPI DEVDELAY */ +#define _QSPI_DEVDELAY_RESETVALUE 0x00000000UL /**< Default value for QSPI_DEVDELAY */ +#define _QSPI_DEVDELAY_MASK 0xFFFFFFFFUL /**< Mask for QSPI_DEVDELAY */ +#define _QSPI_DEVDELAY_DINIT_SHIFT 0 /**< Shift value for QSPI_DINIT */ +#define _QSPI_DEVDELAY_DINIT_MASK 0xFFUL /**< Bit mask for QSPI_DINIT */ +#define _QSPI_DEVDELAY_DINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */ +#define QSPI_DEVDELAY_DINIT_DEFAULT (_QSPI_DEVDELAY_DINIT_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */ +#define _QSPI_DEVDELAY_DAFTER_SHIFT 8 /**< Shift value for QSPI_DAFTER */ +#define _QSPI_DEVDELAY_DAFTER_MASK 0xFF00UL /**< Bit mask for QSPI_DAFTER */ +#define _QSPI_DEVDELAY_DAFTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */ +#define QSPI_DEVDELAY_DAFTER_DEFAULT (_QSPI_DEVDELAY_DAFTER_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */ +#define _QSPI_DEVDELAY_DBTWN_SHIFT 16 /**< Shift value for QSPI_DBTWN */ +#define _QSPI_DEVDELAY_DBTWN_MASK 0xFF0000UL /**< Bit mask for QSPI_DBTWN */ +#define _QSPI_DEVDELAY_DBTWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */ +#define QSPI_DEVDELAY_DBTWN_DEFAULT (_QSPI_DEVDELAY_DBTWN_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */ +#define _QSPI_DEVDELAY_DNSS_SHIFT 24 /**< Shift value for QSPI_DNSS */ +#define _QSPI_DEVDELAY_DNSS_MASK 0xFF000000UL /**< Bit mask for QSPI_DNSS */ +#define _QSPI_DEVDELAY_DNSS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */ +#define QSPI_DEVDELAY_DNSS_DEFAULT (_QSPI_DEVDELAY_DNSS_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */ + +/* Bit fields for QSPI RDDATACAPTURE */ +#define _QSPI_RDDATACAPTURE_RESETVALUE 0x00000001UL /**< Default value for QSPI_RDDATACAPTURE */ +#define _QSPI_RDDATACAPTURE_MASK 0x000F011FUL /**< Mask for QSPI_RDDATACAPTURE */ +#define QSPI_RDDATACAPTURE_BYPASS (0x1UL << 0) /**< Bypass the Adapted Loopback Clock Circuit */ +#define _QSPI_RDDATACAPTURE_BYPASS_SHIFT 0 /**< Shift value for QSPI_BYPASS */ +#define _QSPI_RDDATACAPTURE_BYPASS_MASK 0x1UL /**< Bit mask for QSPI_BYPASS */ +#define _QSPI_RDDATACAPTURE_BYPASS_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */ +#define QSPI_RDDATACAPTURE_BYPASS_DEFAULT (_QSPI_RDDATACAPTURE_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */ +#define _QSPI_RDDATACAPTURE_DELAY_SHIFT 1 /**< Shift value for QSPI_DELAY */ +#define _QSPI_RDDATACAPTURE_DELAY_MASK 0x1EUL /**< Bit mask for QSPI_DELAY */ +#define _QSPI_RDDATACAPTURE_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */ +#define QSPI_RDDATACAPTURE_DELAY_DEFAULT (_QSPI_RDDATACAPTURE_DELAY_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */ +#define QSPI_RDDATACAPTURE_DQSENABLE (0x1UL << 8) /**< DQS Enable Bit */ +#define _QSPI_RDDATACAPTURE_DQSENABLE_SHIFT 8 /**< Shift value for QSPI_DQSENABLE */ +#define _QSPI_RDDATACAPTURE_DQSENABLE_MASK 0x100UL /**< Bit mask for QSPI_DQSENABLE */ +#define _QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */ +#define QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT (_QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */ +#define _QSPI_RDDATACAPTURE_DDRREADDELAY_SHIFT 16 /**< Shift value for QSPI_DDRREADDELAY */ +#define _QSPI_RDDATACAPTURE_DDRREADDELAY_MASK 0xF0000UL /**< Bit mask for QSPI_DDRREADDELAY */ +#define _QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */ +#define QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT (_QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */ + +/* Bit fields for QSPI DEVSIZECONFIG */ +#define _QSPI_DEVSIZECONFIG_RESETVALUE 0x00101002UL /**< Default value for QSPI_DEVSIZECONFIG */ +#define _QSPI_DEVSIZECONFIG_MASK 0x01FFFFFFUL /**< Mask for QSPI_DEVSIZECONFIG */ +#define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_SHIFT 0 /**< Shift value for QSPI_NUMADDRBYTES */ +#define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_MASK 0xFUL /**< Bit mask for QSPI_NUMADDRBYTES */ +#define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */ +#define QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT (_QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */ +#define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_SHIFT 4 /**< Shift value for QSPI_BYTESPERDEVICEPAGE */ +#define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_MASK 0xFFF0UL /**< Bit mask for QSPI_BYTESPERDEVICEPAGE */ +#define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT 0x00000100UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */ +#define QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT (_QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */ +#define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_SHIFT 16 /**< Shift value for QSPI_BYTESPERSUBSECTOR */ +#define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_MASK 0x1F0000UL /**< Bit mask for QSPI_BYTESPERSUBSECTOR */ +#define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT 0x00000010UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */ +#define QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT (_QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */ +#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_SHIFT 21 /**< Shift value for QSPI_MEMSIZEONCS0 */ +#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_MASK 0x600000UL /**< Bit mask for QSPI_MEMSIZEONCS0 */ +#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */ +#define QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT (_QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT << 21) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */ +#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_SHIFT 23 /**< Shift value for QSPI_MEMSIZEONCS1 */ +#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_MASK 0x1800000UL /**< Bit mask for QSPI_MEMSIZEONCS1 */ +#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */ +#define QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT (_QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT << 23) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */ + +/* Bit fields for QSPI SRAMPARTITIONCFG */ +#define _QSPI_SRAMPARTITIONCFG_RESETVALUE 0x00000080UL /**< Default value for QSPI_SRAMPARTITIONCFG */ +#define _QSPI_SRAMPARTITIONCFG_MASK 0x000000FFUL /**< Mask for QSPI_SRAMPARTITIONCFG */ +#define _QSPI_SRAMPARTITIONCFG_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */ +#define _QSPI_SRAMPARTITIONCFG_ADDR_MASK 0xFFUL /**< Bit mask for QSPI_ADDR */ +#define _QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT 0x00000080UL /**< Mode DEFAULT for QSPI_SRAMPARTITIONCFG */ +#define QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT (_QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_SRAMPARTITIONCFG */ + +/* Bit fields for QSPI INDAHBADDRTRIGGER */ +#define _QSPI_INDAHBADDRTRIGGER_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDAHBADDRTRIGGER */ +#define _QSPI_INDAHBADDRTRIGGER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDAHBADDRTRIGGER */ +#define _QSPI_INDAHBADDRTRIGGER_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */ +#define _QSPI_INDAHBADDRTRIGGER_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */ +#define _QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDAHBADDRTRIGGER */ +#define QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT (_QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDAHBADDRTRIGGER */ + +/* Bit fields for QSPI REMAPADDR */ +#define _QSPI_REMAPADDR_RESETVALUE 0x00000000UL /**< Default value for QSPI_REMAPADDR */ +#define _QSPI_REMAPADDR_MASK 0xFFFFFFFFUL /**< Mask for QSPI_REMAPADDR */ +#define _QSPI_REMAPADDR_VALUE_SHIFT 0 /**< Shift value for QSPI_VALUE */ +#define _QSPI_REMAPADDR_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_VALUE */ +#define _QSPI_REMAPADDR_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_REMAPADDR */ +#define QSPI_REMAPADDR_VALUE_DEFAULT (_QSPI_REMAPADDR_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_REMAPADDR */ + +/* Bit fields for QSPI MODEBITCONFIG */ +#define _QSPI_MODEBITCONFIG_RESETVALUE 0x00000200UL /**< Default value for QSPI_MODEBITCONFIG */ +#define _QSPI_MODEBITCONFIG_MASK 0xFFFF87FFUL /**< Mask for QSPI_MODEBITCONFIG */ +#define _QSPI_MODEBITCONFIG_MODE_SHIFT 0 /**< Shift value for QSPI_MODE */ +#define _QSPI_MODEBITCONFIG_MODE_MASK 0xFFUL /**< Bit mask for QSPI_MODE */ +#define _QSPI_MODEBITCONFIG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */ +#define QSPI_MODEBITCONFIG_MODE_DEFAULT (_QSPI_MODEBITCONFIG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */ +#define _QSPI_MODEBITCONFIG_CHUNKSIZE_SHIFT 8 /**< Shift value for QSPI_CHUNKSIZE */ +#define _QSPI_MODEBITCONFIG_CHUNKSIZE_MASK 0x700UL /**< Bit mask for QSPI_CHUNKSIZE */ +#define _QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */ +#define QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT (_QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */ +#define QSPI_MODEBITCONFIG_CRCOUTENABLE (0x1UL << 15) /**< CRC# Output Enable Bit */ +#define _QSPI_MODEBITCONFIG_CRCOUTENABLE_SHIFT 15 /**< Shift value for QSPI_CRCOUTENABLE */ +#define _QSPI_MODEBITCONFIG_CRCOUTENABLE_MASK 0x8000UL /**< Bit mask for QSPI_CRCOUTENABLE */ +#define _QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */ +#define QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT (_QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT << 15) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */ +#define _QSPI_MODEBITCONFIG_RXCRCDATAUP_SHIFT 16 /**< Shift value for QSPI_RXCRCDATAUP */ +#define _QSPI_MODEBITCONFIG_RXCRCDATAUP_MASK 0xFF0000UL /**< Bit mask for QSPI_RXCRCDATAUP */ +#define _QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */ +#define QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT (_QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */ +#define _QSPI_MODEBITCONFIG_RXCRCDATALOW_SHIFT 24 /**< Shift value for QSPI_RXCRCDATALOW */ +#define _QSPI_MODEBITCONFIG_RXCRCDATALOW_MASK 0xFF000000UL /**< Bit mask for QSPI_RXCRCDATALOW */ +#define _QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */ +#define QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT (_QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */ + +/* Bit fields for QSPI SRAMFILL */ +#define _QSPI_SRAMFILL_RESETVALUE 0x00000000UL /**< Default value for QSPI_SRAMFILL */ +#define _QSPI_SRAMFILL_MASK 0xFFFFFFFFUL /**< Mask for QSPI_SRAMFILL */ +#define _QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT 0 /**< Shift value for QSPI_SRAMFILLINDACREAD */ +#define _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK 0xFFFFUL /**< Bit mask for QSPI_SRAMFILLINDACREAD */ +#define _QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_SRAMFILL */ +#define QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT (_QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_SRAMFILL */ +#define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT 16 /**< Shift value for QSPI_SRAMFILLINDACWRITE */ +#define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK 0xFFFF0000UL /**< Bit mask for QSPI_SRAMFILLINDACWRITE */ +#define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_SRAMFILL */ +#define QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT (_QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_SRAMFILL */ + +/* Bit fields for QSPI TXTHRESH */ +#define _QSPI_TXTHRESH_RESETVALUE 0x00000001UL /**< Default value for QSPI_TXTHRESH */ +#define _QSPI_TXTHRESH_MASK 0x0000001FUL /**< Mask for QSPI_TXTHRESH */ +#define _QSPI_TXTHRESH_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */ +#define _QSPI_TXTHRESH_LEVEL_MASK 0x1FUL /**< Bit mask for QSPI_LEVEL */ +#define _QSPI_TXTHRESH_LEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_TXTHRESH */ +#define QSPI_TXTHRESH_LEVEL_DEFAULT (_QSPI_TXTHRESH_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_TXTHRESH */ + +/* Bit fields for QSPI RXTHRESH */ +#define _QSPI_RXTHRESH_RESETVALUE 0x00000001UL /**< Default value for QSPI_RXTHRESH */ +#define _QSPI_RXTHRESH_MASK 0x0000001FUL /**< Mask for QSPI_RXTHRESH */ +#define _QSPI_RXTHRESH_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */ +#define _QSPI_RXTHRESH_LEVEL_MASK 0x1FUL /**< Bit mask for QSPI_LEVEL */ +#define _QSPI_RXTHRESH_LEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_RXTHRESH */ +#define QSPI_RXTHRESH_LEVEL_DEFAULT (_QSPI_RXTHRESH_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_RXTHRESH */ + +/* Bit fields for QSPI WRITECOMPLETIONCTRL */ +#define _QSPI_WRITECOMPLETIONCTRL_RESETVALUE 0x00010005UL /**< Default value for QSPI_WRITECOMPLETIONCTRL */ +#define _QSPI_WRITECOMPLETIONCTRL_MASK 0xFFFFE7FFUL /**< Mask for QSPI_WRITECOMPLETIONCTRL */ +#define _QSPI_WRITECOMPLETIONCTRL_OPCODE_SHIFT 0 /**< Shift value for QSPI_OPCODE */ +#define _QSPI_WRITECOMPLETIONCTRL_OPCODE_MASK 0xFFUL /**< Bit mask for QSPI_OPCODE */ +#define _QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT 0x00000005UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_SHIFT 8 /**< Shift value for QSPI_POLLINGBITINDEX */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_MASK 0x700UL /**< Bit mask for QSPI_POLLINGBITINDEX */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY (0x1UL << 13) /**< Polling Polarity */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_SHIFT 13 /**< Shift value for QSPI_POLLINGPOLARITY */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_MASK 0x2000UL /**< Bit mask for QSPI_POLLINGPOLARITY */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING (0x1UL << 14) /**< Disable Polling */ +#define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_SHIFT 14 /**< Shift value for QSPI_DISABLEPOLLING */ +#define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_MASK 0x4000UL /**< Bit mask for QSPI_DISABLEPOLLING */ +#define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP (0x1UL << 15) /**< Enable Polling Expiration */ +#define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_SHIFT 15 /**< Shift value for QSPI_ENABLEPOLLINGEXP */ +#define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_MASK 0x8000UL /**< Bit mask for QSPI_ENABLEPOLLINGEXP */ +#define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT << 15) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_SHIFT 16 /**< Shift value for QSPI_POLLCOUNT */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_MASK 0xFF0000UL /**< Bit mask for QSPI_POLLCOUNT */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_SHIFT 24 /**< Shift value for QSPI_POLLREPDELAY */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_MASK 0xFF000000UL /**< Bit mask for QSPI_POLLREPDELAY */ +#define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ +#define QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ + +/* Bit fields for QSPI NOOFPOLLSBEFEXP */ +#define _QSPI_NOOFPOLLSBEFEXP_RESETVALUE 0xFFFFFFFFUL /**< Default value for QSPI_NOOFPOLLSBEFEXP */ +#define _QSPI_NOOFPOLLSBEFEXP_MASK 0xFFFFFFFFUL /**< Mask for QSPI_NOOFPOLLSBEFEXP */ +#define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_SHIFT 0 /**< Shift value for QSPI_NOOFPOLLSBEFEXP */ +#define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_NOOFPOLLSBEFEXP */ +#define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for QSPI_NOOFPOLLSBEFEXP */ +#define QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT (_QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_NOOFPOLLSBEFEXP */ + +/* Bit fields for QSPI IRQSTATUS */ +#define _QSPI_IRQSTATUS_RESETVALUE 0x00000000UL /**< Default value for QSPI_IRQSTATUS */ +#define _QSPI_IRQSTATUS_MASK 0x00077FFFUL /**< Mask for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_MODEMFAIL (0x1UL << 0) /**< Mode M Failure */ +#define _QSPI_IRQSTATUS_MODEMFAIL_SHIFT 0 /**< Shift value for QSPI_MODEMFAIL */ +#define _QSPI_IRQSTATUS_MODEMFAIL_MASK 0x1UL /**< Bit mask for QSPI_MODEMFAIL */ +#define _QSPI_IRQSTATUS_MODEMFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_MODEMFAIL_DEFAULT (_QSPI_IRQSTATUS_MODEMFAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_UNDERFLOWDET (0x1UL << 1) /**< Underflow Detected */ +#define _QSPI_IRQSTATUS_UNDERFLOWDET_SHIFT 1 /**< Shift value for QSPI_UNDERFLOWDET */ +#define _QSPI_IRQSTATUS_UNDERFLOWDET_MASK 0x2UL /**< Bit mask for QSPI_UNDERFLOWDET */ +#define _QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT (_QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_INDIRECTOPDONE (0x1UL << 2) /**< Indirect Operation Complete */ +#define _QSPI_IRQSTATUS_INDIRECTOPDONE_SHIFT 2 /**< Shift value for QSPI_INDIRECTOPDONE */ +#define _QSPI_IRQSTATUS_INDIRECTOPDONE_MASK 0x4UL /**< Bit mask for QSPI_INDIRECTOPDONE */ +#define _QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT (_QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_INDIRECTREADREJECT (0x1UL << 3) /**< Indirect Operation Was Requested but Could Not Be Accepted */ +#define _QSPI_IRQSTATUS_INDIRECTREADREJECT_SHIFT 3 /**< Shift value for QSPI_INDIRECTREADREJECT */ +#define _QSPI_IRQSTATUS_INDIRECTREADREJECT_MASK 0x8UL /**< Bit mask for QSPI_INDIRECTREADREJECT */ +#define _QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT (_QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_PROTWRATTEMPT (0x1UL << 4) /**< Write to Protected Area Was Attempted and Rejected */ +#define _QSPI_IRQSTATUS_PROTWRATTEMPT_SHIFT 4 /**< Shift value for QSPI_PROTWRATTEMPT */ +#define _QSPI_IRQSTATUS_PROTWRATTEMPT_MASK 0x10UL /**< Bit mask for QSPI_PROTWRATTEMPT */ +#define _QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT (_QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_ILLEGALACCESSDET (0x1UL << 5) /**< Illegal Memory Access Has Been Detected */ +#define _QSPI_IRQSTATUS_ILLEGALACCESSDET_SHIFT 5 /**< Shift value for QSPI_ILLEGALACCESSDET */ +#define _QSPI_IRQSTATUS_ILLEGALACCESSDET_MASK 0x20UL /**< Bit mask for QSPI_ILLEGALACCESSDET */ +#define _QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT (_QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH (0x1UL << 6) /**< Indirect Transfer Watermark Level Breached */ +#define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_SHIFT 6 /**< Shift value for QSPI_INDIRECTXFERLEVELBREACH */ +#define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_MASK 0x40UL /**< Bit mask for QSPI_INDIRECTXFERLEVELBREACH */ +#define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT (_QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_RECVOVERFLOW (0x1UL << 7) /**< Receive Overflow */ +#define _QSPI_IRQSTATUS_RECVOVERFLOW_SHIFT 7 /**< Shift value for QSPI_RECVOVERFLOW */ +#define _QSPI_IRQSTATUS_RECVOVERFLOW_MASK 0x80UL /**< Bit mask for QSPI_RECVOVERFLOW */ +#define _QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT (_QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_TXFIFONOTFULL (0x1UL << 8) /**< Small TX FIFO Not Full */ +#define _QSPI_IRQSTATUS_TXFIFONOTFULL_SHIFT 8 /**< Shift value for QSPI_TXFIFONOTFULL */ +#define _QSPI_IRQSTATUS_TXFIFONOTFULL_MASK 0x100UL /**< Bit mask for QSPI_TXFIFONOTFULL */ +#define _QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT (_QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_TXFIFOFULL (0x1UL << 9) /**< Small TX FIFO Full */ +#define _QSPI_IRQSTATUS_TXFIFOFULL_SHIFT 9 /**< Shift value for QSPI_TXFIFOFULL */ +#define _QSPI_IRQSTATUS_TXFIFOFULL_MASK 0x200UL /**< Bit mask for QSPI_TXFIFOFULL */ +#define _QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT (_QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_RXFIFONOTEMPTY (0x1UL << 10) /**< Small RX FIFO Not Empty */ +#define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_SHIFT 10 /**< Shift value for QSPI_RXFIFONOTEMPTY */ +#define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_MASK 0x400UL /**< Bit mask for QSPI_RXFIFONOTEMPTY */ +#define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT (_QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_RXFIFOFULL (0x1UL << 11) /**< Small RX FIFO Full */ +#define _QSPI_IRQSTATUS_RXFIFOFULL_SHIFT 11 /**< Shift value for QSPI_RXFIFOFULL */ +#define _QSPI_IRQSTATUS_RXFIFOFULL_MASK 0x800UL /**< Bit mask for QSPI_RXFIFOFULL */ +#define _QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT (_QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT << 11) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_INDRDSRAMFULL (0x1UL << 12) /**< Indirect Read Partition Overflow */ +#define _QSPI_IRQSTATUS_INDRDSRAMFULL_SHIFT 12 /**< Shift value for QSPI_INDRDSRAMFULL */ +#define _QSPI_IRQSTATUS_INDRDSRAMFULL_MASK 0x1000UL /**< Bit mask for QSPI_INDRDSRAMFULL */ +#define _QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT (_QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_POLLEXPINT (0x1UL << 13) /**< The Maximum Number of Programmed Polls Cycles is Expired */ +#define _QSPI_IRQSTATUS_POLLEXPINT_SHIFT 13 /**< Shift value for QSPI_POLLEXPINT */ +#define _QSPI_IRQSTATUS_POLLEXPINT_MASK 0x2000UL /**< Bit mask for QSPI_POLLEXPINT */ +#define _QSPI_IRQSTATUS_POLLEXPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_POLLEXPINT_DEFAULT (_QSPI_IRQSTATUS_POLLEXPINT_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_STIGREQINT (0x1UL << 14) /**< The Controller is Ready for Getting Another STIG Request */ +#define _QSPI_IRQSTATUS_STIGREQINT_SHIFT 14 /**< Shift value for QSPI_STIGREQINT */ +#define _QSPI_IRQSTATUS_STIGREQINT_MASK 0x4000UL /**< Bit mask for QSPI_STIGREQINT */ +#define _QSPI_IRQSTATUS_STIGREQINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_STIGREQINT_DEFAULT (_QSPI_IRQSTATUS_STIGREQINT_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_RXCRCDATAERR (0x1UL << 16) /**< RX CRC Data Error */ +#define _QSPI_IRQSTATUS_RXCRCDATAERR_SHIFT 16 /**< Shift value for QSPI_RXCRCDATAERR */ +#define _QSPI_IRQSTATUS_RXCRCDATAERR_MASK 0x10000UL /**< Bit mask for QSPI_RXCRCDATAERR */ +#define _QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT (_QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_RXCRCDATAVAL (0x1UL << 17) /**< RX CRC Data Valid */ +#define _QSPI_IRQSTATUS_RXCRCDATAVAL_SHIFT 17 /**< Shift value for QSPI_RXCRCDATAVAL */ +#define _QSPI_IRQSTATUS_RXCRCDATAVAL_MASK 0x20000UL /**< Bit mask for QSPI_RXCRCDATAVAL */ +#define _QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT (_QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT << 17) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_TXCRCCHUNKBRK (0x1UL << 18) /**< TX CRC Chunk Was Broken */ +#define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_SHIFT 18 /**< Shift value for QSPI_TXCRCCHUNKBRK */ +#define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_MASK 0x40000UL /**< Bit mask for QSPI_TXCRCCHUNKBRK */ +#define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ +#define QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT (_QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ + +/* Bit fields for QSPI IRQMASK */ +#define _QSPI_IRQMASK_RESETVALUE 0x00000000UL /**< Default value for QSPI_IRQMASK */ +#define _QSPI_IRQMASK_MASK 0x00077FFFUL /**< Mask for QSPI_IRQMASK */ +#define QSPI_IRQMASK_MODEMFAILMASK (0x1UL << 0) /**< Mode M Failure Mask */ +#define _QSPI_IRQMASK_MODEMFAILMASK_SHIFT 0 /**< Shift value for QSPI_MODEMFAILMASK */ +#define _QSPI_IRQMASK_MODEMFAILMASK_MASK 0x1UL /**< Bit mask for QSPI_MODEMFAILMASK */ +#define _QSPI_IRQMASK_MODEMFAILMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_MODEMFAILMASK_DEFAULT (_QSPI_IRQMASK_MODEMFAILMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_UNDERFLOWDETMASK (0x1UL << 1) /**< Underflow Detected Mask */ +#define _QSPI_IRQMASK_UNDERFLOWDETMASK_SHIFT 1 /**< Shift value for QSPI_UNDERFLOWDETMASK */ +#define _QSPI_IRQMASK_UNDERFLOWDETMASK_MASK 0x2UL /**< Bit mask for QSPI_UNDERFLOWDETMASK */ +#define _QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT (_QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_INDIRECTOPDONEMASK (0x1UL << 2) /**< Indirect Complete Mask */ +#define _QSPI_IRQMASK_INDIRECTOPDONEMASK_SHIFT 2 /**< Shift value for QSPI_INDIRECTOPDONEMASK */ +#define _QSPI_IRQMASK_INDIRECTOPDONEMASK_MASK 0x4UL /**< Bit mask for QSPI_INDIRECTOPDONEMASK */ +#define _QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT (_QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_INDIRECTREADREJECTMASK (0x1UL << 3) /**< Indirect Read Reject Mask */ +#define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_SHIFT 3 /**< Shift value for QSPI_INDIRECTREADREJECTMASK */ +#define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_MASK 0x8UL /**< Bit mask for QSPI_INDIRECTREADREJECTMASK */ +#define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT (_QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_PROTWRATTEMPTMASK (0x1UL << 4) /**< Protected Area Write Attempt Mask */ +#define _QSPI_IRQMASK_PROTWRATTEMPTMASK_SHIFT 4 /**< Shift value for QSPI_PROTWRATTEMPTMASK */ +#define _QSPI_IRQMASK_PROTWRATTEMPTMASK_MASK 0x10UL /**< Bit mask for QSPI_PROTWRATTEMPTMASK */ +#define _QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT (_QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_ILLEGALACCESSDETMASK (0x1UL << 5) /**< Illegal Access Detected Mask */ +#define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_SHIFT 5 /**< Shift value for QSPI_ILLEGALACCESSDETMASK */ +#define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_MASK 0x20UL /**< Bit mask for QSPI_ILLEGALACCESSDETMASK */ +#define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT (_QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK (0x1UL << 6) /**< Transfer Watermark Breach Mask */ +#define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_SHIFT 6 /**< Shift value for QSPI_INDIRECTXFERLEVELBREACHMASK */ +#define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_MASK 0x40UL /**< Bit mask for QSPI_INDIRECTXFERLEVELBREACHMASK */ +#define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT (_QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_RECVOVERFLOWMASK (0x1UL << 7) /**< Receive Overflow Mask */ +#define _QSPI_IRQMASK_RECVOVERFLOWMASK_SHIFT 7 /**< Shift value for QSPI_RECVOVERFLOWMASK */ +#define _QSPI_IRQMASK_RECVOVERFLOWMASK_MASK 0x80UL /**< Bit mask for QSPI_RECVOVERFLOWMASK */ +#define _QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT (_QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_TXFIFONOTFULLMASK (0x1UL << 8) /**< Small TX FIFO Not Full Mask */ +#define _QSPI_IRQMASK_TXFIFONOTFULLMASK_SHIFT 8 /**< Shift value for QSPI_TXFIFONOTFULLMASK */ +#define _QSPI_IRQMASK_TXFIFONOTFULLMASK_MASK 0x100UL /**< Bit mask for QSPI_TXFIFONOTFULLMASK */ +#define _QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT (_QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_TXFIFOFULLMASK (0x1UL << 9) /**< Small TX FIFO Full Mask */ +#define _QSPI_IRQMASK_TXFIFOFULLMASK_SHIFT 9 /**< Shift value for QSPI_TXFIFOFULLMASK */ +#define _QSPI_IRQMASK_TXFIFOFULLMASK_MASK 0x200UL /**< Bit mask for QSPI_TXFIFOFULLMASK */ +#define _QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT (_QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_RXFIFONOTEMPTYMASK (0x1UL << 10) /**< Small RX FIFO Not Empty Mask */ +#define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_SHIFT 10 /**< Shift value for QSPI_RXFIFONOTEMPTYMASK */ +#define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_MASK 0x400UL /**< Bit mask for QSPI_RXFIFONOTEMPTYMASK */ +#define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT (_QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_RXFIFOFULLMASK (0x1UL << 11) /**< Small RX FIFO Full Mask */ +#define _QSPI_IRQMASK_RXFIFOFULLMASK_SHIFT 11 /**< Shift value for QSPI_RXFIFOFULLMASK */ +#define _QSPI_IRQMASK_RXFIFOFULLMASK_MASK 0x800UL /**< Bit mask for QSPI_RXFIFOFULLMASK */ +#define _QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT (_QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT << 11) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_INDRDSRAMFULLMASK (0x1UL << 12) /**< Indirect Read Partition Overflow Mask */ +#define _QSPI_IRQMASK_INDRDSRAMFULLMASK_SHIFT 12 /**< Shift value for QSPI_INDRDSRAMFULLMASK */ +#define _QSPI_IRQMASK_INDRDSRAMFULLMASK_MASK 0x1000UL /**< Bit mask for QSPI_INDRDSRAMFULLMASK */ +#define _QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT (_QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_POLLEXPINTMASK (0x1UL << 13) /**< Polling Expiration Detected Mask */ +#define _QSPI_IRQMASK_POLLEXPINTMASK_SHIFT 13 /**< Shift value for QSPI_POLLEXPINTMASK */ +#define _QSPI_IRQMASK_POLLEXPINTMASK_MASK 0x2000UL /**< Bit mask for QSPI_POLLEXPINTMASK */ +#define _QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT (_QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_STIGREQMASK (0x1UL << 14) /**< STIG Request Completion Mask */ +#define _QSPI_IRQMASK_STIGREQMASK_SHIFT 14 /**< Shift value for QSPI_STIGREQMASK */ +#define _QSPI_IRQMASK_STIGREQMASK_MASK 0x4000UL /**< Bit mask for QSPI_STIGREQMASK */ +#define _QSPI_IRQMASK_STIGREQMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_STIGREQMASK_DEFAULT (_QSPI_IRQMASK_STIGREQMASK_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_RXCRCDATAERRMASK (0x1UL << 16) /**< RX CRC Data Error Mask */ +#define _QSPI_IRQMASK_RXCRCDATAERRMASK_SHIFT 16 /**< Shift value for QSPI_RXCRCDATAERRMASK */ +#define _QSPI_IRQMASK_RXCRCDATAERRMASK_MASK 0x10000UL /**< Bit mask for QSPI_RXCRCDATAERRMASK */ +#define _QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT (_QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_RXCRCDATAVALMASK (0x1UL << 17) /**< RX CRC Data Valid Mask */ +#define _QSPI_IRQMASK_RXCRCDATAVALMASK_SHIFT 17 /**< Shift value for QSPI_RXCRCDATAVALMASK */ +#define _QSPI_IRQMASK_RXCRCDATAVALMASK_MASK 0x20000UL /**< Bit mask for QSPI_RXCRCDATAVALMASK */ +#define _QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT (_QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT << 17) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_TXCRCCHUNKBRKMASK (0x1UL << 18) /**< TX CRC Chunk Was Broken Mask */ +#define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_SHIFT 18 /**< Shift value for QSPI_TXCRCCHUNKBRKMASK */ +#define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_MASK 0x40000UL /**< Bit mask for QSPI_TXCRCCHUNKBRKMASK */ +#define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ +#define QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT (_QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ + +/* Bit fields for QSPI LOWERWRPROT */ +#define _QSPI_LOWERWRPROT_RESETVALUE 0x00000000UL /**< Default value for QSPI_LOWERWRPROT */ +#define _QSPI_LOWERWRPROT_MASK 0xFFFFFFFFUL /**< Mask for QSPI_LOWERWRPROT */ +#define _QSPI_LOWERWRPROT_SUBSECTOR_SHIFT 0 /**< Shift value for QSPI_SUBSECTOR */ +#define _QSPI_LOWERWRPROT_SUBSECTOR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_SUBSECTOR */ +#define _QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_LOWERWRPROT */ +#define QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT (_QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_LOWERWRPROT */ + +/* Bit fields for QSPI UPPERWRPROT */ +#define _QSPI_UPPERWRPROT_RESETVALUE 0x00000000UL /**< Default value for QSPI_UPPERWRPROT */ +#define _QSPI_UPPERWRPROT_MASK 0xFFFFFFFFUL /**< Mask for QSPI_UPPERWRPROT */ +#define _QSPI_UPPERWRPROT_SUBSECTOR_SHIFT 0 /**< Shift value for QSPI_SUBSECTOR */ +#define _QSPI_UPPERWRPROT_SUBSECTOR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_SUBSECTOR */ +#define _QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_UPPERWRPROT */ +#define QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT (_QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_UPPERWRPROT */ + +/* Bit fields for QSPI WRPROTCTRL */ +#define _QSPI_WRPROTCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_WRPROTCTRL */ +#define _QSPI_WRPROTCTRL_MASK 0x00000003UL /**< Mask for QSPI_WRPROTCTRL */ +#define QSPI_WRPROTCTRL_INV (0x1UL << 0) /**< Write Protection Inversion Bit */ +#define _QSPI_WRPROTCTRL_INV_SHIFT 0 /**< Shift value for QSPI_INV */ +#define _QSPI_WRPROTCTRL_INV_MASK 0x1UL /**< Bit mask for QSPI_INV */ +#define _QSPI_WRPROTCTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRPROTCTRL */ +#define QSPI_WRPROTCTRL_INV_DEFAULT (_QSPI_WRPROTCTRL_INV_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_WRPROTCTRL */ +#define QSPI_WRPROTCTRL_ENB (0x1UL << 1) /**< Write Protection Enable Bit */ +#define _QSPI_WRPROTCTRL_ENB_SHIFT 1 /**< Shift value for QSPI_ENB */ +#define _QSPI_WRPROTCTRL_ENB_MASK 0x2UL /**< Bit mask for QSPI_ENB */ +#define _QSPI_WRPROTCTRL_ENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRPROTCTRL */ +#define QSPI_WRPROTCTRL_ENB_DEFAULT (_QSPI_WRPROTCTRL_ENB_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_WRPROTCTRL */ + +/* Bit fields for QSPI INDIRECTREADXFERCTRL */ +#define _QSPI_INDIRECTREADXFERCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERCTRL */ +#define _QSPI_INDIRECTREADXFERCTRL_MASK 0x000000FFUL /**< Mask for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_START (0x1UL << 0) /**< Start Indirect Read */ +#define _QSPI_INDIRECTREADXFERCTRL_START_SHIFT 0 /**< Shift value for QSPI_START */ +#define _QSPI_INDIRECTREADXFERCTRL_START_MASK 0x1UL /**< Bit mask for QSPI_START */ +#define _QSPI_INDIRECTREADXFERCTRL_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_START_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_START_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_CANCEL (0x1UL << 1) /**< Cancel Indirect Read */ +#define _QSPI_INDIRECTREADXFERCTRL_CANCEL_SHIFT 1 /**< Shift value for QSPI_CANCEL */ +#define _QSPI_INDIRECTREADXFERCTRL_CANCEL_MASK 0x2UL /**< Bit mask for QSPI_CANCEL */ +#define _QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_RDSTATUS (0x1UL << 2) /**< Indirect Read Status */ +#define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_SHIFT 2 /**< Shift value for QSPI_RDSTATUS */ +#define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_MASK 0x4UL /**< Bit mask for QSPI_RDSTATUS */ +#define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_SRAMFULL (0x1UL << 3) /**< SRAM Full */ +#define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_SHIFT 3 /**< Shift value for QSPI_SRAMFULL */ +#define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_MASK 0x8UL /**< Bit mask for QSPI_SRAMFULL */ +#define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_RDQUEUED (0x1UL << 4) /**< Two Indirect Read Operations Have Been Queued */ +#define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_SHIFT 4 /**< Shift value for QSPI_RDQUEUED */ +#define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_MASK 0x10UL /**< Bit mask for QSPI_RDQUEUED */ +#define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS (0x1UL << 5) /**< Indirect Completion Status */ +#define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_SHIFT 5 /**< Shift value for QSPI_INDOPSDONESTATUS */ +#define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_MASK 0x20UL /**< Bit mask for QSPI_INDOPSDONESTATUS */ +#define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_SHIFT 6 /**< Shift value for QSPI_NUMINDOPSDONE */ +#define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_MASK 0xC0UL /**< Bit mask for QSPI_NUMINDOPSDONE */ +#define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ +#define QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ + +/* Bit fields for QSPI INDIRECTREADXFERWATERMARK */ +#define _QSPI_INDIRECTREADXFERWATERMARK_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERWATERMARK */ +#define _QSPI_INDIRECTREADXFERWATERMARK_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTREADXFERWATERMARK */ +#define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */ +#define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_LEVEL */ +#define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERWATERMARK */ +#define QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT (_QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERWATERMARK */ + +/* Bit fields for QSPI INDIRECTREADXFERSTART */ +#define _QSPI_INDIRECTREADXFERSTART_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERSTART */ +#define _QSPI_INDIRECTREADXFERSTART_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTREADXFERSTART */ +#define _QSPI_INDIRECTREADXFERSTART_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */ +#define _QSPI_INDIRECTREADXFERSTART_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */ +#define _QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERSTART */ +#define QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT (_QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERSTART */ + +/* Bit fields for QSPI INDIRECTREADXFERNUMBYTES */ +#define _QSPI_INDIRECTREADXFERNUMBYTES_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERNUMBYTES */ +#define _QSPI_INDIRECTREADXFERNUMBYTES_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTREADXFERNUMBYTES */ +#define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_SHIFT 0 /**< Shift value for QSPI_VALUE */ +#define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_VALUE */ +#define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERNUMBYTES */ +#define QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT (_QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERNUMBYTES */ + +/* Bit fields for QSPI INDIRECTWRITEXFERCTRL */ +#define _QSPI_INDIRECTWRITEXFERCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTWRITEXFERCTRL */ +#define _QSPI_INDIRECTWRITEXFERCTRL_MASK 0x000000F7UL /**< Mask for QSPI_INDIRECTWRITEXFERCTRL */ +#define QSPI_INDIRECTWRITEXFERCTRL_START (0x1UL << 0) /**< Start Indirect Write */ +#define _QSPI_INDIRECTWRITEXFERCTRL_START_SHIFT 0 /**< Shift value for QSPI_START */ +#define _QSPI_INDIRECTWRITEXFERCTRL_START_MASK 0x1UL /**< Bit mask for QSPI_START */ +#define _QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ +#define QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ +#define QSPI_INDIRECTWRITEXFERCTRL_CANCEL (0x1UL << 1) /**< Cancel Indirect Write */ +#define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_SHIFT 1 /**< Shift value for QSPI_CANCEL */ +#define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_MASK 0x2UL /**< Bit mask for QSPI_CANCEL */ +#define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ +#define QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ +#define QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS (0x1UL << 2) /**< Indirect Write Status */ +#define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_SHIFT 2 /**< Shift value for QSPI_WRSTATUS */ +#define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_MASK 0x4UL /**< Bit mask for QSPI_WRSTATUS */ +#define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ +#define QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ +#define QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED (0x1UL << 4) /**< Two Indirect Write Operations Have Been Queued */ +#define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_SHIFT 4 /**< Shift value for QSPI_WRQUEUED */ +#define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_MASK 0x10UL /**< Bit mask for QSPI_WRQUEUED */ +#define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ +#define QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ +#define QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS (0x1UL << 5) /**< Indirect Completion Status */ +#define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_SHIFT 5 /**< Shift value for QSPI_INDOPSDONESTATUS */ +#define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_MASK 0x20UL /**< Bit mask for QSPI_INDOPSDONESTATUS */ +#define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ +#define QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ +#define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_SHIFT 6 /**< Shift value for QSPI_NUMINDOPSDONE */ +#define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_MASK 0xC0UL /**< Bit mask for QSPI_NUMINDOPSDONE */ +#define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ +#define QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ + +/* Bit fields for QSPI INDIRECTWRITEXFERWATERMARK */ +#define _QSPI_INDIRECTWRITEXFERWATERMARK_RESETVALUE 0xFFFFFFFFUL /**< Default value for QSPI_INDIRECTWRITEXFERWATERMARK */ +#define _QSPI_INDIRECTWRITEXFERWATERMARK_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTWRITEXFERWATERMARK */ +#define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */ +#define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_LEVEL */ +#define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERWATERMARK */ +#define QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT (_QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERWATERMARK */ + +/* Bit fields for QSPI INDIRECTWRITEXFERSTART */ +#define _QSPI_INDIRECTWRITEXFERSTART_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTWRITEXFERSTART */ +#define _QSPI_INDIRECTWRITEXFERSTART_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTWRITEXFERSTART */ +#define _QSPI_INDIRECTWRITEXFERSTART_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */ +#define _QSPI_INDIRECTWRITEXFERSTART_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */ +#define _QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERSTART */ +#define QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT (_QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERSTART */ + +/* Bit fields for QSPI INDIRECTWRITEXFERNUMBYTES */ +#define _QSPI_INDIRECTWRITEXFERNUMBYTES_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTWRITEXFERNUMBYTES */ +#define _QSPI_INDIRECTWRITEXFERNUMBYTES_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTWRITEXFERNUMBYTES */ +#define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_SHIFT 0 /**< Shift value for QSPI_VALUE */ +#define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_VALUE */ +#define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERNUMBYTES */ +#define QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT (_QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERNUMBYTES */ + +/* Bit fields for QSPI INDIRECTTRIGGERADDRRANGE */ +#define _QSPI_INDIRECTTRIGGERADDRRANGE_RESETVALUE 0x00000004UL /**< Default value for QSPI_INDIRECTTRIGGERADDRRANGE */ +#define _QSPI_INDIRECTTRIGGERADDRRANGE_MASK 0x0000000FUL /**< Mask for QSPI_INDIRECTTRIGGERADDRRANGE */ +#define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_SHIFT 0 /**< Shift value for QSPI_INDRANGEWIDTH */ +#define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_MASK 0xFUL /**< Bit mask for QSPI_INDRANGEWIDTH */ +#define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT 0x00000004UL /**< Mode DEFAULT for QSPI_INDIRECTTRIGGERADDRRANGE */ +#define QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT (_QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTTRIGGERADDRRANGE */ + +/* Bit fields for QSPI FLASHCOMMANDCTRLMEM */ +#define _QSPI_FLASHCOMMANDCTRLMEM_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHCOMMANDCTRLMEM */ +#define _QSPI_FLASHCOMMANDCTRLMEM_MASK 0x1FF7FF03UL /**< Mask for QSPI_FLASHCOMMANDCTRLMEM */ +#define QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ (0x1UL << 0) /**< Trigger the Memory Bank Data Request */ +#define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_SHIFT 0 /**< Shift value for QSPI_TRIGGERMEMBANKREQ */ +#define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_MASK 0x1UL /**< Bit mask for QSPI_TRIGGERMEMBANKREQ */ +#define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ +#define QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ +#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS (0x1UL << 1) /**< Memory Bank Data Request in Progress */ +#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_SHIFT 1 /**< Shift value for QSPI_MEMBANKREQINPROGRESS */ +#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_MASK 0x2UL /**< Bit mask for QSPI_MEMBANKREQINPROGRESS */ +#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ +#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ +#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_SHIFT 8 /**< Shift value for QSPI_MEMBANKREADDATA */ +#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_MASK 0xFF00UL /**< Bit mask for QSPI_MEMBANKREADDATA */ +#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ +#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ +#define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_SHIFT 16 /**< Shift value for QSPI_NBOFSTIGREADBYTES */ +#define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_MASK 0x70000UL /**< Bit mask for QSPI_NBOFSTIGREADBYTES */ +#define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ +#define QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ +#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_SHIFT 20 /**< Shift value for QSPI_MEMBANKADDR */ +#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_MASK 0x1FF00000UL /**< Bit mask for QSPI_MEMBANKADDR */ +#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ +#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT << 20) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ + +/* Bit fields for QSPI FLASHCMDCTRL */ +#define _QSPI_FLASHCMDCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHCMDCTRL */ +#define _QSPI_FLASHCMDCTRL_MASK 0xFFFFFF87UL /**< Mask for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_CMDEXEC (0x1UL << 0) /**< Execute the Command */ +#define _QSPI_FLASHCMDCTRL_CMDEXEC_SHIFT 0 /**< Shift value for QSPI_CMDEXEC */ +#define _QSPI_FLASHCMDCTRL_CMDEXEC_MASK 0x1UL /**< Bit mask for QSPI_CMDEXEC */ +#define _QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT (_QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_CMDEXECSTATUS (0x1UL << 1) /**< Command Execution in Progress */ +#define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_SHIFT 1 /**< Shift value for QSPI_CMDEXECSTATUS */ +#define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_MASK 0x2UL /**< Bit mask for QSPI_CMDEXECSTATUS */ +#define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT (_QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_STIGMEMBANKEN (0x1UL << 2) /**< STIG Memory Bank Enable Bit */ +#define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_SHIFT 2 /**< Shift value for QSPI_STIGMEMBANKEN */ +#define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_MASK 0x4UL /**< Bit mask for QSPI_STIGMEMBANKEN */ +#define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT (_QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_SHIFT 7 /**< Shift value for QSPI_NUMDUMMYCYCLES */ +#define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_MASK 0xF80UL /**< Bit mask for QSPI_NUMDUMMYCYCLES */ +#define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_SHIFT 12 /**< Shift value for QSPI_NUMWRDATABYTES */ +#define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_MASK 0x7000UL /**< Bit mask for QSPI_NUMWRDATABYTES */ +#define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_ENBWRITEDATA (0x1UL << 15) /**< Write Data Enable */ +#define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_SHIFT 15 /**< Shift value for QSPI_ENBWRITEDATA */ +#define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_MASK 0x8000UL /**< Bit mask for QSPI_ENBWRITEDATA */ +#define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT (_QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT << 15) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_SHIFT 16 /**< Shift value for QSPI_NUMADDRBYTES */ +#define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_MASK 0x30000UL /**< Bit mask for QSPI_NUMADDRBYTES */ +#define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_ENBMODEBIT (0x1UL << 18) /**< Mode Bit Enable */ +#define _QSPI_FLASHCMDCTRL_ENBMODEBIT_SHIFT 18 /**< Shift value for QSPI_ENBMODEBIT */ +#define _QSPI_FLASHCMDCTRL_ENBMODEBIT_MASK 0x40000UL /**< Bit mask for QSPI_ENBMODEBIT */ +#define _QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT (_QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_ENBCOMDADDR (0x1UL << 19) /**< Command Address Enable */ +#define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_SHIFT 19 /**< Shift value for QSPI_ENBCOMDADDR */ +#define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_MASK 0x80000UL /**< Bit mask for QSPI_ENBCOMDADDR */ +#define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT (_QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT << 19) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_SHIFT 20 /**< Shift value for QSPI_NUMRDDATABYTES */ +#define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_MASK 0x700000UL /**< Bit mask for QSPI_NUMRDDATABYTES */ +#define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT << 20) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_ENBREADDATA (0x1UL << 23) /**< Read Data Enable */ +#define _QSPI_FLASHCMDCTRL_ENBREADDATA_SHIFT 23 /**< Shift value for QSPI_ENBREADDATA */ +#define _QSPI_FLASHCMDCTRL_ENBREADDATA_MASK 0x800000UL /**< Bit mask for QSPI_ENBREADDATA */ +#define _QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT (_QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT << 23) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define _QSPI_FLASHCMDCTRL_CMDOPCODE_SHIFT 24 /**< Shift value for QSPI_CMDOPCODE */ +#define _QSPI_FLASHCMDCTRL_CMDOPCODE_MASK 0xFF000000UL /**< Bit mask for QSPI_CMDOPCODE */ +#define _QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ +#define QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT (_QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ + +/* Bit fields for QSPI FLASHCMDADDR */ +#define _QSPI_FLASHCMDADDR_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHCMDADDR */ +#define _QSPI_FLASHCMDADDR_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHCMDADDR */ +#define _QSPI_FLASHCMDADDR_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */ +#define _QSPI_FLASHCMDADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */ +#define _QSPI_FLASHCMDADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDADDR */ +#define QSPI_FLASHCMDADDR_ADDR_DEFAULT (_QSPI_FLASHCMDADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHCMDADDR */ + +/* Bit fields for QSPI FLASHRDDATALOWER */ +#define _QSPI_FLASHRDDATALOWER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHRDDATALOWER */ +#define _QSPI_FLASHRDDATALOWER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHRDDATALOWER */ +#define _QSPI_FLASHRDDATALOWER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */ +#define _QSPI_FLASHRDDATALOWER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */ +#define _QSPI_FLASHRDDATALOWER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHRDDATALOWER */ +#define QSPI_FLASHRDDATALOWER_DATA_DEFAULT (_QSPI_FLASHRDDATALOWER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHRDDATALOWER */ + +/* Bit fields for QSPI FLASHRDDATAUPPER */ +#define _QSPI_FLASHRDDATAUPPER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHRDDATAUPPER */ +#define _QSPI_FLASHRDDATAUPPER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHRDDATAUPPER */ +#define _QSPI_FLASHRDDATAUPPER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */ +#define _QSPI_FLASHRDDATAUPPER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */ +#define _QSPI_FLASHRDDATAUPPER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHRDDATAUPPER */ +#define QSPI_FLASHRDDATAUPPER_DATA_DEFAULT (_QSPI_FLASHRDDATAUPPER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHRDDATAUPPER */ + +/* Bit fields for QSPI FLASHWRDATALOWER */ +#define _QSPI_FLASHWRDATALOWER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHWRDATALOWER */ +#define _QSPI_FLASHWRDATALOWER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHWRDATALOWER */ +#define _QSPI_FLASHWRDATALOWER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */ +#define _QSPI_FLASHWRDATALOWER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */ +#define _QSPI_FLASHWRDATALOWER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHWRDATALOWER */ +#define QSPI_FLASHWRDATALOWER_DATA_DEFAULT (_QSPI_FLASHWRDATALOWER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHWRDATALOWER */ + +/* Bit fields for QSPI FLASHWRDATAUPPER */ +#define _QSPI_FLASHWRDATAUPPER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHWRDATAUPPER */ +#define _QSPI_FLASHWRDATAUPPER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHWRDATAUPPER */ +#define _QSPI_FLASHWRDATAUPPER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */ +#define _QSPI_FLASHWRDATAUPPER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */ +#define _QSPI_FLASHWRDATAUPPER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHWRDATAUPPER */ +#define QSPI_FLASHWRDATAUPPER_DATA_DEFAULT (_QSPI_FLASHWRDATAUPPER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHWRDATAUPPER */ + +/* Bit fields for QSPI POLLINGFLASHSTATUS */ +#define _QSPI_POLLINGFLASHSTATUS_RESETVALUE 0x00000000UL /**< Default value for QSPI_POLLINGFLASHSTATUS */ +#define _QSPI_POLLINGFLASHSTATUS_MASK 0x000F01FFUL /**< Mask for QSPI_POLLINGFLASHSTATUS */ +#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_SHIFT 0 /**< Shift value for QSPI_DEVICESTATUS */ +#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_MASK 0xFFUL /**< Bit mask for QSPI_DEVICESTATUS */ +#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ +#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ +#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID (0x1UL << 8) /**< Device Status Valid */ +#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_SHIFT 8 /**< Shift value for QSPI_DEVICESTATUSVALID */ +#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_MASK 0x100UL /**< Bit mask for QSPI_DEVICESTATUSVALID */ +#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ +#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ +#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_SHIFT 16 /**< Shift value for QSPI_DEVICESTATUSNBDUMMY */ +#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_MASK 0xF0000UL /**< Bit mask for QSPI_DEVICESTATUSNBDUMMY */ +#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ +#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ + +/* Bit fields for QSPI PHYCONFIGURATION */ +#define _QSPI_PHYCONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for QSPI_PHYCONFIGURATION */ +#define _QSPI_PHYCONFIGURATION_MASK 0x807F007FUL /**< Mask for QSPI_PHYCONFIGURATION */ +#define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_SHIFT 0 /**< Shift value for QSPI_PHYCONFIGRXDLLDELAY */ +#define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_MASK 0x7FUL /**< Bit mask for QSPI_PHYCONFIGRXDLLDELAY */ +#define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYCONFIGURATION */ +#define QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT (_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_PHYCONFIGURATION */ +#define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_SHIFT 16 /**< Shift value for QSPI_PHYCONFIGTXDLLDELAY */ +#define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_MASK 0x7F0000UL /**< Bit mask for QSPI_PHYCONFIGTXDLLDELAY */ +#define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYCONFIGURATION */ +#define QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT (_QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_PHYCONFIGURATION */ +#define QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC (0x1UL << 31) /**< PHY Config Resync */ +#define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_SHIFT 31 /**< Shift value for QSPI_PHYCONFIGRESYNC */ +#define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_MASK 0x80000000UL /**< Bit mask for QSPI_PHYCONFIGRESYNC */ +#define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYCONFIGURATION */ +#define QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT (_QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT << 31) /**< Shifted mode DEFAULT for QSPI_PHYCONFIGURATION */ + +/* Bit fields for QSPI OPCODEEXTLOWER */ +#define _QSPI_OPCODEEXTLOWER_RESETVALUE 0x13EDFA00UL /**< Default value for QSPI_OPCODEEXTLOWER */ +#define _QSPI_OPCODEEXTLOWER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_OPCODEEXTLOWER */ +#define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_SHIFT 0 /**< Shift value for QSPI_EXTSTIGOPCODE */ +#define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_MASK 0xFFUL /**< Bit mask for QSPI_EXTSTIGOPCODE */ +#define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */ +#define QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */ +#define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_SHIFT 8 /**< Shift value for QSPI_EXTPOLLOPCODE */ +#define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_MASK 0xFF00UL /**< Bit mask for QSPI_EXTPOLLOPCODE */ +#define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT 0x000000FAUL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */ +#define QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */ +#define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_SHIFT 16 /**< Shift value for QSPI_EXTWRITEOPCODE */ +#define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_MASK 0xFF0000UL /**< Bit mask for QSPI_EXTWRITEOPCODE */ +#define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT 0x000000EDUL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */ +#define QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */ +#define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_SHIFT 24 /**< Shift value for QSPI_EXTREADOPCODE */ +#define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_MASK 0xFF000000UL /**< Bit mask for QSPI_EXTREADOPCODE */ +#define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT 0x00000013UL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */ +#define QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */ + +/* Bit fields for QSPI OPCODEEXTUPPER */ +#define _QSPI_OPCODEEXTUPPER_RESETVALUE 0x06F90000UL /**< Default value for QSPI_OPCODEEXTUPPER */ +#define _QSPI_OPCODEEXTUPPER_MASK 0xFFFF0000UL /**< Mask for QSPI_OPCODEEXTUPPER */ +#define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_SHIFT 16 /**< Shift value for QSPI_EXTWELOPCODE */ +#define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_MASK 0xFF0000UL /**< Bit mask for QSPI_EXTWELOPCODE */ +#define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT 0x000000F9UL /**< Mode DEFAULT for QSPI_OPCODEEXTUPPER */ +#define QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT (_QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTUPPER */ +#define _QSPI_OPCODEEXTUPPER_WELOPCODE_SHIFT 24 /**< Shift value for QSPI_WELOPCODE */ +#define _QSPI_OPCODEEXTUPPER_WELOPCODE_MASK 0xFF000000UL /**< Bit mask for QSPI_WELOPCODE */ +#define _QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT 0x00000006UL /**< Mode DEFAULT for QSPI_OPCODEEXTUPPER */ +#define QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT (_QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTUPPER */ + +/* Bit fields for QSPI MODULEID */ +#define _QSPI_MODULEID_RESETVALUE 0x00000200UL /**< Default value for QSPI_MODULEID */ +#define _QSPI_MODULEID_MASK 0xFFFFFF03UL /**< Mask for QSPI_MODULEID */ +#define _QSPI_MODULEID_CONF_SHIFT 0 /**< Shift value for QSPI_CONF */ +#define _QSPI_MODULEID_CONF_MASK 0x3UL /**< Bit mask for QSPI_CONF */ +#define _QSPI_MODULEID_CONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODULEID */ +#define QSPI_MODULEID_CONF_DEFAULT (_QSPI_MODULEID_CONF_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_MODULEID */ +#define _QSPI_MODULEID_MODULEID_SHIFT 8 /**< Shift value for QSPI_MODULEID */ +#define _QSPI_MODULEID_MODULEID_MASK 0xFFFF00UL /**< Bit mask for QSPI_MODULEID */ +#define _QSPI_MODULEID_MODULEID_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_MODULEID */ +#define QSPI_MODULEID_MODULEID_DEFAULT (_QSPI_MODULEID_MODULEID_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_MODULEID */ +#define _QSPI_MODULEID_FIXPATCH_SHIFT 24 /**< Shift value for QSPI_FIXPATCH */ +#define _QSPI_MODULEID_FIXPATCH_MASK 0xFF000000UL /**< Bit mask for QSPI_FIXPATCH */ +#define _QSPI_MODULEID_FIXPATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODULEID */ +#define QSPI_MODULEID_FIXPATCH_DEFAULT (_QSPI_MODULEID_FIXPATCH_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_MODULEID */ + +/* Bit fields for QSPI ROUTEPEN */ +#define _QSPI_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for QSPI_ROUTEPEN */ +#define _QSPI_ROUTEPEN_MASK 0x00007FE7UL /**< Mask for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_SCLKPEN (0x1UL << 0) /**< SCLK Pin Enable */ +#define _QSPI_ROUTEPEN_SCLKPEN_SHIFT 0 /**< Shift value for QSPI_SCLKPEN */ +#define _QSPI_ROUTEPEN_SCLKPEN_MASK 0x1UL /**< Bit mask for QSPI_SCLKPEN */ +#define _QSPI_ROUTEPEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_SCLKPEN_DEFAULT (_QSPI_ROUTEPEN_SCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_CS0PEN (0x1UL << 1) /**< CS0 Pin Enable */ +#define _QSPI_ROUTEPEN_CS0PEN_SHIFT 1 /**< Shift value for QSPI_CS0PEN */ +#define _QSPI_ROUTEPEN_CS0PEN_MASK 0x2UL /**< Bit mask for QSPI_CS0PEN */ +#define _QSPI_ROUTEPEN_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_CS0PEN_DEFAULT (_QSPI_ROUTEPEN_CS0PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_CS1PEN (0x1UL << 2) /**< CS1 Pin Enable */ +#define _QSPI_ROUTEPEN_CS1PEN_SHIFT 2 /**< Shift value for QSPI_CS1PEN */ +#define _QSPI_ROUTEPEN_CS1PEN_MASK 0x4UL /**< Bit mask for QSPI_CS1PEN */ +#define _QSPI_ROUTEPEN_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_CS1PEN_DEFAULT (_QSPI_ROUTEPEN_CS1PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ0PEN (0x1UL << 5) /**< DQ0 Pin Enable */ +#define _QSPI_ROUTEPEN_DQ0PEN_SHIFT 5 /**< Shift value for QSPI_DQ0PEN */ +#define _QSPI_ROUTEPEN_DQ0PEN_MASK 0x20UL /**< Bit mask for QSPI_DQ0PEN */ +#define _QSPI_ROUTEPEN_DQ0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ0PEN_DEFAULT (_QSPI_ROUTEPEN_DQ0PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ1PEN (0x1UL << 6) /**< DQ1 Pin Enable */ +#define _QSPI_ROUTEPEN_DQ1PEN_SHIFT 6 /**< Shift value for QSPI_DQ1PEN */ +#define _QSPI_ROUTEPEN_DQ1PEN_MASK 0x40UL /**< Bit mask for QSPI_DQ1PEN */ +#define _QSPI_ROUTEPEN_DQ1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ1PEN_DEFAULT (_QSPI_ROUTEPEN_DQ1PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ2PEN (0x1UL << 7) /**< DQ2 Pin Enable */ +#define _QSPI_ROUTEPEN_DQ2PEN_SHIFT 7 /**< Shift value for QSPI_DQ2PEN */ +#define _QSPI_ROUTEPEN_DQ2PEN_MASK 0x80UL /**< Bit mask for QSPI_DQ2PEN */ +#define _QSPI_ROUTEPEN_DQ2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ2PEN_DEFAULT (_QSPI_ROUTEPEN_DQ2PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ3PEN (0x1UL << 8) /**< DQ3 Pin Enable */ +#define _QSPI_ROUTEPEN_DQ3PEN_SHIFT 8 /**< Shift value for QSPI_DQ3PEN */ +#define _QSPI_ROUTEPEN_DQ3PEN_MASK 0x100UL /**< Bit mask for QSPI_DQ3PEN */ +#define _QSPI_ROUTEPEN_DQ3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ3PEN_DEFAULT (_QSPI_ROUTEPEN_DQ3PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ4PEN (0x1UL << 9) /**< DQ4 Pin Enable */ +#define _QSPI_ROUTEPEN_DQ4PEN_SHIFT 9 /**< Shift value for QSPI_DQ4PEN */ +#define _QSPI_ROUTEPEN_DQ4PEN_MASK 0x200UL /**< Bit mask for QSPI_DQ4PEN */ +#define _QSPI_ROUTEPEN_DQ4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ4PEN_DEFAULT (_QSPI_ROUTEPEN_DQ4PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ5PEN (0x1UL << 10) /**< DQ5 Pin Enable */ +#define _QSPI_ROUTEPEN_DQ5PEN_SHIFT 10 /**< Shift value for QSPI_DQ5PEN */ +#define _QSPI_ROUTEPEN_DQ5PEN_MASK 0x400UL /**< Bit mask for QSPI_DQ5PEN */ +#define _QSPI_ROUTEPEN_DQ5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ5PEN_DEFAULT (_QSPI_ROUTEPEN_DQ5PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ6PEN (0x1UL << 11) /**< DQ6 Pin Enable */ +#define _QSPI_ROUTEPEN_DQ6PEN_SHIFT 11 /**< Shift value for QSPI_DQ6PEN */ +#define _QSPI_ROUTEPEN_DQ6PEN_MASK 0x800UL /**< Bit mask for QSPI_DQ6PEN */ +#define _QSPI_ROUTEPEN_DQ6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ6PEN_DEFAULT (_QSPI_ROUTEPEN_DQ6PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ7PEN (0x1UL << 12) /**< DQ7 Pin Enable */ +#define _QSPI_ROUTEPEN_DQ7PEN_SHIFT 12 /**< Shift value for QSPI_DQ7PEN */ +#define _QSPI_ROUTEPEN_DQ7PEN_MASK 0x1000UL /**< Bit mask for QSPI_DQ7PEN */ +#define _QSPI_ROUTEPEN_DQ7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQ7PEN_DEFAULT (_QSPI_ROUTEPEN_DQ7PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQSPEN (0x1UL << 13) /**< DQS Pin Enable */ +#define _QSPI_ROUTEPEN_DQSPEN_SHIFT 13 /**< Shift value for QSPI_DQSPEN */ +#define _QSPI_ROUTEPEN_DQSPEN_MASK 0x2000UL /**< Bit mask for QSPI_DQSPEN */ +#define _QSPI_ROUTEPEN_DQSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_DQSPEN_DEFAULT (_QSPI_ROUTEPEN_DQSPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_SCLKINPEN (0x1UL << 14) /**< SCLKIN Pin Enable */ +#define _QSPI_ROUTEPEN_SCLKINPEN_SHIFT 14 /**< Shift value for QSPI_SCLKINPEN */ +#define _QSPI_ROUTEPEN_SCLKINPEN_MASK 0x4000UL /**< Bit mask for QSPI_SCLKINPEN */ +#define _QSPI_ROUTEPEN_SCLKINPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ +#define QSPI_ROUTEPEN_SCLKINPEN_DEFAULT (_QSPI_ROUTEPEN_SCLKINPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ + +/* Bit fields for QSPI ROUTELOC0 */ +#define _QSPI_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for QSPI_ROUTELOC0 */ +#define _QSPI_ROUTELOC0_MASK 0x00000003UL /**< Mask for QSPI_ROUTELOC0 */ +#define _QSPI_ROUTELOC0_QSPILOC_SHIFT 0 /**< Shift value for QSPI_QSPILOC */ +#define _QSPI_ROUTELOC0_QSPILOC_MASK 0x3UL /**< Bit mask for QSPI_QSPILOC */ +#define _QSPI_ROUTELOC0_QSPILOC_LOC0 0x00000000UL /**< Mode LOC0 for QSPI_ROUTELOC0 */ +#define _QSPI_ROUTELOC0_QSPILOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTELOC0 */ +#define _QSPI_ROUTELOC0_QSPILOC_LOC1 0x00000001UL /**< Mode LOC1 for QSPI_ROUTELOC0 */ +#define _QSPI_ROUTELOC0_QSPILOC_LOC2 0x00000002UL /**< Mode LOC2 for QSPI_ROUTELOC0 */ +#define QSPI_ROUTELOC0_QSPILOC_LOC0 (_QSPI_ROUTELOC0_QSPILOC_LOC0 << 0) /**< Shifted mode LOC0 for QSPI_ROUTELOC0 */ +#define QSPI_ROUTELOC0_QSPILOC_DEFAULT (_QSPI_ROUTELOC0_QSPILOC_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_ROUTELOC0 */ +#define QSPI_ROUTELOC0_QSPILOC_LOC1 (_QSPI_ROUTELOC0_QSPILOC_LOC1 << 0) /**< Shifted mode LOC1 for QSPI_ROUTELOC0 */ +#define QSPI_ROUTELOC0_QSPILOC_LOC2 (_QSPI_ROUTELOC0_QSPILOC_LOC2 << 0) /**< Shifted mode LOC2 for QSPI_ROUTELOC0 */ + +/** @} */ +/** @} End of group EFM32GG11B_QSPI */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rmu.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rmu.h new file mode 100644 index 0000000000000..134fbedfb32bd --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rmu.h @@ -0,0 +1,212 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_RMU register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_RMU RMU + * @{ + * @brief EFM32GG11B_RMU Register Declaration + ******************************************************************************/ +/** RMU Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t RSTCAUSE; /**< Reset Cause Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t RST; /**< Reset Control Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ +} RMU_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_RMU + * @{ + * @defgroup EFM32GG11B_RMU_BitFields RMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for RMU CTRL */ +#define _RMU_CTRL_RESETVALUE 0x00004204UL /**< Default value for RMU_CTRL */ +#define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */ +#define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */ +#define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */ +#define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */ +#define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */ +#define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */ +#define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */ +#define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */ +#define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */ +#define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */ +#define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */ + +/* Bit fields for RMU RSTCAUSE */ +#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_MASK 0x00011F1DUL /**< Mask for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power on Reset */ +#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */ +#define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */ +#define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */ +#define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */ +#define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */ +#define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */ +#define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */ +#define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */ +#define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */ +#define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */ +#define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */ +#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */ +#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */ +#define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUMODERST (0x1UL << 12) /**< Backup Mode Reset */ +#define _RMU_RSTCAUSE_BUMODERST_SHIFT 12 /**< Shift value for RMU_BUMODERST */ +#define _RMU_RSTCAUSE_BUMODERST_MASK 0x1000UL /**< Bit mask for RMU_BUMODERST */ +#define _RMU_RSTCAUSE_BUMODERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUMODERST_DEFAULT (_RMU_RSTCAUSE_BUMODERST_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */ +#define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ + +/* Bit fields for RMU CMD */ +#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */ +#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */ +#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */ +#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */ +#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */ + +/* Bit fields for RMU RST */ +#define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */ +#define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */ + +/* Bit fields for RMU LOCK */ +#define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */ +#define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */ +#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */ +#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */ + +/** @} */ +/** @} End of group EFM32GG11B_RMU */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_romtable.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_romtable.h new file mode 100644 index 0000000000000..49056791e189a --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_romtable.h @@ -0,0 +1,88 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_ROMTABLE register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_ROMTABLE ROM Table, Chip Revision Information + * @{ + * @brief Chip Information, Revision numbers + ******************************************************************************/ +/** ROMTABLE Register Declaration */ +typedef struct { + __IM uint32_t PID4; /**< JEP_106_BANK */ + __IM uint32_t PID5; /**< Unused */ + __IM uint32_t PID6; /**< Unused */ + __IM uint32_t PID7; /**< Unused */ + __IM uint32_t PID0; /**< Chip family LSB, chip major revision */ + __IM uint32_t PID1; /**< JEP_106_NO, Chip family MSB */ + __IM uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */ + __IM uint32_t PID3; /**< Chip minor rev LSB */ + __IM uint32_t CID0; /**< Unused */ +} ROMTABLE_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_ROMTABLE + * @{ + * @defgroup EFM32GG11B_ROMTABLE_BitFields ROM Table Bit Field definitions + * @{ + ******************************************************************************/ +/* Bit fields for EFM32GG11B_ROMTABLE */ +#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */ +#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */ +#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */ +#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */ +#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */ + +/** @} */ +/** @} End of group EFM32GG11B_ROMTABLE */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtc.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtc.h new file mode 100644 index 0000000000000..fdf2c78f8e5f3 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtc.h @@ -0,0 +1,168 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_RTC register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_RTC RTC + * @{ + * @brief EFM32GG11B_RTC Register Declaration + ******************************************************************************/ +/** RTC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED0[2U]; /**< Reserved registers */ + RTC_COMP_TypeDef COMP[6U]; /**< Compare channels */ +} RTC_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_RTC + * @{ + * @defgroup EFM32GG11B_RTC_BitFields RTC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for RTC CTRL */ +#define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */ +#define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */ +#define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */ +#define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */ +#define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */ +#define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */ +#define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */ +#define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */ +#define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */ +#define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */ +#define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ +#define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */ +#define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */ +#define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */ +#define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */ + +/* Bit fields for RTC CNT */ +#define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */ +#define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */ +#define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */ +#define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */ +#define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */ +#define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */ + +/* Bit fields for RTC IF */ +#define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */ +#define _RTC_IF_MASK 0x0000007FUL /**< Mask for RTC_IF */ +#define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */ +#define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ +#define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ +#define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */ +#define _RTC_IF_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ +#define _RTC_IF_COMP_MASK 0x7EUL /**< Bit mask for RTC_COMP */ +#define _RTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ +#define RTC_IF_COMP_DEFAULT (_RTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */ + +/* Bit fields for RTC IFS */ +#define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */ +#define _RTC_IFS_MASK 0x0000007FUL /**< Mask for RTC_IFS */ +#define RTC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */ +#define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ +#define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ +#define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */ +#define _RTC_IFS_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ +#define _RTC_IFS_COMP_MASK 0x7EUL /**< Bit mask for RTC_COMP */ +#define _RTC_IFS_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ +#define RTC_IFS_COMP_DEFAULT (_RTC_IFS_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */ + +/* Bit fields for RTC IFC */ +#define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */ +#define _RTC_IFC_MASK 0x0000007FUL /**< Mask for RTC_IFC */ +#define RTC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */ +#define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ +#define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ +#define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */ +#define _RTC_IFC_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ +#define _RTC_IFC_COMP_MASK 0x7EUL /**< Bit mask for RTC_COMP */ +#define _RTC_IFC_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ +#define RTC_IFC_COMP_DEFAULT (_RTC_IFC_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */ + +/* Bit fields for RTC IEN */ +#define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */ +#define _RTC_IEN_MASK 0x0000007FUL /**< Mask for RTC_IEN */ +#define RTC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */ +#define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ +#define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ +#define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */ +#define _RTC_IEN_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ +#define _RTC_IEN_COMP_MASK 0x7EUL /**< Bit mask for RTC_COMP */ +#define _RTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ +#define RTC_IEN_COMP_DEFAULT (_RTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */ + +/* Bit fields for RTC COMP_COMP */ +#define _RTC_COMP_COMP_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP_COMP */ +#define _RTC_COMP_COMP_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP_COMP */ +#define _RTC_COMP_COMP_COMP_SHIFT 0 /**< Shift value for RTC_COMP */ +#define _RTC_COMP_COMP_COMP_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP */ +#define _RTC_COMP_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP_COMP */ +#define RTC_COMP_COMP_COMP_DEFAULT (_RTC_COMP_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP_COMP */ + +/** @} */ +/** @} End of group EFM32GG11B_RTC */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtc_comp.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtc_comp.h new file mode 100644 index 0000000000000..b2580e34bdf1c --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtc_comp.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_RTC_COMP register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief RTC_COMP RTC COMP Register + * @ingroup EFM32GG11B_RTC + ******************************************************************************/ +typedef struct { + __IOM uint32_t COMP; /**< Compare Value Register X */ +} RTC_COMP_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc.h new file mode 100644 index 0000000000000..d4ee18c27e295 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc.h @@ -0,0 +1,745 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_RTCC register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_RTCC RTCC + * @{ + * @brief EFM32GG11B_RTCC Register Declaration + ******************************************************************************/ +/** RTCC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */ + __IOM uint32_t TIME; /**< Time of Day Register */ + __IOM uint32_t DATE; /**< Date Register */ + __IM uint32_t IF; /**< RTCC Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t POWERDOWN; /**< Retention RAM Power-down Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ + + RTCC_CC_TypeDef CC[3U]; /**< Capture/Compare Channel */ + + uint32_t RESERVED0[37U]; /**< Reserved registers */ + RTCC_RET_TypeDef RET[32U]; /**< RetentionReg */ +} RTCC_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_RTCC + * @{ + * @defgroup EFM32GG11B_RTCC_BitFields RTCC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for RTCC CTRL */ +#define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */ +#define _RTCC_CTRL_MASK 0x0003DF35UL /**< Mask for RTCC_CTRL */ +#define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */ +#define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */ +#define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */ +#define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */ +#define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */ +#define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */ +#define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 Top Value Enable */ +#define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */ +#define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */ +#define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 Top Value Enable */ +#define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */ +#define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */ +#define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */ +#define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */ +#define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter Prescaler Mode */ +#define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */ +#define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */ +#define RTCC_CTRL_BUMODETSEN (0x1UL << 14) /**< Backup Mode Timestamp Enable */ +#define _RTCC_CTRL_BUMODETSEN_SHIFT 14 /**< Shift value for RTCC_BUMODETSEN */ +#define _RTCC_CTRL_BUMODETSEN_MASK 0x4000UL /**< Bit mask for RTCC_BUMODETSEN */ +#define _RTCC_CTRL_BUMODETSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_BUMODETSEN_DEFAULT (_RTCC_CTRL_BUMODETSEN_DEFAULT << 14) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator Failure Detection Enable */ +#define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */ +#define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */ +#define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main Counter Mode */ +#define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */ +#define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */ +#define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */ +#define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */ +#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap Year Correction Disabled */ +#define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */ +#define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */ +#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */ + +/* Bit fields for RTCC PRECNT */ +#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ +#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ +#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ + +/* Bit fields for RTCC CNT */ +#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ +#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ +#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ +#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ + +/* Bit fields for RTCC COMBCNT */ +#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ + +/* Bit fields for RTCC TIME */ +#define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */ +#define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */ +#define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */ +#define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */ +#define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */ +#define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */ +#define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */ +#define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */ +#define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */ +#define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */ +#define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */ +#define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */ +#define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */ +#define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */ +#define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */ + +/* Bit fields for RTCC DATE */ +#define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */ +#define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */ +#define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */ +#define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */ +#define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */ +#define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */ +#define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */ +#define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */ +#define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */ +#define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */ +#define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */ +#define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */ +#define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */ +#define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */ +#define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */ +#define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */ +#define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */ +#define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */ + +/* Bit fields for RTCC IF */ +#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ +#define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */ +#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */ +#define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */ +#define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */ +#define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator Failure Interrupt Flag */ +#define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main Counter Tick */ +#define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute Tick */ +#define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour Tick */ +#define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day Tick */ +#define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of Week Overflow */ +#define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month Tick */ +#define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */ + +/* Bit fields for RTCC IFS */ +#define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */ +#define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */ +#define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */ +#define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */ +#define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */ +#define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */ +#define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */ +#define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */ +#define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */ +#define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */ +#define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */ +#define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */ +#define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */ + +/* Bit fields for RTCC IFC */ +#define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */ +#define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */ +#define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */ +#define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */ +#define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */ +#define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */ +#define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */ +#define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */ +#define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */ +#define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */ +#define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */ +#define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */ +#define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */ + +/* Bit fields for RTCC IEN */ +#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ +#define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */ +#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */ +#define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */ +#define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */ +#define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */ +#define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */ +#define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */ +#define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */ +#define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */ +#define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */ +#define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */ +#define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */ + +/* Bit fields for RTCC STATUS */ +#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ +#define _RTCC_STATUS_MASK 0x00000001UL /**< Mask for RTCC_STATUS */ +#define RTCC_STATUS_BUMODETS (0x1UL << 0) /**< Timestamp for Backup Mode Entry Stored */ +#define _RTCC_STATUS_BUMODETS_SHIFT 0 /**< Shift value for RTCC_BUMODETS */ +#define _RTCC_STATUS_BUMODETS_MASK 0x1UL /**< Bit mask for RTCC_BUMODETS */ +#define _RTCC_STATUS_BUMODETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_STATUS */ +#define RTCC_STATUS_BUMODETS_DEFAULT (_RTCC_STATUS_BUMODETS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_STATUS */ + +/* Bit fields for RTCC CMD */ +#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ +#define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */ +#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS Register */ +#define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */ +#define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */ +#define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ + +/* Bit fields for RTCC SYNCBUSY */ +#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ +#define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */ +#define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */ +#define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */ +#define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ + +/* Bit fields for RTCC POWERDOWN */ +#define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */ +#define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */ +#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM Power-down */ +#define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */ +#define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */ +#define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */ +#define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */ + +/* Bit fields for RTCC LOCK */ +#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ +#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ + +/* Bit fields for RTCC EM4WUEN */ +#define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */ +#define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */ +#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */ +#define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */ +#define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */ +#define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */ +#define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */ + +/* Bit fields for RTCC CC_CTRL */ +#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MASK 0x0003FFFFUL /**< Mask for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */ +#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */ +#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */ +#define _RTCC_CC_CTRL_PRSSEL_MASK 0x7C0UL /**< Bit mask for CC_PRSSEL */ +#define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH12 (_RTCC_CC_CTRL_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH13 (_RTCC_CC_CTRL_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH14 (_RTCC_CC_CTRL_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH15 (_RTCC_CC_CTRL_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH16 (_RTCC_CC_CTRL_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH17 (_RTCC_CC_CTRL_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH18 (_RTCC_CC_CTRL_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH19 (_RTCC_CC_CTRL_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH20 (_RTCC_CC_CTRL_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH21 (_RTCC_CC_CTRL_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH22 (_RTCC_CC_CTRL_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH23 (_RTCC_CC_CTRL_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture Compare Channel Comparison Base */ +#define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */ +#define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */ +#define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare Selection */ +#define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */ +#define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */ +#define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */ + +/* Bit fields for RTCC CC_CCV */ +#define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */ +#define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */ +#define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */ +#define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */ +#define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */ +#define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */ + +/* Bit fields for RTCC CC_TIME */ +#define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */ +#define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */ +#define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */ +#define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */ +#define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */ +#define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */ +#define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */ +#define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */ +#define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */ +#define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */ +#define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */ +#define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */ +#define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ + +/* Bit fields for RTCC CC_DATE */ +#define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */ +#define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */ +#define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */ +#define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */ +#define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */ +#define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */ +#define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */ +#define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */ +#define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */ +#define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ + +/* Bit fields for RTCC RET_REG */ +#define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */ +#define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */ +#define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */ +#define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */ +#define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */ +#define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */ + +/** @} */ +/** @} End of group EFM32GG11B_RTCC */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc_cc.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc_cc.h new file mode 100644 index 0000000000000..b58de6d879672 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc_cc.h @@ -0,0 +1,61 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_RTCC_CC register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief RTCC_CC RTCC CC Register + * @ingroup EFM32GG11B_RTCC + ******************************************************************************/ +typedef struct { + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t CCV; /**< Capture/Compare Value Register */ + __IOM uint32_t TIME; /**< Capture/Compare Time Register */ + __IOM uint32_t DATE; /**< Capture/Compare Date Register */ +} RTCC_CC_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc_ret.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc_ret.h new file mode 100644 index 0000000000000..3c381ab3eaffe --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_rtcc_ret.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_RTCC_RET register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief RTCC_RET RTCC RET Register + * @ingroup EFM32GG11B_RTCC + ******************************************************************************/ +typedef struct { + __IOM uint32_t REG; /**< Retention Register */ +} RTCC_RET_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_sdio.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_sdio.h new file mode 100644 index 0000000000000..43fd9a787b0be --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_sdio.h @@ -0,0 +1,1925 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_SDIO register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_SDIO SDIO + * @{ + * @brief EFM32GG11B_SDIO Register Declaration + ******************************************************************************/ +/** SDIO Register Declaration */ +typedef struct { + __IOM uint32_t SDMASYSADDR; /**< SDMA System Address Register */ + __IOM uint32_t BLKSIZE; /**< Block Size and Block Count Register */ + __IOM uint32_t CMDARG1; /**< SD Command Argument Register */ + __IOM uint32_t TFRMODE; /**< Transfer Mode and Command Register */ + __IM uint32_t RESP0; /**< Response0 and Response1 Register */ + __IM uint32_t RESP2; /**< Response2 and Response3 Register */ + __IM uint32_t RESP4; /**< Response4 and Response5 Register */ + __IM uint32_t RESP6; /**< Response6 and Response7 Register */ + __IOM uint32_t BUFDATPORT; /**< Buffer Data Register */ + __IM uint32_t PRSSTAT; /**< Present State Register */ + __IOM uint32_t HOSTCTRL1; /**< Host Control1, Power, Block Gap and Wakeup-up Control Register */ + __IOM uint32_t CLOCKCTRL; /**< Clock Control, Timeout Control and Software Register */ + __IOM uint32_t IFCR; /**< Normal and Error Interrupt Status Register */ + __IOM uint32_t IFENC; /**< Normal and Error Interrupt Status Enable Register */ + __IOM uint32_t IEN; /**< Normal and Error Interrupt Signal Enable Register */ + __IOM uint32_t AC12ERRSTAT; /**< AUTO CMD12 Error Status and Host Control2 Register */ + __IM uint32_t CAPAB0; /**< Capabilities Register to Hold Bits 31~0 */ + __IM uint32_t CAPAB2; /**< Capabilities Register to Hold Bits 63~32 */ + __IM uint32_t MAXCURCAPAB; /**< Maximum Current Capabilities Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t FEVTERRSTAT; /**< Force Event Register for Auto CMD Error Status */ + __IM uint32_t ADMAES; /**< ADMA Error Status Register */ + __IOM uint32_t ADSADDR; /**< ADMA System Address Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IM uint32_t PRSTVAL0; /**< Preset Value for Initialization and Default Speed Mode */ + __IM uint32_t PRSTVAL2; /**< Preset Value for High Speed and SDR12 Modes */ + __IM uint32_t PRSTVAL4; /**< Preset Value for SDR25 and SDR50 Modes */ + __IM uint32_t PRSTVAL6; /**< Preset Value for SDR104 and DDR50 Modes */ + __IOM uint32_t BOOTTOCTRL; /**< Boot Timeout Control Register */ + uint32_t RESERVED2[34U]; /**< Reserved for future use **/ + __IM uint32_t SLOTINTSTAT; /**< Slot Interrupt Status Register */ + + uint32_t RESERVED3[448U]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Core Control Signals */ + __IOM uint32_t CFG0; /**< Core Configuration 0 */ + __IOM uint32_t CFG1; /**< Core Configuration 1 */ + __IOM uint32_t CFGPRESETVAL0; /**< Core Configuration Preset Value 0 */ + __IOM uint32_t CFGPRESETVAL1; /**< Core Configuration Preset Value 1 */ + __IOM uint32_t CFGPRESETVAL2; /**< Core Configuration Preset Value 2 */ + __IOM uint32_t CFGPRESETVAL3; /**< Core Configuration Preset Value 3 */ + __IOM uint32_t ROUTELOC0; /**< I/O LOCATION Register */ + __IOM uint32_t ROUTELOC1; /**< I/O LOCATION Register */ + __IOM uint32_t ROUTEPEN; /**< I/O LOCATION Enable Register */ +} SDIO_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_SDIO + * @{ + * @defgroup EFM32GG11B_SDIO_BitFields SDIO Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SDIO SDMASYSADDR */ +#define _SDIO_SDMASYSADDR_RESETVALUE 0x00000000UL /**< Default value for SDIO_SDMASYSADDR */ +#define _SDIO_SDMASYSADDR_MASK 0xFFFFFFFFUL /**< Mask for SDIO_SDMASYSADDR */ +#define _SDIO_SDMASYSADDR_SDMASYSADDRARG_SHIFT 0 /**< Shift value for SDIO_SDMASYSADDRARG */ +#define _SDIO_SDMASYSADDR_SDMASYSADDRARG_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_SDMASYSADDRARG */ +#define _SDIO_SDMASYSADDR_SDMASYSADDRARG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_SDMASYSADDR */ +#define SDIO_SDMASYSADDR_SDMASYSADDRARG_DEFAULT (_SDIO_SDMASYSADDR_SDMASYSADDRARG_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_SDMASYSADDR */ + +/* Bit fields for SDIO BLKSIZE */ +#define _SDIO_BLKSIZE_RESETVALUE 0x00000000UL /**< Default value for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_MASK 0xFFFF7FFFUL /**< Mask for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_TFRBLKSIZE_SHIFT 0 /**< Shift value for SDIO_TFRBLKSIZE */ +#define _SDIO_BLKSIZE_TFRBLKSIZE_MASK 0xFFFUL /**< Bit mask for SDIO_TFRBLKSIZE */ +#define _SDIO_BLKSIZE_TFRBLKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_TFRBLKSIZE_NOXFER 0x00000000UL /**< Mode NOXFER for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_TFRBLKSIZE_DEFAULT (_SDIO_BLKSIZE_TFRBLKSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_TFRBLKSIZE_NOXFER (_SDIO_BLKSIZE_TFRBLKSIZE_NOXFER << 0) /**< Shifted mode NOXFER for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SHIFT 12 /**< Shift value for SDIO_HSTSDMABUFSIZE */ +#define _SDIO_BLKSIZE_HSTSDMABUFSIZE_MASK 0x7000UL /**< Bit mask for SDIO_HSTSDMABUFSIZE */ +#define _SDIO_BLKSIZE_HSTSDMABUFSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE4 0x00000000UL /**< Mode SIZE4 for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE8 0x00000001UL /**< Mode SIZE8 for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE16 0x00000002UL /**< Mode SIZE16 for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE32 0x00000003UL /**< Mode SIZE32 for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE64 0x00000004UL /**< Mode SIZE64 for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE128 0x00000005UL /**< Mode SIZE128 for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE256 0x00000006UL /**< Mode SIZE256 for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE512 0x00000007UL /**< Mode SIZE512 for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_HSTSDMABUFSIZE_DEFAULT (_SDIO_BLKSIZE_HSTSDMABUFSIZE_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE4 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE4 << 12) /**< Shifted mode SIZE4 for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE8 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE8 << 12) /**< Shifted mode SIZE8 for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE16 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE16 << 12) /**< Shifted mode SIZE16 for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE32 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE32 << 12) /**< Shifted mode SIZE32 for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE64 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE64 << 12) /**< Shifted mode SIZE64 for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE128 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE128 << 12) /**< Shifted mode SIZE128 for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE256 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE256 << 12) /**< Shifted mode SIZE256 for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE512 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE512 << 12) /**< Shifted mode SIZE512 for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_SHIFT 16 /**< Shift value for SDIO_BLKSCNTFORCURRTFR */ +#define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_MASK 0xFFFF0000UL /**< Bit mask for SDIO_BLKSCNTFORCURRTFR */ +#define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BLKSIZE */ +#define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_STOPCNT 0x00000000UL /**< Mode STOPCNT for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_BLKSCNTFORCURRTFR_DEFAULT (_SDIO_BLKSIZE_BLKSCNTFORCURRTFR_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_BLKSIZE */ +#define SDIO_BLKSIZE_BLKSCNTFORCURRTFR_STOPCNT (_SDIO_BLKSIZE_BLKSCNTFORCURRTFR_STOPCNT << 16) /**< Shifted mode STOPCNT for SDIO_BLKSIZE */ + +/* Bit fields for SDIO CMDARG1 */ +#define _SDIO_CMDARG1_RESETVALUE 0x00000000UL /**< Default value for SDIO_CMDARG1 */ +#define _SDIO_CMDARG1_MASK 0xFFFFFFFFUL /**< Mask for SDIO_CMDARG1 */ +#define _SDIO_CMDARG1_CMDARG1_SHIFT 0 /**< Shift value for SDIO_CMDARG1 */ +#define _SDIO_CMDARG1_CMDARG1_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDARG1 */ +#define _SDIO_CMDARG1_CMDARG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CMDARG1 */ +#define SDIO_CMDARG1_CMDARG1_DEFAULT (_SDIO_CMDARG1_CMDARG1_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CMDARG1 */ + +/* Bit fields for SDIO TFRMODE */ +#define _SDIO_TFRMODE_RESETVALUE 0x00000000UL /**< Default value for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_MASK 0x3FFB003FUL /**< Mask for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DMAEN (0x1UL << 0) /**< DMA Enable */ +#define _SDIO_TFRMODE_DMAEN_SHIFT 0 /**< Shift value for SDIO_DMAEN */ +#define _SDIO_TFRMODE_DMAEN_MASK 0x1UL /**< Bit mask for SDIO_DMAEN */ +#define _SDIO_TFRMODE_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DMAEN_DEFAULT (_SDIO_TFRMODE_DMAEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DMAEN_DISABLE (_SDIO_TFRMODE_DMAEN_DISABLE << 0) /**< Shifted mode DISABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DMAEN_ENABLE (_SDIO_TFRMODE_DMAEN_ENABLE << 0) /**< Shifted mode ENABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_BLKCNTEN (0x1UL << 1) /**< Block Count Enable */ +#define _SDIO_TFRMODE_BLKCNTEN_SHIFT 1 /**< Shift value for SDIO_BLKCNTEN */ +#define _SDIO_TFRMODE_BLKCNTEN_MASK 0x2UL /**< Bit mask for SDIO_BLKCNTEN */ +#define _SDIO_TFRMODE_BLKCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_BLKCNTEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_BLKCNTEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_BLKCNTEN_DEFAULT (_SDIO_TFRMODE_BLKCNTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_BLKCNTEN_DISABLE (_SDIO_TFRMODE_BLKCNTEN_DISABLE << 1) /**< Shifted mode DISABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_BLKCNTEN_ENABLE (_SDIO_TFRMODE_BLKCNTEN_ENABLE << 1) /**< Shifted mode ENABLE for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_AUTOCMDEN_SHIFT 2 /**< Shift value for SDIO_AUTOCMDEN */ +#define _SDIO_TFRMODE_AUTOCMDEN_MASK 0xCUL /**< Bit mask for SDIO_AUTOCMDEN */ +#define _SDIO_TFRMODE_AUTOCMDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_AUTOCMDEN_ACMDDISABLED 0x00000000UL /**< Mode ACMDDISABLED for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_AUTOCMDEN_ACMD12EN 0x00000001UL /**< Mode ACMD12EN for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_AUTOCMDEN_ACMD23EN 0x00000002UL /**< Mode ACMD23EN for SDIO_TFRMODE */ +#define SDIO_TFRMODE_AUTOCMDEN_DEFAULT (_SDIO_TFRMODE_AUTOCMDEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_AUTOCMDEN_ACMDDISABLED (_SDIO_TFRMODE_AUTOCMDEN_ACMDDISABLED << 2) /**< Shifted mode ACMDDISABLED for SDIO_TFRMODE */ +#define SDIO_TFRMODE_AUTOCMDEN_ACMD12EN (_SDIO_TFRMODE_AUTOCMDEN_ACMD12EN << 2) /**< Shifted mode ACMD12EN for SDIO_TFRMODE */ +#define SDIO_TFRMODE_AUTOCMDEN_ACMD23EN (_SDIO_TFRMODE_AUTOCMDEN_ACMD23EN << 2) /**< Shifted mode ACMD23EN for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DATDIRSEL (0x1UL << 4) /**< Data Transfer Direction Select */ +#define _SDIO_TFRMODE_DATDIRSEL_SHIFT 4 /**< Shift value for SDIO_DATDIRSEL */ +#define _SDIO_TFRMODE_DATDIRSEL_MASK 0x10UL /**< Bit mask for SDIO_DATDIRSEL */ +#define _SDIO_TFRMODE_DATDIRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_DATDIRSEL_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_DATDIRSEL_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DATDIRSEL_DEFAULT (_SDIO_TFRMODE_DATDIRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DATDIRSEL_DISABLE (_SDIO_TFRMODE_DATDIRSEL_DISABLE << 4) /**< Shifted mode DISABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DATDIRSEL_ENABLE (_SDIO_TFRMODE_DATDIRSEL_ENABLE << 4) /**< Shifted mode ENABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_MULTSINGBLKSEL (0x1UL << 5) /**< Multiple or Single Block Data Transfer Selection */ +#define _SDIO_TFRMODE_MULTSINGBLKSEL_SHIFT 5 /**< Shift value for SDIO_MULTSINGBLKSEL */ +#define _SDIO_TFRMODE_MULTSINGBLKSEL_MASK 0x20UL /**< Bit mask for SDIO_MULTSINGBLKSEL */ +#define _SDIO_TFRMODE_MULTSINGBLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_MULTSINGBLKSEL_SINGLEBLK 0x00000000UL /**< Mode SINGLEBLK for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_MULTSINGBLKSEL_MULTIBLK 0x00000001UL /**< Mode MULTIBLK for SDIO_TFRMODE */ +#define SDIO_TFRMODE_MULTSINGBLKSEL_DEFAULT (_SDIO_TFRMODE_MULTSINGBLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_MULTSINGBLKSEL_SINGLEBLK (_SDIO_TFRMODE_MULTSINGBLKSEL_SINGLEBLK << 5) /**< Shifted mode SINGLEBLK for SDIO_TFRMODE */ +#define SDIO_TFRMODE_MULTSINGBLKSEL_MULTIBLK (_SDIO_TFRMODE_MULTSINGBLKSEL_MULTIBLK << 5) /**< Shifted mode MULTIBLK for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_RESPTYPESEL_SHIFT 16 /**< Shift value for SDIO_RESPTYPESEL */ +#define _SDIO_TFRMODE_RESPTYPESEL_MASK 0x30000UL /**< Bit mask for SDIO_RESPTYPESEL */ +#define _SDIO_TFRMODE_RESPTYPESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_RESPTYPESEL_NORESP 0x00000000UL /**< Mode NORESP for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_RESPTYPESEL_RESP136 0x00000001UL /**< Mode RESP136 for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_RESPTYPESEL_RESP48 0x00000002UL /**< Mode RESP48 for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_RESPTYPESEL_BUSYAFTRESP 0x00000003UL /**< Mode BUSYAFTRESP for SDIO_TFRMODE */ +#define SDIO_TFRMODE_RESPTYPESEL_DEFAULT (_SDIO_TFRMODE_RESPTYPESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_RESPTYPESEL_NORESP (_SDIO_TFRMODE_RESPTYPESEL_NORESP << 16) /**< Shifted mode NORESP for SDIO_TFRMODE */ +#define SDIO_TFRMODE_RESPTYPESEL_RESP136 (_SDIO_TFRMODE_RESPTYPESEL_RESP136 << 16) /**< Shifted mode RESP136 for SDIO_TFRMODE */ +#define SDIO_TFRMODE_RESPTYPESEL_RESP48 (_SDIO_TFRMODE_RESPTYPESEL_RESP48 << 16) /**< Shifted mode RESP48 for SDIO_TFRMODE */ +#define SDIO_TFRMODE_RESPTYPESEL_BUSYAFTRESP (_SDIO_TFRMODE_RESPTYPESEL_BUSYAFTRESP << 16) /**< Shifted mode BUSYAFTRESP for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDCRCCHKEN (0x1UL << 19) /**< Command CRC Check Enable */ +#define _SDIO_TFRMODE_CMDCRCCHKEN_SHIFT 19 /**< Shift value for SDIO_CMDCRCCHKEN */ +#define _SDIO_TFRMODE_CMDCRCCHKEN_MASK 0x80000UL /**< Bit mask for SDIO_CMDCRCCHKEN */ +#define _SDIO_TFRMODE_CMDCRCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_CMDCRCCHKEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_CMDCRCCHKEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDCRCCHKEN_DEFAULT (_SDIO_TFRMODE_CMDCRCCHKEN_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDCRCCHKEN_DISABLE (_SDIO_TFRMODE_CMDCRCCHKEN_DISABLE << 19) /**< Shifted mode DISABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDCRCCHKEN_ENABLE (_SDIO_TFRMODE_CMDCRCCHKEN_ENABLE << 19) /**< Shifted mode ENABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDINDXCHKEN (0x1UL << 20) /**< Command Index Check Enable */ +#define _SDIO_TFRMODE_CMDINDXCHKEN_SHIFT 20 /**< Shift value for SDIO_CMDINDXCHKEN */ +#define _SDIO_TFRMODE_CMDINDXCHKEN_MASK 0x100000UL /**< Bit mask for SDIO_CMDINDXCHKEN */ +#define _SDIO_TFRMODE_CMDINDXCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_CMDINDXCHKEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_CMDINDXCHKEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDINDXCHKEN_DEFAULT (_SDIO_TFRMODE_CMDINDXCHKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDINDXCHKEN_DISABLE (_SDIO_TFRMODE_CMDINDXCHKEN_DISABLE << 20) /**< Shifted mode DISABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDINDXCHKEN_ENABLE (_SDIO_TFRMODE_CMDINDXCHKEN_ENABLE << 20) /**< Shifted mode ENABLE for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DATPRESSEL (0x1UL << 21) /**< Data Present Select */ +#define _SDIO_TFRMODE_DATPRESSEL_SHIFT 21 /**< Shift value for SDIO_DATPRESSEL */ +#define _SDIO_TFRMODE_DATPRESSEL_MASK 0x200000UL /**< Bit mask for SDIO_DATPRESSEL */ +#define _SDIO_TFRMODE_DATPRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_DATPRESSEL_NODATA 0x00000000UL /**< Mode NODATA for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_DATPRESSEL_DATA 0x00000001UL /**< Mode DATA for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DATPRESSEL_DEFAULT (_SDIO_TFRMODE_DATPRESSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DATPRESSEL_NODATA (_SDIO_TFRMODE_DATPRESSEL_NODATA << 21) /**< Shifted mode NODATA for SDIO_TFRMODE */ +#define SDIO_TFRMODE_DATPRESSEL_DATA (_SDIO_TFRMODE_DATPRESSEL_DATA << 21) /**< Shifted mode DATA for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_CMDTYPE_SHIFT 22 /**< Shift value for SDIO_CMDTYPE */ +#define _SDIO_TFRMODE_CMDTYPE_MASK 0xC00000UL /**< Bit mask for SDIO_CMDTYPE */ +#define _SDIO_TFRMODE_CMDTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_CMDTYPE_NORMAL 0x00000000UL /**< Mode NORMAL for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_CMDTYPE_SUSPEND 0x00000001UL /**< Mode SUSPEND for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_CMDTYPE_RESUME 0x00000002UL /**< Mode RESUME for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_CMDTYPE_ABORT 0x00000003UL /**< Mode ABORT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDTYPE_DEFAULT (_SDIO_TFRMODE_CMDTYPE_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDTYPE_NORMAL (_SDIO_TFRMODE_CMDTYPE_NORMAL << 22) /**< Shifted mode NORMAL for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDTYPE_SUSPEND (_SDIO_TFRMODE_CMDTYPE_SUSPEND << 22) /**< Shifted mode SUSPEND for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDTYPE_RESUME (_SDIO_TFRMODE_CMDTYPE_RESUME << 22) /**< Shifted mode RESUME for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDTYPE_ABORT (_SDIO_TFRMODE_CMDTYPE_ABORT << 22) /**< Shifted mode ABORT for SDIO_TFRMODE */ +#define _SDIO_TFRMODE_CMDINDEX_SHIFT 24 /**< Shift value for SDIO_CMDINDEX */ +#define _SDIO_TFRMODE_CMDINDEX_MASK 0x3F000000UL /**< Bit mask for SDIO_CMDINDEX */ +#define _SDIO_TFRMODE_CMDINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */ +#define SDIO_TFRMODE_CMDINDEX_DEFAULT (_SDIO_TFRMODE_CMDINDEX_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_TFRMODE */ + +/* Bit fields for SDIO RESP0 */ +#define _SDIO_RESP0_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP0 */ +#define _SDIO_RESP0_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP0 */ +#define _SDIO_RESP0_CMDRESP0_SHIFT 0 /**< Shift value for SDIO_CMDRESP0 */ +#define _SDIO_RESP0_CMDRESP0_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP0 */ +#define _SDIO_RESP0_CMDRESP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP0 */ +#define SDIO_RESP0_CMDRESP0_DEFAULT (_SDIO_RESP0_CMDRESP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP0 */ + +/* Bit fields for SDIO RESP2 */ +#define _SDIO_RESP2_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP2 */ +#define _SDIO_RESP2_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP2 */ +#define _SDIO_RESP2_CMDRESP1_SHIFT 0 /**< Shift value for SDIO_CMDRESP1 */ +#define _SDIO_RESP2_CMDRESP1_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP1 */ +#define _SDIO_RESP2_CMDRESP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP2 */ +#define SDIO_RESP2_CMDRESP1_DEFAULT (_SDIO_RESP2_CMDRESP1_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP2 */ + +/* Bit fields for SDIO RESP4 */ +#define _SDIO_RESP4_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP4 */ +#define _SDIO_RESP4_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP4 */ +#define _SDIO_RESP4_CMDRESP2_SHIFT 0 /**< Shift value for SDIO_CMDRESP2 */ +#define _SDIO_RESP4_CMDRESP2_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP2 */ +#define _SDIO_RESP4_CMDRESP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP4 */ +#define SDIO_RESP4_CMDRESP2_DEFAULT (_SDIO_RESP4_CMDRESP2_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP4 */ + +/* Bit fields for SDIO RESP6 */ +#define _SDIO_RESP6_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP6 */ +#define _SDIO_RESP6_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP6 */ +#define _SDIO_RESP6_CMDRESP3_SHIFT 0 /**< Shift value for SDIO_CMDRESP3 */ +#define _SDIO_RESP6_CMDRESP3_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP3 */ +#define _SDIO_RESP6_CMDRESP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP6 */ +#define SDIO_RESP6_CMDRESP3_DEFAULT (_SDIO_RESP6_CMDRESP3_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP6 */ + +/* Bit fields for SDIO BUFDATPORT */ +#define _SDIO_BUFDATPORT_RESETVALUE 0x00000000UL /**< Default value for SDIO_BUFDATPORT */ +#define _SDIO_BUFDATPORT_MASK 0xFFFFFFFFUL /**< Mask for SDIO_BUFDATPORT */ +#define _SDIO_BUFDATPORT_BUFDAT_SHIFT 0 /**< Shift value for SDIO_BUFDAT */ +#define _SDIO_BUFDATPORT_BUFDAT_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_BUFDAT */ +#define _SDIO_BUFDATPORT_BUFDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BUFDATPORT */ +#define SDIO_BUFDATPORT_BUFDAT_DEFAULT (_SDIO_BUFDATPORT_BUFDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_BUFDATPORT */ + +/* Bit fields for SDIO PRSSTAT */ +#define _SDIO_PRSSTAT_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSSTAT */ +#define _SDIO_PRSSTAT_MASK 0x1FFF0F0FUL /**< Mask for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CMDINHIBITCMD (0x1UL << 0) /**< Command Inhibit (CMD) */ +#define _SDIO_PRSSTAT_CMDINHIBITCMD_SHIFT 0 /**< Shift value for SDIO_CMDINHIBITCMD */ +#define _SDIO_PRSSTAT_CMDINHIBITCMD_MASK 0x1UL /**< Bit mask for SDIO_CMDINHIBITCMD */ +#define _SDIO_PRSSTAT_CMDINHIBITCMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CMDINHIBITCMD_DEFAULT (_SDIO_PRSSTAT_CMDINHIBITCMD_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CMDINHIBITDAT (0x1UL << 1) /**< Command Inhibit (DAT) */ +#define _SDIO_PRSSTAT_CMDINHIBITDAT_SHIFT 1 /**< Shift value for SDIO_CMDINHIBITDAT */ +#define _SDIO_PRSSTAT_CMDINHIBITDAT_MASK 0x2UL /**< Bit mask for SDIO_CMDINHIBITDAT */ +#define _SDIO_PRSSTAT_CMDINHIBITDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CMDINHIBITDAT_DEFAULT (_SDIO_PRSSTAT_CMDINHIBITDAT_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_DATLINEACTIVE (0x1UL << 2) /**< DAT Line Active */ +#define _SDIO_PRSSTAT_DATLINEACTIVE_SHIFT 2 /**< Shift value for SDIO_DATLINEACTIVE */ +#define _SDIO_PRSSTAT_DATLINEACTIVE_MASK 0x4UL /**< Bit mask for SDIO_DATLINEACTIVE */ +#define _SDIO_PRSSTAT_DATLINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_DATLINEACTIVE_DEFAULT (_SDIO_PRSSTAT_DATLINEACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_RETUNINGREQ (0x1UL << 3) /**< Re-Tuning Request */ +#define _SDIO_PRSSTAT_RETUNINGREQ_SHIFT 3 /**< Shift value for SDIO_RETUNINGREQ */ +#define _SDIO_PRSSTAT_RETUNINGREQ_MASK 0x8UL /**< Bit mask for SDIO_RETUNINGREQ */ +#define _SDIO_PRSSTAT_RETUNINGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_RETUNINGREQ_DEFAULT (_SDIO_PRSSTAT_RETUNINGREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_WRTRANACT (0x1UL << 8) /**< Write Transfer Active */ +#define _SDIO_PRSSTAT_WRTRANACT_SHIFT 8 /**< Shift value for SDIO_WRTRANACT */ +#define _SDIO_PRSSTAT_WRTRANACT_MASK 0x100UL /**< Bit mask for SDIO_WRTRANACT */ +#define _SDIO_PRSSTAT_WRTRANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_WRTRANACT_DEFAULT (_SDIO_PRSSTAT_WRTRANACT_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_RDTRANACT (0x1UL << 9) /**< Read Transfer Active */ +#define _SDIO_PRSSTAT_RDTRANACT_SHIFT 9 /**< Shift value for SDIO_RDTRANACT */ +#define _SDIO_PRSSTAT_RDTRANACT_MASK 0x200UL /**< Bit mask for SDIO_RDTRANACT */ +#define _SDIO_PRSSTAT_RDTRANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_RDTRANACT_DEFAULT (_SDIO_PRSSTAT_RDTRANACT_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_BUFFERWRITEENABLE (0x1UL << 10) /**< Buffer Write Enable */ +#define _SDIO_PRSSTAT_BUFFERWRITEENABLE_SHIFT 10 /**< Shift value for SDIO_BUFFERWRITEENABLE */ +#define _SDIO_PRSSTAT_BUFFERWRITEENABLE_MASK 0x400UL /**< Bit mask for SDIO_BUFFERWRITEENABLE */ +#define _SDIO_PRSSTAT_BUFFERWRITEENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_BUFFERWRITEENABLE_DEFAULT (_SDIO_PRSSTAT_BUFFERWRITEENABLE_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_BUFRDEN (0x1UL << 11) /**< Buffer Read Enable */ +#define _SDIO_PRSSTAT_BUFRDEN_SHIFT 11 /**< Shift value for SDIO_BUFRDEN */ +#define _SDIO_PRSSTAT_BUFRDEN_MASK 0x800UL /**< Bit mask for SDIO_BUFRDEN */ +#define _SDIO_PRSSTAT_BUFRDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_BUFRDEN_DEFAULT (_SDIO_PRSSTAT_BUFRDEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CARDINS (0x1UL << 16) /**< Card Inserted Status */ +#define _SDIO_PRSSTAT_CARDINS_SHIFT 16 /**< Shift value for SDIO_CARDINS */ +#define _SDIO_PRSSTAT_CARDINS_MASK 0x10000UL /**< Bit mask for SDIO_CARDINS */ +#define _SDIO_PRSSTAT_CARDINS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CARDINS_DEFAULT (_SDIO_PRSSTAT_CARDINS_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CARDSTATESTABLE (0x1UL << 17) /**< Card State Stable Status */ +#define _SDIO_PRSSTAT_CARDSTATESTABLE_SHIFT 17 /**< Shift value for SDIO_CARDSTATESTABLE */ +#define _SDIO_PRSSTAT_CARDSTATESTABLE_MASK 0x20000UL /**< Bit mask for SDIO_CARDSTATESTABLE */ +#define _SDIO_PRSSTAT_CARDSTATESTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CARDSTATESTABLE_DEFAULT (_SDIO_PRSSTAT_CARDSTATESTABLE_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CARDDETPINLVL (0x1UL << 18) /**< Card Detect Pin Level */ +#define _SDIO_PRSSTAT_CARDDETPINLVL_SHIFT 18 /**< Shift value for SDIO_CARDDETPINLVL */ +#define _SDIO_PRSSTAT_CARDDETPINLVL_MASK 0x40000UL /**< Bit mask for SDIO_CARDDETPINLVL */ +#define _SDIO_PRSSTAT_CARDDETPINLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CARDDETPINLVL_DEFAULT (_SDIO_PRSSTAT_CARDDETPINLVL_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_WRPROTSWPINLVL (0x1UL << 19) /**< Write Protect Switch Pin Level */ +#define _SDIO_PRSSTAT_WRPROTSWPINLVL_SHIFT 19 /**< Shift value for SDIO_WRPROTSWPINLVL */ +#define _SDIO_PRSSTAT_WRPROTSWPINLVL_MASK 0x80000UL /**< Bit mask for SDIO_WRPROTSWPINLVL */ +#define _SDIO_PRSSTAT_WRPROTSWPINLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_WRPROTSWPINLVL_DEFAULT (_SDIO_PRSSTAT_WRPROTSWPINLVL_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define _SDIO_PRSSTAT_DAT3TO0SIGLVL_SHIFT 20 /**< Shift value for SDIO_DAT3TO0SIGLVL */ +#define _SDIO_PRSSTAT_DAT3TO0SIGLVL_MASK 0xF00000UL /**< Bit mask for SDIO_DAT3TO0SIGLVL */ +#define _SDIO_PRSSTAT_DAT3TO0SIGLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_DAT3TO0SIGLVL_DEFAULT (_SDIO_PRSSTAT_DAT3TO0SIGLVL_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CMDSIGLVL (0x1UL << 24) /**< Command Line Signal Level */ +#define _SDIO_PRSSTAT_CMDSIGLVL_SHIFT 24 /**< Shift value for SDIO_CMDSIGLVL */ +#define _SDIO_PRSSTAT_CMDSIGLVL_MASK 0x1000000UL /**< Bit mask for SDIO_CMDSIGLVL */ +#define _SDIO_PRSSTAT_CMDSIGLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_CMDSIGLVL_DEFAULT (_SDIO_PRSSTAT_CMDSIGLVL_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ +#define _SDIO_PRSSTAT_DAT7TO4SIGLVL_SHIFT 25 /**< Shift value for SDIO_DAT7TO4SIGLVL */ +#define _SDIO_PRSSTAT_DAT7TO4SIGLVL_MASK 0x1E000000UL /**< Bit mask for SDIO_DAT7TO4SIGLVL */ +#define _SDIO_PRSSTAT_DAT7TO4SIGLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */ +#define SDIO_PRSSTAT_DAT7TO4SIGLVL_DEFAULT (_SDIO_PRSSTAT_DAT7TO4SIGLVL_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */ + +/* Bit fields for SDIO HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_RESETVALUE 0x00800000UL /**< Default value for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_MASK 0x07FF1FFFUL /**< Mask for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_LEDCTRL (0x1UL << 0) /**< LED Control */ +#define _SDIO_HOSTCTRL1_LEDCTRL_SHIFT 0 /**< Shift value for SDIO_LEDCTRL */ +#define _SDIO_HOSTCTRL1_LEDCTRL_MASK 0x1UL /**< Bit mask for SDIO_LEDCTRL */ +#define _SDIO_HOSTCTRL1_LEDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_LEDCTRL_LEDOFF 0x00000000UL /**< Mode LEDOFF for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_LEDCTRL_LEDON 0x00000001UL /**< Mode LEDON for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_LEDCTRL_DEFAULT (_SDIO_HOSTCTRL1_LEDCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_LEDCTRL_LEDOFF (_SDIO_HOSTCTRL1_LEDCTRL_LEDOFF << 0) /**< Shifted mode LEDOFF for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_LEDCTRL_LEDON (_SDIO_HOSTCTRL1_LEDCTRL_LEDON << 0) /**< Shifted mode LEDON for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_DATTRANWD (0x1UL << 1) /**< Data Transfer Width 1-bit or 4-bit Mode */ +#define _SDIO_HOSTCTRL1_DATTRANWD_SHIFT 1 /**< Shift value for SDIO_DATTRANWD */ +#define _SDIO_HOSTCTRL1_DATTRANWD_MASK 0x2UL /**< Bit mask for SDIO_DATTRANWD */ +#define _SDIO_HOSTCTRL1_DATTRANWD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_DATTRANWD_SD1 0x00000000UL /**< Mode SD1 for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_DATTRANWD_SD4 0x00000001UL /**< Mode SD4 for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_DATTRANWD_DEFAULT (_SDIO_HOSTCTRL1_DATTRANWD_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_DATTRANWD_SD1 (_SDIO_HOSTCTRL1_DATTRANWD_SD1 << 1) /**< Shifted mode SD1 for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_DATTRANWD_SD4 (_SDIO_HOSTCTRL1_DATTRANWD_SD4 << 1) /**< Shifted mode SD4 for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_HSEN (0x1UL << 2) /**< High Speed Enable */ +#define _SDIO_HOSTCTRL1_HSEN_SHIFT 2 /**< Shift value for SDIO_HSEN */ +#define _SDIO_HOSTCTRL1_HSEN_MASK 0x4UL /**< Bit mask for SDIO_HSEN */ +#define _SDIO_HOSTCTRL1_HSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_HSEN_NS 0x00000000UL /**< Mode NS for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_HSEN_HS 0x00000001UL /**< Mode HS for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_HSEN_DEFAULT (_SDIO_HOSTCTRL1_HSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_HSEN_NS (_SDIO_HOSTCTRL1_HSEN_NS << 2) /**< Shifted mode NS for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_HSEN_HS (_SDIO_HOSTCTRL1_HSEN_HS << 2) /**< Shifted mode HS for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_DMASEL_SHIFT 3 /**< Shift value for SDIO_DMASEL */ +#define _SDIO_HOSTCTRL1_DMASEL_MASK 0x18UL /**< Bit mask for SDIO_DMASEL */ +#define _SDIO_HOSTCTRL1_DMASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_DMASEL_SDMA 0x00000000UL /**< Mode SDMA for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_DMASEL_ADMA1 0x00000001UL /**< Mode ADMA1 for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_DMASEL_ADMA2 0x00000002UL /**< Mode ADMA2 for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_DMASEL_64BITADMA2 0x00000003UL /**< Mode 64BITADMA2 for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_DMASEL_DEFAULT (_SDIO_HOSTCTRL1_DMASEL_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_DMASEL_SDMA (_SDIO_HOSTCTRL1_DMASEL_SDMA << 3) /**< Shifted mode SDMA for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_DMASEL_ADMA1 (_SDIO_HOSTCTRL1_DMASEL_ADMA1 << 3) /**< Shifted mode ADMA1 for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_DMASEL_ADMA2 (_SDIO_HOSTCTRL1_DMASEL_ADMA2 << 3) /**< Shifted mode ADMA2 for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_DMASEL_64BITADMA2 (_SDIO_HOSTCTRL1_DMASEL_64BITADMA2 << 3) /**< Shifted mode 64BITADMA2 for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_EXTDATTRANWD (0x1UL << 5) /**< Extended Data Transfer Width */ +#define _SDIO_HOSTCTRL1_EXTDATTRANWD_SHIFT 5 /**< Shift value for SDIO_EXTDATTRANWD */ +#define _SDIO_HOSTCTRL1_EXTDATTRANWD_MASK 0x20UL /**< Bit mask for SDIO_EXTDATTRANWD */ +#define _SDIO_HOSTCTRL1_EXTDATTRANWD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_EXTDATTRANWD_8BIT 0x00000000UL /**< Mode 8BIT for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_EXTDATTRANWD_DATXFR 0x00000001UL /**< Mode DATXFR for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_EXTDATTRANWD_DEFAULT (_SDIO_HOSTCTRL1_EXTDATTRANWD_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_EXTDATTRANWD_8BIT (_SDIO_HOSTCTRL1_EXTDATTRANWD_8BIT << 5) /**< Shifted mode 8BIT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_EXTDATTRANWD_DATXFR (_SDIO_HOSTCTRL1_EXTDATTRANWD_DATXFR << 5) /**< Shifted mode DATXFR for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_CDTSTLVL (0x1UL << 6) /**< Card Detect Test Level */ +#define _SDIO_HOSTCTRL1_CDTSTLVL_SHIFT 6 /**< Shift value for SDIO_CDTSTLVL */ +#define _SDIO_HOSTCTRL1_CDTSTLVL_MASK 0x40UL /**< Bit mask for SDIO_CDTSTLVL */ +#define _SDIO_HOSTCTRL1_CDTSTLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_CDTSTLVL_NOCARD 0x00000000UL /**< Mode NOCARD for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_CDTSTLVL_CARDIN 0x00000001UL /**< Mode CARDIN for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_CDTSTLVL_DEFAULT (_SDIO_HOSTCTRL1_CDTSTLVL_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_CDTSTLVL_NOCARD (_SDIO_HOSTCTRL1_CDTSTLVL_NOCARD << 6) /**< Shifted mode NOCARD for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_CDTSTLVL_CARDIN (_SDIO_HOSTCTRL1_CDTSTLVL_CARDIN << 6) /**< Shifted mode CARDIN for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_CDSIGDET (0x1UL << 7) /**< Card Detetct Signal Detection */ +#define _SDIO_HOSTCTRL1_CDSIGDET_SHIFT 7 /**< Shift value for SDIO_CDSIGDET */ +#define _SDIO_HOSTCTRL1_CDSIGDET_MASK 0x80UL /**< Bit mask for SDIO_CDSIGDET */ +#define _SDIO_HOSTCTRL1_CDSIGDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_CDSIGDET_SDCD 0x00000000UL /**< Mode SDCD for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_CDSIGDET_TSTLVL 0x00000001UL /**< Mode TSTLVL for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_CDSIGDET_DEFAULT (_SDIO_HOSTCTRL1_CDSIGDET_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_CDSIGDET_SDCD (_SDIO_HOSTCTRL1_CDSIGDET_SDCD << 7) /**< Shifted mode SDCD for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_CDSIGDET_TSTLVL (_SDIO_HOSTCTRL1_CDSIGDET_TSTLVL << 7) /**< Shifted mode TSTLVL for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_SDBUSPOWER (0x1UL << 8) /**< SD Bus Power */ +#define _SDIO_HOSTCTRL1_SDBUSPOWER_SHIFT 8 /**< Shift value for SDIO_SDBUSPOWER */ +#define _SDIO_HOSTCTRL1_SDBUSPOWER_MASK 0x100UL /**< Bit mask for SDIO_SDBUSPOWER */ +#define _SDIO_HOSTCTRL1_SDBUSPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_SDBUSPOWER_DEFAULT (_SDIO_HOSTCTRL1_SDBUSPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_SHIFT 9 /**< Shift value for SDIO_SDBUSVOLTSEL */ +#define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_MASK 0xE00UL /**< Bit mask for SDIO_SDBUSVOLTSEL */ +#define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_1P8V 0x00000005UL /**< Mode 1P8V for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P0V 0x00000006UL /**< Mode 3P0V for SDIO_HOSTCTRL1 */ +#define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P3V 0x00000007UL /**< Mode 3P3V for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_SDBUSVOLTSEL_DEFAULT (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_SDBUSVOLTSEL_1P8V (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_1P8V << 9) /**< Shifted mode 1P8V for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P0V (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P0V << 9) /**< Shifted mode 3P0V for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P3V (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P3V << 9) /**< Shifted mode 3P3V for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_HRDRST (0x1UL << 12) /**< Hardware Reset Signal */ +#define _SDIO_HOSTCTRL1_HRDRST_SHIFT 12 /**< Shift value for SDIO_HRDRST */ +#define _SDIO_HOSTCTRL1_HRDRST_MASK 0x1000UL /**< Bit mask for SDIO_HRDRST */ +#define _SDIO_HOSTCTRL1_HRDRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_HRDRST_DEFAULT (_SDIO_HOSTCTRL1_HRDRST_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_STOPATBLKGAPREQ (0x1UL << 16) /**< Stop at Block Gap Request */ +#define _SDIO_HOSTCTRL1_STOPATBLKGAPREQ_SHIFT 16 /**< Shift value for SDIO_STOPATBLKGAPREQ */ +#define _SDIO_HOSTCTRL1_STOPATBLKGAPREQ_MASK 0x10000UL /**< Bit mask for SDIO_STOPATBLKGAPREQ */ +#define _SDIO_HOSTCTRL1_STOPATBLKGAPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_STOPATBLKGAPREQ_DEFAULT (_SDIO_HOSTCTRL1_STOPATBLKGAPREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_CONTINUEREQ (0x1UL << 17) /**< Continue Request */ +#define _SDIO_HOSTCTRL1_CONTINUEREQ_SHIFT 17 /**< Shift value for SDIO_CONTINUEREQ */ +#define _SDIO_HOSTCTRL1_CONTINUEREQ_MASK 0x20000UL /**< Bit mask for SDIO_CONTINUEREQ */ +#define _SDIO_HOSTCTRL1_CONTINUEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_CONTINUEREQ_DEFAULT (_SDIO_HOSTCTRL1_CONTINUEREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_RDWAITCTRL (0x1UL << 18) /**< Read Wait Control */ +#define _SDIO_HOSTCTRL1_RDWAITCTRL_SHIFT 18 /**< Shift value for SDIO_RDWAITCTRL */ +#define _SDIO_HOSTCTRL1_RDWAITCTRL_MASK 0x40000UL /**< Bit mask for SDIO_RDWAITCTRL */ +#define _SDIO_HOSTCTRL1_RDWAITCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_RDWAITCTRL_DEFAULT (_SDIO_HOSTCTRL1_RDWAITCTRL_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_INTATBLKGAP (0x1UL << 19) /**< Interrupt at Block Gap */ +#define _SDIO_HOSTCTRL1_INTATBLKGAP_SHIFT 19 /**< Shift value for SDIO_INTATBLKGAP */ +#define _SDIO_HOSTCTRL1_INTATBLKGAP_MASK 0x80000UL /**< Bit mask for SDIO_INTATBLKGAP */ +#define _SDIO_HOSTCTRL1_INTATBLKGAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_INTATBLKGAP_DEFAULT (_SDIO_HOSTCTRL1_INTATBLKGAP_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_SPIMODE (0x1UL << 20) /**< SPI Mode Enable */ +#define _SDIO_HOSTCTRL1_SPIMODE_SHIFT 20 /**< Shift value for SDIO_SPIMODE */ +#define _SDIO_HOSTCTRL1_SPIMODE_MASK 0x100000UL /**< Bit mask for SDIO_SPIMODE */ +#define _SDIO_HOSTCTRL1_SPIMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_SPIMODE_DEFAULT (_SDIO_HOSTCTRL1_SPIMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_BOOTEN (0x1UL << 21) /**< Boot Enable */ +#define _SDIO_HOSTCTRL1_BOOTEN_SHIFT 21 /**< Shift value for SDIO_BOOTEN */ +#define _SDIO_HOSTCTRL1_BOOTEN_MASK 0x200000UL /**< Bit mask for SDIO_BOOTEN */ +#define _SDIO_HOSTCTRL1_BOOTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_BOOTEN_DEFAULT (_SDIO_HOSTCTRL1_BOOTEN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_ALTBOOTEN (0x1UL << 22) /**< Alternate Boot Enable */ +#define _SDIO_HOSTCTRL1_ALTBOOTEN_SHIFT 22 /**< Shift value for SDIO_ALTBOOTEN */ +#define _SDIO_HOSTCTRL1_ALTBOOTEN_MASK 0x400000UL /**< Bit mask for SDIO_ALTBOOTEN */ +#define _SDIO_HOSTCTRL1_ALTBOOTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_ALTBOOTEN_DEFAULT (_SDIO_HOSTCTRL1_ALTBOOTEN_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_BOOTACKCHK (0x1UL << 23) /**< Boot Ack Check */ +#define _SDIO_HOSTCTRL1_BOOTACKCHK_SHIFT 23 /**< Shift value for SDIO_BOOTACKCHK */ +#define _SDIO_HOSTCTRL1_BOOTACKCHK_MASK 0x800000UL /**< Bit mask for SDIO_BOOTACKCHK */ +#define _SDIO_HOSTCTRL1_BOOTACKCHK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_BOOTACKCHK_DEFAULT (_SDIO_HOSTCTRL1_BOOTACKCHK_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT (0x1UL << 24) /**< Wakeup Event Enable on Card Interrupt */ +#define _SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_SHIFT 24 /**< Shift value for SDIO_WKUPEVNTENONCARDINT */ +#define _SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_MASK 0x1000000UL /**< Bit mask for SDIO_WKUPEVNTENONCARDINT */ +#define _SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_DEFAULT (_SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_WKUPEVNTENONCINS (0x1UL << 25) /**< Wakeup Event Enable on SD Card Insertion */ +#define _SDIO_HOSTCTRL1_WKUPEVNTENONCINS_SHIFT 25 /**< Shift value for SDIO_WKUPEVNTENONCINS */ +#define _SDIO_HOSTCTRL1_WKUPEVNTENONCINS_MASK 0x2000000UL /**< Bit mask for SDIO_WKUPEVNTENONCINS */ +#define _SDIO_HOSTCTRL1_WKUPEVNTENONCINS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_WKUPEVNTENONCINS_DEFAULT (_SDIO_HOSTCTRL1_WKUPEVNTENONCINS_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_WKUPEVNTENONCRM (0x1UL << 26) /**< Wakeup Event Enable on SD Card Removal */ +#define _SDIO_HOSTCTRL1_WKUPEVNTENONCRM_SHIFT 26 /**< Shift value for SDIO_WKUPEVNTENONCRM */ +#define _SDIO_HOSTCTRL1_WKUPEVNTENONCRM_MASK 0x4000000UL /**< Bit mask for SDIO_WKUPEVNTENONCRM */ +#define _SDIO_HOSTCTRL1_WKUPEVNTENONCRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */ +#define SDIO_HOSTCTRL1_WKUPEVNTENONCRM_DEFAULT (_SDIO_HOSTCTRL1_WKUPEVNTENONCRM_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */ + +/* Bit fields for SDIO CLOCKCTRL */ +#define _SDIO_CLOCKCTRL_RESETVALUE 0x00000000UL /**< Default value for SDIO_CLOCKCTRL */ +#define _SDIO_CLOCKCTRL_MASK 0x070FFFE7UL /**< Mask for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_INTCLKEN (0x1UL << 0) /**< Internal Clock Enable */ +#define _SDIO_CLOCKCTRL_INTCLKEN_SHIFT 0 /**< Shift value for SDIO_INTCLKEN */ +#define _SDIO_CLOCKCTRL_INTCLKEN_MASK 0x1UL /**< Bit mask for SDIO_INTCLKEN */ +#define _SDIO_CLOCKCTRL_INTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_INTCLKEN_DEFAULT (_SDIO_CLOCKCTRL_INTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_INTCLKSTABLE (0x1UL << 1) /**< Internal Clock Stable */ +#define _SDIO_CLOCKCTRL_INTCLKSTABLE_SHIFT 1 /**< Shift value for SDIO_INTCLKSTABLE */ +#define _SDIO_CLOCKCTRL_INTCLKSTABLE_MASK 0x2UL /**< Bit mask for SDIO_INTCLKSTABLE */ +#define _SDIO_CLOCKCTRL_INTCLKSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_INTCLKSTABLE_DEFAULT (_SDIO_CLOCKCTRL_INTCLKSTABLE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_SDCLKEN (0x1UL << 2) /**< SDIO_CLK Pin Clock Enable */ +#define _SDIO_CLOCKCTRL_SDCLKEN_SHIFT 2 /**< Shift value for SDIO_SDCLKEN */ +#define _SDIO_CLOCKCTRL_SDCLKEN_MASK 0x4UL /**< Bit mask for SDIO_SDCLKEN */ +#define _SDIO_CLOCKCTRL_SDCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_SDCLKEN_DEFAULT (_SDIO_CLOCKCTRL_SDCLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_CLKGENSEL (0x1UL << 5) /**< Clock Generator Select */ +#define _SDIO_CLOCKCTRL_CLKGENSEL_SHIFT 5 /**< Shift value for SDIO_CLKGENSEL */ +#define _SDIO_CLOCKCTRL_CLKGENSEL_MASK 0x20UL /**< Bit mask for SDIO_CLKGENSEL */ +#define _SDIO_CLOCKCTRL_CLKGENSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_CLKGENSEL_DEFAULT (_SDIO_CLOCKCTRL_CLKGENSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ +#define _SDIO_CLOCKCTRL_UPPSDCLKFRE_SHIFT 6 /**< Shift value for SDIO_UPPSDCLKFRE */ +#define _SDIO_CLOCKCTRL_UPPSDCLKFRE_MASK 0xC0UL /**< Bit mask for SDIO_UPPSDCLKFRE */ +#define _SDIO_CLOCKCTRL_UPPSDCLKFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_UPPSDCLKFRE_DEFAULT (_SDIO_CLOCKCTRL_UPPSDCLKFRE_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ +#define _SDIO_CLOCKCTRL_SDCLKFREQSEL_SHIFT 8 /**< Shift value for SDIO_SDCLKFREQSEL */ +#define _SDIO_CLOCKCTRL_SDCLKFREQSEL_MASK 0xFF00UL /**< Bit mask for SDIO_SDCLKFREQSEL */ +#define _SDIO_CLOCKCTRL_SDCLKFREQSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ +#define _SDIO_CLOCKCTRL_SDCLKFREQSEL_NODIVISION 0x00000000UL /**< Mode NODIVISION for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_SDCLKFREQSEL_DEFAULT (_SDIO_CLOCKCTRL_SDCLKFREQSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_SDCLKFREQSEL_NODIVISION (_SDIO_CLOCKCTRL_SDCLKFREQSEL_NODIVISION << 8) /**< Shifted mode NODIVISION for SDIO_CLOCKCTRL */ +#define _SDIO_CLOCKCTRL_DATTOUTCNTVAL_SHIFT 16 /**< Shift value for SDIO_DATTOUTCNTVAL */ +#define _SDIO_CLOCKCTRL_DATTOUTCNTVAL_MASK 0xF0000UL /**< Bit mask for SDIO_DATTOUTCNTVAL */ +#define _SDIO_CLOCKCTRL_DATTOUTCNTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_DATTOUTCNTVAL_DEFAULT (_SDIO_CLOCKCTRL_DATTOUTCNTVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_SFTRSTA (0x1UL << 24) /**< Software Reset for All */ +#define _SDIO_CLOCKCTRL_SFTRSTA_SHIFT 24 /**< Shift value for SDIO_SFTRSTA */ +#define _SDIO_CLOCKCTRL_SFTRSTA_MASK 0x1000000UL /**< Bit mask for SDIO_SFTRSTA */ +#define _SDIO_CLOCKCTRL_SFTRSTA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_SFTRSTA_DEFAULT (_SDIO_CLOCKCTRL_SFTRSTA_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_SFTRSTCMD (0x1UL << 25) /**< Software Reset for CMD Line */ +#define _SDIO_CLOCKCTRL_SFTRSTCMD_SHIFT 25 /**< Shift value for SDIO_SFTRSTCMD */ +#define _SDIO_CLOCKCTRL_SFTRSTCMD_MASK 0x2000000UL /**< Bit mask for SDIO_SFTRSTCMD */ +#define _SDIO_CLOCKCTRL_SFTRSTCMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_SFTRSTCMD_DEFAULT (_SDIO_CLOCKCTRL_SFTRSTCMD_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_SFTRSTDAT (0x1UL << 26) /**< Software Reset for DAT Line */ +#define _SDIO_CLOCKCTRL_SFTRSTDAT_SHIFT 26 /**< Shift value for SDIO_SFTRSTDAT */ +#define _SDIO_CLOCKCTRL_SFTRSTDAT_MASK 0x4000000UL /**< Bit mask for SDIO_SFTRSTDAT */ +#define _SDIO_CLOCKCTRL_SFTRSTDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */ +#define SDIO_CLOCKCTRL_SFTRSTDAT_DEFAULT (_SDIO_CLOCKCTRL_SFTRSTDAT_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */ + +/* Bit fields for SDIO IFCR */ +#define _SDIO_IFCR_RESETVALUE 0x00000000UL /**< Default value for SDIO_IFCR */ +#define _SDIO_IFCR_MASK 0x13FFF1FFUL /**< Mask for SDIO_IFCR */ +#define SDIO_IFCR_CMDCOM (0x1UL << 0) /**< Command Complete */ +#define _SDIO_IFCR_CMDCOM_SHIFT 0 /**< Shift value for SDIO_CMDCOM */ +#define _SDIO_IFCR_CMDCOM_MASK 0x1UL /**< Bit mask for SDIO_CMDCOM */ +#define _SDIO_IFCR_CMDCOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CMDCOM_DEFAULT (_SDIO_IFCR_CMDCOM_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_TRANCOM (0x1UL << 1) /**< Transfer Complete */ +#define _SDIO_IFCR_TRANCOM_SHIFT 1 /**< Shift value for SDIO_TRANCOM */ +#define _SDIO_IFCR_TRANCOM_MASK 0x2UL /**< Bit mask for SDIO_TRANCOM */ +#define _SDIO_IFCR_TRANCOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_TRANCOM_DEFAULT (_SDIO_IFCR_TRANCOM_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_BLKGAPEVT (0x1UL << 2) /**< Block Gap Event */ +#define _SDIO_IFCR_BLKGAPEVT_SHIFT 2 /**< Shift value for SDIO_BLKGAPEVT */ +#define _SDIO_IFCR_BLKGAPEVT_MASK 0x4UL /**< Bit mask for SDIO_BLKGAPEVT */ +#define _SDIO_IFCR_BLKGAPEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_BLKGAPEVT_DEFAULT (_SDIO_IFCR_BLKGAPEVT_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_DMAINT (0x1UL << 3) /**< DMA Interrupt */ +#define _SDIO_IFCR_DMAINT_SHIFT 3 /**< Shift value for SDIO_DMAINT */ +#define _SDIO_IFCR_DMAINT_MASK 0x8UL /**< Bit mask for SDIO_DMAINT */ +#define _SDIO_IFCR_DMAINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_DMAINT_DEFAULT (_SDIO_IFCR_DMAINT_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_BFRWRRDY (0x1UL << 4) /**< Buffer Write Ready */ +#define _SDIO_IFCR_BFRWRRDY_SHIFT 4 /**< Shift value for SDIO_BFRWRRDY */ +#define _SDIO_IFCR_BFRWRRDY_MASK 0x10UL /**< Bit mask for SDIO_BFRWRRDY */ +#define _SDIO_IFCR_BFRWRRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_BFRWRRDY_DEFAULT (_SDIO_IFCR_BFRWRRDY_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_BFRRDRDY (0x1UL << 5) /**< Buffer Read Ready */ +#define _SDIO_IFCR_BFRRDRDY_SHIFT 5 /**< Shift value for SDIO_BFRRDRDY */ +#define _SDIO_IFCR_BFRRDRDY_MASK 0x20UL /**< Bit mask for SDIO_BFRRDRDY */ +#define _SDIO_IFCR_BFRRDRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_BFRRDRDY_DEFAULT (_SDIO_IFCR_BFRRDRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CARDINS (0x1UL << 6) /**< Card Insertion */ +#define _SDIO_IFCR_CARDINS_SHIFT 6 /**< Shift value for SDIO_CARDINS */ +#define _SDIO_IFCR_CARDINS_MASK 0x40UL /**< Bit mask for SDIO_CARDINS */ +#define _SDIO_IFCR_CARDINS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CARDINS_DEFAULT (_SDIO_IFCR_CARDINS_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CARDRM (0x1UL << 7) /**< Card Removal */ +#define _SDIO_IFCR_CARDRM_SHIFT 7 /**< Shift value for SDIO_CARDRM */ +#define _SDIO_IFCR_CARDRM_MASK 0x80UL /**< Bit mask for SDIO_CARDRM */ +#define _SDIO_IFCR_CARDRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CARDRM_DEFAULT (_SDIO_IFCR_CARDRM_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CARDINT (0x1UL << 8) /**< Card Interrupt */ +#define _SDIO_IFCR_CARDINT_SHIFT 8 /**< Shift value for SDIO_CARDINT */ +#define _SDIO_IFCR_CARDINT_MASK 0x100UL /**< Bit mask for SDIO_CARDINT */ +#define _SDIO_IFCR_CARDINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CARDINT_DEFAULT (_SDIO_IFCR_CARDINT_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_RETUNINGEVT (0x1UL << 12) /**< Re-Tunning Event */ +#define _SDIO_IFCR_RETUNINGEVT_SHIFT 12 /**< Shift value for SDIO_RETUNINGEVT */ +#define _SDIO_IFCR_RETUNINGEVT_MASK 0x1000UL /**< Bit mask for SDIO_RETUNINGEVT */ +#define _SDIO_IFCR_RETUNINGEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_RETUNINGEVT_DEFAULT (_SDIO_IFCR_RETUNINGEVT_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_BOOTACKRCV (0x1UL << 13) /**< Boot Ack Received */ +#define _SDIO_IFCR_BOOTACKRCV_SHIFT 13 /**< Shift value for SDIO_BOOTACKRCV */ +#define _SDIO_IFCR_BOOTACKRCV_MASK 0x2000UL /**< Bit mask for SDIO_BOOTACKRCV */ +#define _SDIO_IFCR_BOOTACKRCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_BOOTACKRCV_DEFAULT (_SDIO_IFCR_BOOTACKRCV_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_BOOTTERMINATE (0x1UL << 14) /**< Boot Terminate Interrupt */ +#define _SDIO_IFCR_BOOTTERMINATE_SHIFT 14 /**< Shift value for SDIO_BOOTTERMINATE */ +#define _SDIO_IFCR_BOOTTERMINATE_MASK 0x4000UL /**< Bit mask for SDIO_BOOTTERMINATE */ +#define _SDIO_IFCR_BOOTTERMINATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_BOOTTERMINATE_DEFAULT (_SDIO_IFCR_BOOTTERMINATE_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_ERRINT (0x1UL << 15) /**< Error Interrupt */ +#define _SDIO_IFCR_ERRINT_SHIFT 15 /**< Shift value for SDIO_ERRINT */ +#define _SDIO_IFCR_ERRINT_MASK 0x8000UL /**< Bit mask for SDIO_ERRINT */ +#define _SDIO_IFCR_ERRINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_ERRINT_DEFAULT (_SDIO_IFCR_ERRINT_DEFAULT << 15) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CMDTOUTERR (0x1UL << 16) /**< Command Timeout Error */ +#define _SDIO_IFCR_CMDTOUTERR_SHIFT 16 /**< Shift value for SDIO_CMDTOUTERR */ +#define _SDIO_IFCR_CMDTOUTERR_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOUTERR */ +#define _SDIO_IFCR_CMDTOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CMDTOUTERR_DEFAULT (_SDIO_IFCR_CMDTOUTERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CMDCRCERR (0x1UL << 17) /**< CMD CRC Error */ +#define _SDIO_IFCR_CMDCRCERR_SHIFT 17 /**< Shift value for SDIO_CMDCRCERR */ +#define _SDIO_IFCR_CMDCRCERR_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCERR */ +#define _SDIO_IFCR_CMDCRCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CMDCRCERR_DEFAULT (_SDIO_IFCR_CMDCRCERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CMDENDBITERR (0x1UL << 18) /**< Command End Bit Error */ +#define _SDIO_IFCR_CMDENDBITERR_SHIFT 18 /**< Shift value for SDIO_CMDENDBITERR */ +#define _SDIO_IFCR_CMDENDBITERR_MASK 0x40000UL /**< Bit mask for SDIO_CMDENDBITERR */ +#define _SDIO_IFCR_CMDENDBITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CMDENDBITERR_DEFAULT (_SDIO_IFCR_CMDENDBITERR_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CMDINDEXERR (0x1UL << 19) /**< Command Index Error */ +#define _SDIO_IFCR_CMDINDEXERR_SHIFT 19 /**< Shift value for SDIO_CMDINDEXERR */ +#define _SDIO_IFCR_CMDINDEXERR_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDEXERR */ +#define _SDIO_IFCR_CMDINDEXERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CMDINDEXERR_DEFAULT (_SDIO_IFCR_CMDINDEXERR_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_DATTOUTERR (0x1UL << 20) /**< Data Time-out Error */ +#define _SDIO_IFCR_DATTOUTERR_SHIFT 20 /**< Shift value for SDIO_DATTOUTERR */ +#define _SDIO_IFCR_DATTOUTERR_MASK 0x100000UL /**< Bit mask for SDIO_DATTOUTERR */ +#define _SDIO_IFCR_DATTOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_DATTOUTERR_DEFAULT (_SDIO_IFCR_DATTOUTERR_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_DATCRCERR (0x1UL << 21) /**< Data CRC Error */ +#define _SDIO_IFCR_DATCRCERR_SHIFT 21 /**< Shift value for SDIO_DATCRCERR */ +#define _SDIO_IFCR_DATCRCERR_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCERR */ +#define _SDIO_IFCR_DATCRCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_DATCRCERR_DEFAULT (_SDIO_IFCR_DATCRCERR_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_DATENDBITERR (0x1UL << 22) /**< Data End Bit Error */ +#define _SDIO_IFCR_DATENDBITERR_SHIFT 22 /**< Shift value for SDIO_DATENDBITERR */ +#define _SDIO_IFCR_DATENDBITERR_MASK 0x400000UL /**< Bit mask for SDIO_DATENDBITERR */ +#define _SDIO_IFCR_DATENDBITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_DATENDBITERR_DEFAULT (_SDIO_IFCR_DATENDBITERR_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CURRENTLIMITERR (0x1UL << 23) /**< Current Limit Error */ +#define _SDIO_IFCR_CURRENTLIMITERR_SHIFT 23 /**< Shift value for SDIO_CURRENTLIMITERR */ +#define _SDIO_IFCR_CURRENTLIMITERR_MASK 0x800000UL /**< Bit mask for SDIO_CURRENTLIMITERR */ +#define _SDIO_IFCR_CURRENTLIMITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_CURRENTLIMITERR_DEFAULT (_SDIO_IFCR_CURRENTLIMITERR_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_AUTOCMDERR (0x1UL << 24) /**< Auto CMD Error */ +#define _SDIO_IFCR_AUTOCMDERR_SHIFT 24 /**< Shift value for SDIO_AUTOCMDERR */ +#define _SDIO_IFCR_AUTOCMDERR_MASK 0x1000000UL /**< Bit mask for SDIO_AUTOCMDERR */ +#define _SDIO_IFCR_AUTOCMDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_AUTOCMDERR_DEFAULT (_SDIO_IFCR_AUTOCMDERR_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_ADMAERR (0x1UL << 25) /**< ADMA Error */ +#define _SDIO_IFCR_ADMAERR_SHIFT 25 /**< Shift value for SDIO_ADMAERR */ +#define _SDIO_IFCR_ADMAERR_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAERR */ +#define _SDIO_IFCR_ADMAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_ADMAERR_DEFAULT (_SDIO_IFCR_ADMAERR_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_TARGETRESP (0x1UL << 28) /**< Specific Error STAT */ +#define _SDIO_IFCR_TARGETRESP_SHIFT 28 /**< Shift value for SDIO_TARGETRESP */ +#define _SDIO_IFCR_TARGETRESP_MASK 0x10000000UL /**< Bit mask for SDIO_TARGETRESP */ +#define _SDIO_IFCR_TARGETRESP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */ +#define SDIO_IFCR_TARGETRESP_DEFAULT (_SDIO_IFCR_TARGETRESP_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_IFCR */ + +/* Bit fields for SDIO IFENC */ +#define _SDIO_IFENC_RESETVALUE 0x00000000UL /**< Default value for SDIO_IFENC */ +#define _SDIO_IFENC_MASK 0x17FF71FFUL /**< Mask for SDIO_IFENC */ +#define SDIO_IFENC_CMDCOMEN (0x1UL << 0) /**< Command Complete Signal Enable */ +#define _SDIO_IFENC_CMDCOMEN_SHIFT 0 /**< Shift value for SDIO_CMDCOMEN */ +#define _SDIO_IFENC_CMDCOMEN_MASK 0x1UL /**< Bit mask for SDIO_CMDCOMEN */ +#define _SDIO_IFENC_CMDCOMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CMDCOMEN_DEFAULT (_SDIO_IFENC_CMDCOMEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_TRANCOMEN (0x1UL << 1) /**< Transfer Complete Signal Enable */ +#define _SDIO_IFENC_TRANCOMEN_SHIFT 1 /**< Shift value for SDIO_TRANCOMEN */ +#define _SDIO_IFENC_TRANCOMEN_MASK 0x2UL /**< Bit mask for SDIO_TRANCOMEN */ +#define _SDIO_IFENC_TRANCOMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_TRANCOMEN_DEFAULT (_SDIO_IFENC_TRANCOMEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_BLKGAPEVTEN (0x1UL << 2) /**< Block Gap Event Signal Enable */ +#define _SDIO_IFENC_BLKGAPEVTEN_SHIFT 2 /**< Shift value for SDIO_BLKGAPEVTEN */ +#define _SDIO_IFENC_BLKGAPEVTEN_MASK 0x4UL /**< Bit mask for SDIO_BLKGAPEVTEN */ +#define _SDIO_IFENC_BLKGAPEVTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_BLKGAPEVTEN_DEFAULT (_SDIO_IFENC_BLKGAPEVTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_DMAINTEN (0x1UL << 3) /**< DMA Interrupt Signal Enable */ +#define _SDIO_IFENC_DMAINTEN_SHIFT 3 /**< Shift value for SDIO_DMAINTEN */ +#define _SDIO_IFENC_DMAINTEN_MASK 0x8UL /**< Bit mask for SDIO_DMAINTEN */ +#define _SDIO_IFENC_DMAINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_DMAINTEN_DEFAULT (_SDIO_IFENC_DMAINTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_BUFWRRDYEN (0x1UL << 4) /**< Buffer Write Ready Signal Enable */ +#define _SDIO_IFENC_BUFWRRDYEN_SHIFT 4 /**< Shift value for SDIO_BUFWRRDYEN */ +#define _SDIO_IFENC_BUFWRRDYEN_MASK 0x10UL /**< Bit mask for SDIO_BUFWRRDYEN */ +#define _SDIO_IFENC_BUFWRRDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_BUFWRRDYEN_DEFAULT (_SDIO_IFENC_BUFWRRDYEN_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_BUFRDRDYEN (0x1UL << 5) /**< Buffer Read Ready Signal Enable */ +#define _SDIO_IFENC_BUFRDRDYEN_SHIFT 5 /**< Shift value for SDIO_BUFRDRDYEN */ +#define _SDIO_IFENC_BUFRDRDYEN_MASK 0x20UL /**< Bit mask for SDIO_BUFRDRDYEN */ +#define _SDIO_IFENC_BUFRDRDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_BUFRDRDYEN_DEFAULT (_SDIO_IFENC_BUFRDRDYEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CARDINSEN (0x1UL << 6) /**< Card Insertion Signal Enable */ +#define _SDIO_IFENC_CARDINSEN_SHIFT 6 /**< Shift value for SDIO_CARDINSEN */ +#define _SDIO_IFENC_CARDINSEN_MASK 0x40UL /**< Bit mask for SDIO_CARDINSEN */ +#define _SDIO_IFENC_CARDINSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CARDINSEN_DEFAULT (_SDIO_IFENC_CARDINSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CARDRMEN (0x1UL << 7) /**< Card Removal Signal Enable */ +#define _SDIO_IFENC_CARDRMEN_SHIFT 7 /**< Shift value for SDIO_CARDRMEN */ +#define _SDIO_IFENC_CARDRMEN_MASK 0x80UL /**< Bit mask for SDIO_CARDRMEN */ +#define _SDIO_IFENC_CARDRMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CARDRMEN_DEFAULT (_SDIO_IFENC_CARDRMEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CARDINTEN (0x1UL << 8) /**< Card Interrupt Signal Enable */ +#define _SDIO_IFENC_CARDINTEN_SHIFT 8 /**< Shift value for SDIO_CARDINTEN */ +#define _SDIO_IFENC_CARDINTEN_MASK 0x100UL /**< Bit mask for SDIO_CARDINTEN */ +#define _SDIO_IFENC_CARDINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CARDINTEN_DEFAULT (_SDIO_IFENC_CARDINTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_RETUNINGEVTEN (0x1UL << 12) /**< Re-Tunning Event Signal Enable */ +#define _SDIO_IFENC_RETUNINGEVTEN_SHIFT 12 /**< Shift value for SDIO_RETUNINGEVTEN */ +#define _SDIO_IFENC_RETUNINGEVTEN_MASK 0x1000UL /**< Bit mask for SDIO_RETUNINGEVTEN */ +#define _SDIO_IFENC_RETUNINGEVTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_RETUNINGEVTEN_DEFAULT (_SDIO_IFENC_RETUNINGEVTEN_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_BOOTACKRCVEN (0x1UL << 13) /**< Boot Ack Received Signal Enable */ +#define _SDIO_IFENC_BOOTACKRCVEN_SHIFT 13 /**< Shift value for SDIO_BOOTACKRCVEN */ +#define _SDIO_IFENC_BOOTACKRCVEN_MASK 0x2000UL /**< Bit mask for SDIO_BOOTACKRCVEN */ +#define _SDIO_IFENC_BOOTACKRCVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_BOOTACKRCVEN_DEFAULT (_SDIO_IFENC_BOOTACKRCVEN_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_BOOTTERMINATEEN (0x1UL << 14) /**< Boot Terminate Interrupt Signal Enable */ +#define _SDIO_IFENC_BOOTTERMINATEEN_SHIFT 14 /**< Shift value for SDIO_BOOTTERMINATEEN */ +#define _SDIO_IFENC_BOOTTERMINATEEN_MASK 0x4000UL /**< Bit mask for SDIO_BOOTTERMINATEEN */ +#define _SDIO_IFENC_BOOTTERMINATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_BOOTTERMINATEEN_DEFAULT (_SDIO_IFENC_BOOTTERMINATEEN_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CMDTOUTERREN (0x1UL << 16) /**< Command Time-out Error Status Enable */ +#define _SDIO_IFENC_CMDTOUTERREN_SHIFT 16 /**< Shift value for SDIO_CMDTOUTERREN */ +#define _SDIO_IFENC_CMDTOUTERREN_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOUTERREN */ +#define _SDIO_IFENC_CMDTOUTERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CMDTOUTERREN_DEFAULT (_SDIO_IFENC_CMDTOUTERREN_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CMDCRCERREN (0x1UL << 17) /**< Command CRC Error Status Enable */ +#define _SDIO_IFENC_CMDCRCERREN_SHIFT 17 /**< Shift value for SDIO_CMDCRCERREN */ +#define _SDIO_IFENC_CMDCRCERREN_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCERREN */ +#define _SDIO_IFENC_CMDCRCERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CMDCRCERREN_DEFAULT (_SDIO_IFENC_CMDCRCERREN_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CMDENDBITERREN (0x1UL << 18) /**< Command End Bit Error Status Enable */ +#define _SDIO_IFENC_CMDENDBITERREN_SHIFT 18 /**< Shift value for SDIO_CMDENDBITERREN */ +#define _SDIO_IFENC_CMDENDBITERREN_MASK 0x40000UL /**< Bit mask for SDIO_CMDENDBITERREN */ +#define _SDIO_IFENC_CMDENDBITERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CMDENDBITERREN_DEFAULT (_SDIO_IFENC_CMDENDBITERREN_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CMDINDEXERREN (0x1UL << 19) /**< Command Index Error Status Enable */ +#define _SDIO_IFENC_CMDINDEXERREN_SHIFT 19 /**< Shift value for SDIO_CMDINDEXERREN */ +#define _SDIO_IFENC_CMDINDEXERREN_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDEXERREN */ +#define _SDIO_IFENC_CMDINDEXERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CMDINDEXERREN_DEFAULT (_SDIO_IFENC_CMDINDEXERREN_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_DATTOUTERREN (0x1UL << 20) /**< Data Timeout Error Status Enable */ +#define _SDIO_IFENC_DATTOUTERREN_SHIFT 20 /**< Shift value for SDIO_DATTOUTERREN */ +#define _SDIO_IFENC_DATTOUTERREN_MASK 0x100000UL /**< Bit mask for SDIO_DATTOUTERREN */ +#define _SDIO_IFENC_DATTOUTERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_DATTOUTERREN_DEFAULT (_SDIO_IFENC_DATTOUTERREN_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_DATCRCERREN (0x1UL << 21) /**< Data CRC Error Status Enable */ +#define _SDIO_IFENC_DATCRCERREN_SHIFT 21 /**< Shift value for SDIO_DATCRCERREN */ +#define _SDIO_IFENC_DATCRCERREN_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCERREN */ +#define _SDIO_IFENC_DATCRCERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_DATCRCERREN_DEFAULT (_SDIO_IFENC_DATCRCERREN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_DATENDBITERREN (0x1UL << 22) /**< Data End Bit Error Status Enable */ +#define _SDIO_IFENC_DATENDBITERREN_SHIFT 22 /**< Shift value for SDIO_DATENDBITERREN */ +#define _SDIO_IFENC_DATENDBITERREN_MASK 0x400000UL /**< Bit mask for SDIO_DATENDBITERREN */ +#define _SDIO_IFENC_DATENDBITERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_DATENDBITERREN_DEFAULT (_SDIO_IFENC_DATENDBITERREN_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CURRENTLIMITERREN (0x1UL << 23) /**< Current Limit Error Status Enable */ +#define _SDIO_IFENC_CURRENTLIMITERREN_SHIFT 23 /**< Shift value for SDIO_CURRENTLIMITERREN */ +#define _SDIO_IFENC_CURRENTLIMITERREN_MASK 0x800000UL /**< Bit mask for SDIO_CURRENTLIMITERREN */ +#define _SDIO_IFENC_CURRENTLIMITERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_CURRENTLIMITERREN_DEFAULT (_SDIO_IFENC_CURRENTLIMITERREN_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_AUTOCMDERREN (0x1UL << 24) /**< Auto CMD12 Error Status Enable */ +#define _SDIO_IFENC_AUTOCMDERREN_SHIFT 24 /**< Shift value for SDIO_AUTOCMDERREN */ +#define _SDIO_IFENC_AUTOCMDERREN_MASK 0x1000000UL /**< Bit mask for SDIO_AUTOCMDERREN */ +#define _SDIO_IFENC_AUTOCMDERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_AUTOCMDERREN_DEFAULT (_SDIO_IFENC_AUTOCMDERREN_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_ADMAERREN (0x1UL << 25) /**< ADMA Error Status Enable */ +#define _SDIO_IFENC_ADMAERREN_SHIFT 25 /**< Shift value for SDIO_ADMAERREN */ +#define _SDIO_IFENC_ADMAERREN_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAERREN */ +#define _SDIO_IFENC_ADMAERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_ADMAERREN_DEFAULT (_SDIO_IFENC_ADMAERREN_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_TUNINGERREN (0x1UL << 26) /**< Tuning Error Status Enable */ +#define _SDIO_IFENC_TUNINGERREN_SHIFT 26 /**< Shift value for SDIO_TUNINGERREN */ +#define _SDIO_IFENC_TUNINGERREN_MASK 0x4000000UL /**< Bit mask for SDIO_TUNINGERREN */ +#define _SDIO_IFENC_TUNINGERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_TUNINGERREN_DEFAULT (_SDIO_IFENC_TUNINGERREN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_TARGETRESPEN (0x1UL << 28) /**< Target Response/Host Error Status Enable */ +#define _SDIO_IFENC_TARGETRESPEN_SHIFT 28 /**< Shift value for SDIO_TARGETRESPEN */ +#define _SDIO_IFENC_TARGETRESPEN_MASK 0x10000000UL /**< Bit mask for SDIO_TARGETRESPEN */ +#define _SDIO_IFENC_TARGETRESPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */ +#define SDIO_IFENC_TARGETRESPEN_DEFAULT (_SDIO_IFENC_TARGETRESPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_IFENC */ + +/* Bit fields for SDIO IEN */ +#define _SDIO_IEN_RESETVALUE 0x00000000UL /**< Default value for SDIO_IEN */ +#define _SDIO_IEN_MASK 0x17FF71FFUL /**< Mask for SDIO_IEN */ +#define SDIO_IEN_CMDCOMSEN (0x1UL << 0) /**< Command Complete Signal Enable */ +#define _SDIO_IEN_CMDCOMSEN_SHIFT 0 /**< Shift value for SDIO_CMDCOMSEN */ +#define _SDIO_IEN_CMDCOMSEN_MASK 0x1UL /**< Bit mask for SDIO_CMDCOMSEN */ +#define _SDIO_IEN_CMDCOMSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CMDCOMSEN_DEFAULT (_SDIO_IEN_CMDCOMSEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_TRANCOMSEN (0x1UL << 1) /**< Transfer Complete Signal Enable */ +#define _SDIO_IEN_TRANCOMSEN_SHIFT 1 /**< Shift value for SDIO_TRANCOMSEN */ +#define _SDIO_IEN_TRANCOMSEN_MASK 0x2UL /**< Bit mask for SDIO_TRANCOMSEN */ +#define _SDIO_IEN_TRANCOMSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_TRANCOMSEN_DEFAULT (_SDIO_IEN_TRANCOMSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_BLKGAPEVTSEN (0x1UL << 2) /**< Block Gap Event Signal Enable */ +#define _SDIO_IEN_BLKGAPEVTSEN_SHIFT 2 /**< Shift value for SDIO_BLKGAPEVTSEN */ +#define _SDIO_IEN_BLKGAPEVTSEN_MASK 0x4UL /**< Bit mask for SDIO_BLKGAPEVTSEN */ +#define _SDIO_IEN_BLKGAPEVTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_BLKGAPEVTSEN_DEFAULT (_SDIO_IEN_BLKGAPEVTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_DMAINTSEN (0x1UL << 3) /**< DMA Interrupt Signal Enable */ +#define _SDIO_IEN_DMAINTSEN_SHIFT 3 /**< Shift value for SDIO_DMAINTSEN */ +#define _SDIO_IEN_DMAINTSEN_MASK 0x8UL /**< Bit mask for SDIO_DMAINTSEN */ +#define _SDIO_IEN_DMAINTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_DMAINTSEN_DEFAULT (_SDIO_IEN_DMAINTSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_BUFWRRDYSEN (0x1UL << 4) /**< Buffer Write Ready Signal Enable */ +#define _SDIO_IEN_BUFWRRDYSEN_SHIFT 4 /**< Shift value for SDIO_BUFWRRDYSEN */ +#define _SDIO_IEN_BUFWRRDYSEN_MASK 0x10UL /**< Bit mask for SDIO_BUFWRRDYSEN */ +#define _SDIO_IEN_BUFWRRDYSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_BUFWRRDYSEN_DEFAULT (_SDIO_IEN_BUFWRRDYSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_BUFRDRDYSEN (0x1UL << 5) /**< Buffer Read Ready Signal Enable */ +#define _SDIO_IEN_BUFRDRDYSEN_SHIFT 5 /**< Shift value for SDIO_BUFRDRDYSEN */ +#define _SDIO_IEN_BUFRDRDYSEN_MASK 0x20UL /**< Bit mask for SDIO_BUFRDRDYSEN */ +#define _SDIO_IEN_BUFRDRDYSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_BUFRDRDYSEN_DEFAULT (_SDIO_IEN_BUFRDRDYSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CARDINSSEN (0x1UL << 6) /**< Card Insertion Signal Enable */ +#define _SDIO_IEN_CARDINSSEN_SHIFT 6 /**< Shift value for SDIO_CARDINSSEN */ +#define _SDIO_IEN_CARDINSSEN_MASK 0x40UL /**< Bit mask for SDIO_CARDINSSEN */ +#define _SDIO_IEN_CARDINSSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CARDINSSEN_DEFAULT (_SDIO_IEN_CARDINSSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CARDREMSEN (0x1UL << 7) /**< Card Removal Signal Enable */ +#define _SDIO_IEN_CARDREMSEN_SHIFT 7 /**< Shift value for SDIO_CARDREMSEN */ +#define _SDIO_IEN_CARDREMSEN_MASK 0x80UL /**< Bit mask for SDIO_CARDREMSEN */ +#define _SDIO_IEN_CARDREMSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CARDREMSEN_DEFAULT (_SDIO_IEN_CARDREMSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CARDINTSEN (0x1UL << 8) /**< Card Interrupt Signal Enable */ +#define _SDIO_IEN_CARDINTSEN_SHIFT 8 /**< Shift value for SDIO_CARDINTSEN */ +#define _SDIO_IEN_CARDINTSEN_MASK 0x100UL /**< Bit mask for SDIO_CARDINTSEN */ +#define _SDIO_IEN_CARDINTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CARDINTSEN_DEFAULT (_SDIO_IEN_CARDINTSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_RETUNINGEVTSEN (0x1UL << 12) /**< Re-Tuning Event Signal Enable */ +#define _SDIO_IEN_RETUNINGEVTSEN_SHIFT 12 /**< Shift value for SDIO_RETUNINGEVTSEN */ +#define _SDIO_IEN_RETUNINGEVTSEN_MASK 0x1000UL /**< Bit mask for SDIO_RETUNINGEVTSEN */ +#define _SDIO_IEN_RETUNINGEVTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_RETUNINGEVTSEN_DEFAULT (_SDIO_IEN_RETUNINGEVTSEN_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_BOOTACKRCVSEN (0x1UL << 13) /**< Boot Ack Received Signal Enable */ +#define _SDIO_IEN_BOOTACKRCVSEN_SHIFT 13 /**< Shift value for SDIO_BOOTACKRCVSEN */ +#define _SDIO_IEN_BOOTACKRCVSEN_MASK 0x2000UL /**< Bit mask for SDIO_BOOTACKRCVSEN */ +#define _SDIO_IEN_BOOTACKRCVSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_BOOTACKRCVSEN_DEFAULT (_SDIO_IEN_BOOTACKRCVSEN_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_BOOTTERMINATESEN (0x1UL << 14) /**< Boot Terminate Interrupt Signal Enable */ +#define _SDIO_IEN_BOOTTERMINATESEN_SHIFT 14 /**< Shift value for SDIO_BOOTTERMINATESEN */ +#define _SDIO_IEN_BOOTTERMINATESEN_MASK 0x4000UL /**< Bit mask for SDIO_BOOTTERMINATESEN */ +#define _SDIO_IEN_BOOTTERMINATESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_BOOTTERMINATESEN_DEFAULT (_SDIO_IEN_BOOTTERMINATESEN_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CMDTOUTERRSEN (0x1UL << 16) /**< Command Timeout Error Signal Enable */ +#define _SDIO_IEN_CMDTOUTERRSEN_SHIFT 16 /**< Shift value for SDIO_CMDTOUTERRSEN */ +#define _SDIO_IEN_CMDTOUTERRSEN_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOUTERRSEN */ +#define _SDIO_IEN_CMDTOUTERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CMDTOUTERRSEN_DEFAULT (_SDIO_IEN_CMDTOUTERRSEN_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CMDCRCERRSEN (0x1UL << 17) /**< Command CRC Error Signal Enable */ +#define _SDIO_IEN_CMDCRCERRSEN_SHIFT 17 /**< Shift value for SDIO_CMDCRCERRSEN */ +#define _SDIO_IEN_CMDCRCERRSEN_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCERRSEN */ +#define _SDIO_IEN_CMDCRCERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CMDCRCERRSEN_DEFAULT (_SDIO_IEN_CMDCRCERRSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CMDENDBITERRSEN (0x1UL << 18) /**< Command End Bit Error Signal Enable */ +#define _SDIO_IEN_CMDENDBITERRSEN_SHIFT 18 /**< Shift value for SDIO_CMDENDBITERRSEN */ +#define _SDIO_IEN_CMDENDBITERRSEN_MASK 0x40000UL /**< Bit mask for SDIO_CMDENDBITERRSEN */ +#define _SDIO_IEN_CMDENDBITERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CMDENDBITERRSEN_DEFAULT (_SDIO_IEN_CMDENDBITERRSEN_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CMDINDEXERRSEN (0x1UL << 19) /**< Command Index Error Signal Enable */ +#define _SDIO_IEN_CMDINDEXERRSEN_SHIFT 19 /**< Shift value for SDIO_CMDINDEXERRSEN */ +#define _SDIO_IEN_CMDINDEXERRSEN_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDEXERRSEN */ +#define _SDIO_IEN_CMDINDEXERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CMDINDEXERRSEN_DEFAULT (_SDIO_IEN_CMDINDEXERRSEN_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_DATTOUTERRSEN (0x1UL << 20) /**< Data Timeout Error Signal Enable */ +#define _SDIO_IEN_DATTOUTERRSEN_SHIFT 20 /**< Shift value for SDIO_DATTOUTERRSEN */ +#define _SDIO_IEN_DATTOUTERRSEN_MASK 0x100000UL /**< Bit mask for SDIO_DATTOUTERRSEN */ +#define _SDIO_IEN_DATTOUTERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_DATTOUTERRSEN_DEFAULT (_SDIO_IEN_DATTOUTERRSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_DATCRCERRSEN (0x1UL << 21) /**< Data CRC Error Signal Enable */ +#define _SDIO_IEN_DATCRCERRSEN_SHIFT 21 /**< Shift value for SDIO_DATCRCERRSEN */ +#define _SDIO_IEN_DATCRCERRSEN_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCERRSEN */ +#define _SDIO_IEN_DATCRCERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_DATCRCERRSEN_DEFAULT (_SDIO_IEN_DATCRCERRSEN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_DATENDBITERRSEN (0x1UL << 22) /**< Data End Bit Error Signal Enable */ +#define _SDIO_IEN_DATENDBITERRSEN_SHIFT 22 /**< Shift value for SDIO_DATENDBITERRSEN */ +#define _SDIO_IEN_DATENDBITERRSEN_MASK 0x400000UL /**< Bit mask for SDIO_DATENDBITERRSEN */ +#define _SDIO_IEN_DATENDBITERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_DATENDBITERRSEN_DEFAULT (_SDIO_IEN_DATENDBITERRSEN_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CURRENTLIMITERRSEN (0x1UL << 23) /**< Current Limit Error Signal Enable */ +#define _SDIO_IEN_CURRENTLIMITERRSEN_SHIFT 23 /**< Shift value for SDIO_CURRENTLIMITERRSEN */ +#define _SDIO_IEN_CURRENTLIMITERRSEN_MASK 0x800000UL /**< Bit mask for SDIO_CURRENTLIMITERRSEN */ +#define _SDIO_IEN_CURRENTLIMITERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_CURRENTLIMITERRSEN_DEFAULT (_SDIO_IEN_CURRENTLIMITERRSEN_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_AUTOCMDERRSEN (0x1UL << 24) /**< Auto CMD12 Error Signal Enable */ +#define _SDIO_IEN_AUTOCMDERRSEN_SHIFT 24 /**< Shift value for SDIO_AUTOCMDERRSEN */ +#define _SDIO_IEN_AUTOCMDERRSEN_MASK 0x1000000UL /**< Bit mask for SDIO_AUTOCMDERRSEN */ +#define _SDIO_IEN_AUTOCMDERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_AUTOCMDERRSEN_DEFAULT (_SDIO_IEN_AUTOCMDERRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_ADMAERRSEN (0x1UL << 25) /**< ADMA Error Signal Enable */ +#define _SDIO_IEN_ADMAERRSEN_SHIFT 25 /**< Shift value for SDIO_ADMAERRSEN */ +#define _SDIO_IEN_ADMAERRSEN_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAERRSEN */ +#define _SDIO_IEN_ADMAERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_ADMAERRSEN_DEFAULT (_SDIO_IEN_ADMAERRSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_TUNINGERRSIGNALENABLE (0x1UL << 26) /**< Tuning Error Signal Enable */ +#define _SDIO_IEN_TUNINGERRSIGNALENABLE_SHIFT 26 /**< Shift value for SDIO_TUNINGERRSIGNALENABLE */ +#define _SDIO_IEN_TUNINGERRSIGNALENABLE_MASK 0x4000000UL /**< Bit mask for SDIO_TUNINGERRSIGNALENABLE */ +#define _SDIO_IEN_TUNINGERRSIGNALENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_TUNINGERRSIGNALENABLE_DEFAULT (_SDIO_IEN_TUNINGERRSIGNALENABLE_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_TARGETRESPERRSEN (0x1UL << 28) /**< Target Response Error Signal Enable */ +#define _SDIO_IEN_TARGETRESPERRSEN_SHIFT 28 /**< Shift value for SDIO_TARGETRESPERRSEN */ +#define _SDIO_IEN_TARGETRESPERRSEN_MASK 0x10000000UL /**< Bit mask for SDIO_TARGETRESPERRSEN */ +#define _SDIO_IEN_TARGETRESPERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */ +#define SDIO_IEN_TARGETRESPERRSEN_DEFAULT (_SDIO_IEN_TARGETRESPERRSEN_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_IEN */ + +/* Bit fields for SDIO AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_RESETVALUE 0x00000000UL /**< Default value for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_MASK 0xC0FF009FUL /**< Mask for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_AC12NOTEXE (0x1UL << 0) /**< Auto CMD12 Not Executed */ +#define _SDIO_AC12ERRSTAT_AC12NOTEXE_SHIFT 0 /**< Shift value for SDIO_AC12NOTEXE */ +#define _SDIO_AC12ERRSTAT_AC12NOTEXE_MASK 0x1UL /**< Bit mask for SDIO_AC12NOTEXE */ +#define _SDIO_AC12ERRSTAT_AC12NOTEXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_AC12NOTEXE_DEFAULT (_SDIO_AC12ERRSTAT_AC12NOTEXE_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_AC12TOE (0x1UL << 1) /**< Auto CMD12 Timeout Error */ +#define _SDIO_AC12ERRSTAT_AC12TOE_SHIFT 1 /**< Shift value for SDIO_AC12TOE */ +#define _SDIO_AC12ERRSTAT_AC12TOE_MASK 0x2UL /**< Bit mask for SDIO_AC12TOE */ +#define _SDIO_AC12ERRSTAT_AC12TOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_AC12TOE_DEFAULT (_SDIO_AC12ERRSTAT_AC12TOE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_AC12CRCERR (0x1UL << 2) /**< Auto CMD CRC Error */ +#define _SDIO_AC12ERRSTAT_AC12CRCERR_SHIFT 2 /**< Shift value for SDIO_AC12CRCERR */ +#define _SDIO_AC12ERRSTAT_AC12CRCERR_MASK 0x4UL /**< Bit mask for SDIO_AC12CRCERR */ +#define _SDIO_AC12ERRSTAT_AC12CRCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_AC12CRCERR_DEFAULT (_SDIO_AC12ERRSTAT_AC12CRCERR_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_AC12ENDBITERR (0x1UL << 3) /**< Auto CMD End Bit Error */ +#define _SDIO_AC12ERRSTAT_AC12ENDBITERR_SHIFT 3 /**< Shift value for SDIO_AC12ENDBITERR */ +#define _SDIO_AC12ERRSTAT_AC12ENDBITERR_MASK 0x8UL /**< Bit mask for SDIO_AC12ENDBITERR */ +#define _SDIO_AC12ERRSTAT_AC12ENDBITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_AC12ENDBITERR_DEFAULT (_SDIO_AC12ERRSTAT_AC12ENDBITERR_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_AC12INDEXERR (0x1UL << 4) /**< Auto CMD Index Error */ +#define _SDIO_AC12ERRSTAT_AC12INDEXERR_SHIFT 4 /**< Shift value for SDIO_AC12INDEXERR */ +#define _SDIO_AC12ERRSTAT_AC12INDEXERR_MASK 0x10UL /**< Bit mask for SDIO_AC12INDEXERR */ +#define _SDIO_AC12ERRSTAT_AC12INDEXERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_AC12INDEXERR_DEFAULT (_SDIO_AC12ERRSTAT_AC12INDEXERR_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_CNIBAC12ERR (0x1UL << 7) /**< Command Not Issued By Auto CMD12 Error */ +#define _SDIO_AC12ERRSTAT_CNIBAC12ERR_SHIFT 7 /**< Shift value for SDIO_CNIBAC12ERR */ +#define _SDIO_AC12ERRSTAT_CNIBAC12ERR_MASK 0x80UL /**< Bit mask for SDIO_CNIBAC12ERR */ +#define _SDIO_AC12ERRSTAT_CNIBAC12ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_CNIBAC12ERR_DEFAULT (_SDIO_AC12ERRSTAT_CNIBAC12ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_UHSMODESEL_SHIFT 16 /**< Shift value for SDIO_UHSMODESEL */ +#define _SDIO_AC12ERRSTAT_UHSMODESEL_MASK 0x70000UL /**< Bit mask for SDIO_UHSMODESEL */ +#define _SDIO_AC12ERRSTAT_UHSMODESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR12 0x00000000UL /**< Mode SDR12 for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR25 0x00000001UL /**< Mode SDR25 for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR50 0x00000002UL /**< Mode SDR50 for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR104 0x00000003UL /**< Mode SDR104 for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_UHSMODESEL_DDR50 0x00000004UL /**< Mode DDR50 for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_UHSMODESEL_DEFAULT (_SDIO_AC12ERRSTAT_UHSMODESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_UHSMODESEL_SDR12 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR12 << 16) /**< Shifted mode SDR12 for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_UHSMODESEL_SDR25 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR25 << 16) /**< Shifted mode SDR25 for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_UHSMODESEL_SDR50 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR50 << 16) /**< Shifted mode SDR50 for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_UHSMODESEL_SDR104 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR104 << 16) /**< Shifted mode SDR104 for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_UHSMODESEL_DDR50 (_SDIO_AC12ERRSTAT_UHSMODESEL_DDR50 << 16) /**< Shifted mode DDR50 for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_SIGEN1P8V (0x1UL << 19) /**< Voltage 1.8V Signal Enable */ +#define _SDIO_AC12ERRSTAT_SIGEN1P8V_SHIFT 19 /**< Shift value for SDIO_SIGEN1P8V */ +#define _SDIO_AC12ERRSTAT_SIGEN1P8V_MASK 0x80000UL /**< Bit mask for SDIO_SIGEN1P8V */ +#define _SDIO_AC12ERRSTAT_SIGEN1P8V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_SIGEN1P8V_DEFAULT (_SDIO_AC12ERRSTAT_SIGEN1P8V_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_DRVSTNSEL_SHIFT 20 /**< Shift value for SDIO_DRVSTNSEL */ +#define _SDIO_AC12ERRSTAT_DRVSTNSEL_MASK 0x300000UL /**< Bit mask for SDIO_DRVSTNSEL */ +#define _SDIO_AC12ERRSTAT_DRVSTNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_AC12ERRSTAT */ +#define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_DRVSTNSEL_DEFAULT (_SDIO_AC12ERRSTAT_DRVSTNSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEB (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEB << 20) /**< Shifted mode TYPEB for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEA (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEA << 20) /**< Shifted mode TYPEA for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEC (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEC << 20) /**< Shifted mode TYPEC for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPED (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPED << 20) /**< Shifted mode TYPED for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_EXETUNING (0x1UL << 22) /**< Execute Tuning */ +#define _SDIO_AC12ERRSTAT_EXETUNING_SHIFT 22 /**< Shift value for SDIO_EXETUNING */ +#define _SDIO_AC12ERRSTAT_EXETUNING_MASK 0x400000UL /**< Bit mask for SDIO_EXETUNING */ +#define _SDIO_AC12ERRSTAT_EXETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_EXETUNING_DEFAULT (_SDIO_AC12ERRSTAT_EXETUNING_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_SAMPCLKSEL (0x1UL << 23) /**< Sampling Clock Select */ +#define _SDIO_AC12ERRSTAT_SAMPCLKSEL_SHIFT 23 /**< Shift value for SDIO_SAMPCLKSEL */ +#define _SDIO_AC12ERRSTAT_SAMPCLKSEL_MASK 0x800000UL /**< Bit mask for SDIO_SAMPCLKSEL */ +#define _SDIO_AC12ERRSTAT_SAMPCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_SAMPCLKSEL_DEFAULT (_SDIO_AC12ERRSTAT_SAMPCLKSEL_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_ASYNCINTEN (0x1UL << 30) /**< Asynchronous Interrupt Enable */ +#define _SDIO_AC12ERRSTAT_ASYNCINTEN_SHIFT 30 /**< Shift value for SDIO_ASYNCINTEN */ +#define _SDIO_AC12ERRSTAT_ASYNCINTEN_MASK 0x40000000UL /**< Bit mask for SDIO_ASYNCINTEN */ +#define _SDIO_AC12ERRSTAT_ASYNCINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_ASYNCINTEN_DEFAULT (_SDIO_AC12ERRSTAT_ASYNCINTEN_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_PRSTVALEN (0x1UL << 31) /**< Preset Value Enable */ +#define _SDIO_AC12ERRSTAT_PRSTVALEN_SHIFT 31 /**< Shift value for SDIO_PRSTVALEN */ +#define _SDIO_AC12ERRSTAT_PRSTVALEN_MASK 0x80000000UL /**< Bit mask for SDIO_PRSTVALEN */ +#define _SDIO_AC12ERRSTAT_PRSTVALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */ +#define SDIO_AC12ERRSTAT_PRSTVALEN_DEFAULT (_SDIO_AC12ERRSTAT_PRSTVALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */ + +/* Bit fields for SDIO CAPAB0 */ +#define _SDIO_CAPAB0_RESETVALUE 0x00000000UL /**< Default value for SDIO_CAPAB0 */ +#define _SDIO_CAPAB0_MASK 0xF7EFFFBFUL /**< Mask for SDIO_CAPAB0 */ +#define _SDIO_CAPAB0_TMOUTCLKFREQ_SHIFT 0 /**< Shift value for SDIO_TMOUTCLKFREQ */ +#define _SDIO_CAPAB0_TMOUTCLKFREQ_MASK 0x3FUL /**< Bit mask for SDIO_TMOUTCLKFREQ */ +#define _SDIO_CAPAB0_TMOUTCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_TMOUTCLKFREQ_DEFAULT (_SDIO_CAPAB0_TMOUTCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_TMOUTCLKUNIT (0x1UL << 7) /**< Timeout Clock Unit */ +#define _SDIO_CAPAB0_TMOUTCLKUNIT_SHIFT 7 /**< Shift value for SDIO_TMOUTCLKUNIT */ +#define _SDIO_CAPAB0_TMOUTCLKUNIT_MASK 0x80UL /**< Bit mask for SDIO_TMOUTCLKUNIT */ +#define _SDIO_CAPAB0_TMOUTCLKUNIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_TMOUTCLKUNIT_DEFAULT (_SDIO_CAPAB0_TMOUTCLKUNIT_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define _SDIO_CAPAB0_BASECLKFREQSD_SHIFT 8 /**< Shift value for SDIO_BASECLKFREQSD */ +#define _SDIO_CAPAB0_BASECLKFREQSD_MASK 0xFF00UL /**< Bit mask for SDIO_BASECLKFREQSD */ +#define _SDIO_CAPAB0_BASECLKFREQSD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_BASECLKFREQSD_DEFAULT (_SDIO_CAPAB0_BASECLKFREQSD_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define _SDIO_CAPAB0_MAXBLOCKLEN_SHIFT 16 /**< Shift value for SDIO_MAXBLOCKLEN */ +#define _SDIO_CAPAB0_MAXBLOCKLEN_MASK 0x30000UL /**< Bit mask for SDIO_MAXBLOCKLEN */ +#define _SDIO_CAPAB0_MAXBLOCKLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_MAXBLOCKLEN_DEFAULT (_SDIO_CAPAB0_MAXBLOCKLEN_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_EXTMEDIABUSSUP (0x1UL << 18) /**< Extended Media Bus Support */ +#define _SDIO_CAPAB0_EXTMEDIABUSSUP_SHIFT 18 /**< Shift value for SDIO_EXTMEDIABUSSUP */ +#define _SDIO_CAPAB0_EXTMEDIABUSSUP_MASK 0x40000UL /**< Bit mask for SDIO_EXTMEDIABUSSUP */ +#define _SDIO_CAPAB0_EXTMEDIABUSSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_EXTMEDIABUSSUP_DEFAULT (_SDIO_CAPAB0_EXTMEDIABUSSUP_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_ADMA2SUP (0x1UL << 19) /**< ADMA2 Support */ +#define _SDIO_CAPAB0_ADMA2SUP_SHIFT 19 /**< Shift value for SDIO_ADMA2SUP */ +#define _SDIO_CAPAB0_ADMA2SUP_MASK 0x80000UL /**< Bit mask for SDIO_ADMA2SUP */ +#define _SDIO_CAPAB0_ADMA2SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_ADMA2SUP_DEFAULT (_SDIO_CAPAB0_ADMA2SUP_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_HSSUP (0x1UL << 21) /**< High Speed Support */ +#define _SDIO_CAPAB0_HSSUP_SHIFT 21 /**< Shift value for SDIO_HSSUP */ +#define _SDIO_CAPAB0_HSSUP_MASK 0x200000UL /**< Bit mask for SDIO_HSSUP */ +#define _SDIO_CAPAB0_HSSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_HSSUP_DEFAULT (_SDIO_CAPAB0_HSSUP_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_SDMASUP (0x1UL << 22) /**< SDMA Support */ +#define _SDIO_CAPAB0_SDMASUP_SHIFT 22 /**< Shift value for SDIO_SDMASUP */ +#define _SDIO_CAPAB0_SDMASUP_MASK 0x400000UL /**< Bit mask for SDIO_SDMASUP */ +#define _SDIO_CAPAB0_SDMASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_SDMASUP_DEFAULT (_SDIO_CAPAB0_SDMASUP_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_SUSRESSUP (0x1UL << 23) /**< Suspend / Resume Support */ +#define _SDIO_CAPAB0_SUSRESSUP_SHIFT 23 /**< Shift value for SDIO_SUSRESSUP */ +#define _SDIO_CAPAB0_SUSRESSUP_MASK 0x800000UL /**< Bit mask for SDIO_SUSRESSUP */ +#define _SDIO_CAPAB0_SUSRESSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_SUSRESSUP_DEFAULT (_SDIO_CAPAB0_SUSRESSUP_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_VOLTSUP3P3V (0x1UL << 24) /**< Voltage Support 3.3V */ +#define _SDIO_CAPAB0_VOLTSUP3P3V_SHIFT 24 /**< Shift value for SDIO_VOLTSUP3P3V */ +#define _SDIO_CAPAB0_VOLTSUP3P3V_MASK 0x1000000UL /**< Bit mask for SDIO_VOLTSUP3P3V */ +#define _SDIO_CAPAB0_VOLTSUP3P3V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_VOLTSUP3P3V_DEFAULT (_SDIO_CAPAB0_VOLTSUP3P3V_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_VOLTSUP3P0V (0x1UL << 25) /**< Voltage Support 3.0V */ +#define _SDIO_CAPAB0_VOLTSUP3P0V_SHIFT 25 /**< Shift value for SDIO_VOLTSUP3P0V */ +#define _SDIO_CAPAB0_VOLTSUP3P0V_MASK 0x2000000UL /**< Bit mask for SDIO_VOLTSUP3P0V */ +#define _SDIO_CAPAB0_VOLTSUP3P0V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_VOLTSUP3P0V_DEFAULT (_SDIO_CAPAB0_VOLTSUP3P0V_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_VOLTSUP1P8V (0x1UL << 26) /**< Voltage Support 1.8V */ +#define _SDIO_CAPAB0_VOLTSUP1P8V_SHIFT 26 /**< Shift value for SDIO_VOLTSUP1P8V */ +#define _SDIO_CAPAB0_VOLTSUP1P8V_MASK 0x4000000UL /**< Bit mask for SDIO_VOLTSUP1P8V */ +#define _SDIO_CAPAB0_VOLTSUP1P8V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_VOLTSUP1P8V_DEFAULT (_SDIO_CAPAB0_VOLTSUP1P8V_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_SYSBUS64BSUP (0x1UL << 28) /**< System Bus 64-bit Support */ +#define _SDIO_CAPAB0_SYSBUS64BSUP_SHIFT 28 /**< Shift value for SDIO_SYSBUS64BSUP */ +#define _SDIO_CAPAB0_SYSBUS64BSUP_MASK 0x10000000UL /**< Bit mask for SDIO_SYSBUS64BSUP */ +#define _SDIO_CAPAB0_SYSBUS64BSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_SYSBUS64BSUP_DEFAULT (_SDIO_CAPAB0_SYSBUS64BSUP_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_ASYNCINTSUP (0x1UL << 29) /**< Asynchronous Interrupt Support */ +#define _SDIO_CAPAB0_ASYNCINTSUP_SHIFT 29 /**< Shift value for SDIO_ASYNCINTSUP */ +#define _SDIO_CAPAB0_ASYNCINTSUP_MASK 0x20000000UL /**< Bit mask for SDIO_ASYNCINTSUP */ +#define _SDIO_CAPAB0_ASYNCINTSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_ASYNCINTSUP_DEFAULT (_SDIO_CAPAB0_ASYNCINTSUP_DEFAULT << 29) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define _SDIO_CAPAB0_IFSLOTTYPE_SHIFT 30 /**< Shift value for SDIO_IFSLOTTYPE */ +#define _SDIO_CAPAB0_IFSLOTTYPE_MASK 0xC0000000UL /**< Bit mask for SDIO_IFSLOTTYPE */ +#define _SDIO_CAPAB0_IFSLOTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */ +#define _SDIO_CAPAB0_IFSLOTTYPE_REMOVABLE 0x00000000UL /**< Mode REMOVABLE for SDIO_CAPAB0 */ +#define _SDIO_CAPAB0_IFSLOTTYPE_EMBEDDED 0x00000001UL /**< Mode EMBEDDED for SDIO_CAPAB0 */ +#define _SDIO_CAPAB0_IFSLOTTYPE_SHARED 0x00000002UL /**< Mode SHARED for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_IFSLOTTYPE_DEFAULT (_SDIO_CAPAB0_IFSLOTTYPE_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_IFSLOTTYPE_REMOVABLE (_SDIO_CAPAB0_IFSLOTTYPE_REMOVABLE << 30) /**< Shifted mode REMOVABLE for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_IFSLOTTYPE_EMBEDDED (_SDIO_CAPAB0_IFSLOTTYPE_EMBEDDED << 30) /**< Shifted mode EMBEDDED for SDIO_CAPAB0 */ +#define SDIO_CAPAB0_IFSLOTTYPE_SHARED (_SDIO_CAPAB0_IFSLOTTYPE_SHARED << 30) /**< Shifted mode SHARED for SDIO_CAPAB0 */ + +/* Bit fields for SDIO CAPAB2 */ +#define _SDIO_CAPAB2_RESETVALUE 0x00000000UL /**< Default value for SDIO_CAPAB2 */ +#define _SDIO_CAPAB2_MASK 0x03FFEF77UL /**< Mask for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_SDR50SUP (0x1UL << 0) /**< SDR50 Support */ +#define _SDIO_CAPAB2_SDR50SUP_SHIFT 0 /**< Shift value for SDIO_SDR50SUP */ +#define _SDIO_CAPAB2_SDR50SUP_MASK 0x1UL /**< Bit mask for SDIO_SDR50SUP */ +#define _SDIO_CAPAB2_SDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_SDR50SUP_DEFAULT (_SDIO_CAPAB2_SDR50SUP_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_SDR104SUP (0x1UL << 1) /**< SDR104 Support */ +#define _SDIO_CAPAB2_SDR104SUP_SHIFT 1 /**< Shift value for SDIO_SDR104SUP */ +#define _SDIO_CAPAB2_SDR104SUP_MASK 0x2UL /**< Bit mask for SDIO_SDR104SUP */ +#define _SDIO_CAPAB2_SDR104SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_SDR104SUP_DEFAULT (_SDIO_CAPAB2_SDR104SUP_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_DDR50SUP (0x1UL << 2) /**< DDR50 Support */ +#define _SDIO_CAPAB2_DDR50SUP_SHIFT 2 /**< Shift value for SDIO_DDR50SUP */ +#define _SDIO_CAPAB2_DDR50SUP_MASK 0x4UL /**< Bit mask for SDIO_DDR50SUP */ +#define _SDIO_CAPAB2_DDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_DDR50SUP_DEFAULT (_SDIO_CAPAB2_DDR50SUP_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_DRVTYPASUP (0x1UL << 4) /**< Driver Type a Support */ +#define _SDIO_CAPAB2_DRVTYPASUP_SHIFT 4 /**< Shift value for SDIO_DRVTYPASUP */ +#define _SDIO_CAPAB2_DRVTYPASUP_MASK 0x10UL /**< Bit mask for SDIO_DRVTYPASUP */ +#define _SDIO_CAPAB2_DRVTYPASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_DRVTYPASUP_DEFAULT (_SDIO_CAPAB2_DRVTYPASUP_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_DRVTYPCSUP (0x1UL << 5) /**< Driver Type C Support */ +#define _SDIO_CAPAB2_DRVTYPCSUP_SHIFT 5 /**< Shift value for SDIO_DRVTYPCSUP */ +#define _SDIO_CAPAB2_DRVTYPCSUP_MASK 0x20UL /**< Bit mask for SDIO_DRVTYPCSUP */ +#define _SDIO_CAPAB2_DRVTYPCSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_DRVTYPCSUP_DEFAULT (_SDIO_CAPAB2_DRVTYPCSUP_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_DRVTYPDSUP (0x1UL << 6) /**< Driver Type D Support */ +#define _SDIO_CAPAB2_DRVTYPDSUP_SHIFT 6 /**< Shift value for SDIO_DRVTYPDSUP */ +#define _SDIO_CAPAB2_DRVTYPDSUP_MASK 0x40UL /**< Bit mask for SDIO_DRVTYPDSUP */ +#define _SDIO_CAPAB2_DRVTYPDSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_DRVTYPDSUP_DEFAULT (_SDIO_CAPAB2_DRVTYPDSUP_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ +#define _SDIO_CAPAB2_TIMCNTRETUN_SHIFT 8 /**< Shift value for SDIO_TIMCNTRETUN */ +#define _SDIO_CAPAB2_TIMCNTRETUN_MASK 0xF00UL /**< Bit mask for SDIO_TIMCNTRETUN */ +#define _SDIO_CAPAB2_TIMCNTRETUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_TIMCNTRETUN_DEFAULT (_SDIO_CAPAB2_TIMCNTRETUN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_USETUNSDR50 (0x1UL << 13) /**< Use Tuning for SDR50 */ +#define _SDIO_CAPAB2_USETUNSDR50_SHIFT 13 /**< Shift value for SDIO_USETUNSDR50 */ +#define _SDIO_CAPAB2_USETUNSDR50_MASK 0x2000UL /**< Bit mask for SDIO_USETUNSDR50 */ +#define _SDIO_CAPAB2_USETUNSDR50_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_USETUNSDR50_DEFAULT (_SDIO_CAPAB2_USETUNSDR50_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ +#define _SDIO_CAPAB2_RETUNEMODES_SHIFT 14 /**< Shift value for SDIO_RETUNEMODES */ +#define _SDIO_CAPAB2_RETUNEMODES_MASK 0xC000UL /**< Bit mask for SDIO_RETUNEMODES */ +#define _SDIO_CAPAB2_RETUNEMODES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_RETUNEMODES_DEFAULT (_SDIO_CAPAB2_RETUNEMODES_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ +#define _SDIO_CAPAB2_CLOCKKMUL_SHIFT 16 /**< Shift value for SDIO_CLOCKKMUL */ +#define _SDIO_CAPAB2_CLOCKKMUL_MASK 0xFF0000UL /**< Bit mask for SDIO_CLOCKKMUL */ +#define _SDIO_CAPAB2_CLOCKKMUL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_CLOCKKMUL_DEFAULT (_SDIO_CAPAB2_CLOCKKMUL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_SPIMODE (0x1UL << 24) /**< SPI Mode Support */ +#define _SDIO_CAPAB2_SPIMODE_SHIFT 24 /**< Shift value for SDIO_SPIMODE */ +#define _SDIO_CAPAB2_SPIMODE_MASK 0x1000000UL /**< Bit mask for SDIO_SPIMODE */ +#define _SDIO_CAPAB2_SPIMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_SPIMODE_DEFAULT (_SDIO_CAPAB2_SPIMODE_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_SPIBLOCKMODE (0x1UL << 25) /**< SPI Block Mode Support */ +#define _SDIO_CAPAB2_SPIBLOCKMODE_SHIFT 25 /**< Shift value for SDIO_SPIBLOCKMODE */ +#define _SDIO_CAPAB2_SPIBLOCKMODE_MASK 0x2000000UL /**< Bit mask for SDIO_SPIBLOCKMODE */ +#define _SDIO_CAPAB2_SPIBLOCKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */ +#define SDIO_CAPAB2_SPIBLOCKMODE_DEFAULT (_SDIO_CAPAB2_SPIBLOCKMODE_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */ + +/* Bit fields for SDIO MAXCURCAPAB */ +#define _SDIO_MAXCURCAPAB_RESETVALUE 0x00000000UL /**< Default value for SDIO_MAXCURCAPAB */ +#define _SDIO_MAXCURCAPAB_MASK 0x00FFFFFFUL /**< Mask for SDIO_MAXCURCAPAB */ +#define _SDIO_MAXCURCAPAB_MAXCUR3P3VAL_SHIFT 0 /**< Shift value for SDIO_MAXCUR3P3VAL */ +#define _SDIO_MAXCURCAPAB_MAXCUR3P3VAL_MASK 0xFFUL /**< Bit mask for SDIO_MAXCUR3P3VAL */ +#define _SDIO_MAXCURCAPAB_MAXCUR3P3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_MAXCURCAPAB */ +#define SDIO_MAXCURCAPAB_MAXCUR3P3VAL_DEFAULT (_SDIO_MAXCURCAPAB_MAXCUR3P3VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_MAXCURCAPAB */ +#define _SDIO_MAXCURCAPAB_MAXCUR3P0VAL_SHIFT 8 /**< Shift value for SDIO_MAXCUR3P0VAL */ +#define _SDIO_MAXCURCAPAB_MAXCUR3P0VAL_MASK 0xFF00UL /**< Bit mask for SDIO_MAXCUR3P0VAL */ +#define _SDIO_MAXCURCAPAB_MAXCUR3P0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_MAXCURCAPAB */ +#define SDIO_MAXCURCAPAB_MAXCUR3P0VAL_DEFAULT (_SDIO_MAXCURCAPAB_MAXCUR3P0VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_MAXCURCAPAB */ +#define _SDIO_MAXCURCAPAB_MAXCUR1P8VAL_SHIFT 16 /**< Shift value for SDIO_MAXCUR1P8VAL */ +#define _SDIO_MAXCURCAPAB_MAXCUR1P8VAL_MASK 0xFF0000UL /**< Bit mask for SDIO_MAXCUR1P8VAL */ +#define _SDIO_MAXCURCAPAB_MAXCUR1P8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_MAXCURCAPAB */ +#define SDIO_MAXCURCAPAB_MAXCUR1P8VAL_DEFAULT (_SDIO_MAXCURCAPAB_MAXCUR1P8VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_MAXCURCAPAB */ + +/* Bit fields for SDIO FEVTERRSTAT */ +#define _SDIO_FEVTERRSTAT_RESETVALUE 0x00000000UL /**< Default value for SDIO_FEVTERRSTAT */ +#define _SDIO_FEVTERRSTAT_MASK 0xF7FF009FUL /**< Mask for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12NEX (0x1UL << 0) /**< Force Event for Command Not Issued By Auto CM12 Not Executed */ +#define _SDIO_FEVTERRSTAT_AC12NEX_SHIFT 0 /**< Shift value for SDIO_AC12NEX */ +#define _SDIO_FEVTERRSTAT_AC12NEX_MASK 0x1UL /**< Bit mask for SDIO_AC12NEX */ +#define _SDIO_FEVTERRSTAT_AC12NEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12NEX_DEFAULT (_SDIO_FEVTERRSTAT_AC12NEX_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12TOE (0x1UL << 1) /**< Force Event for Auto CMD Timeout Error */ +#define _SDIO_FEVTERRSTAT_AC12TOE_SHIFT 1 /**< Shift value for SDIO_AC12TOE */ +#define _SDIO_FEVTERRSTAT_AC12TOE_MASK 0x2UL /**< Bit mask for SDIO_AC12TOE */ +#define _SDIO_FEVTERRSTAT_AC12TOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12TOE_DEFAULT (_SDIO_FEVTERRSTAT_AC12TOE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12CRCE (0x1UL << 2) /**< Force Event for Auto CMD CRC Error */ +#define _SDIO_FEVTERRSTAT_AC12CRCE_SHIFT 2 /**< Shift value for SDIO_AC12CRCE */ +#define _SDIO_FEVTERRSTAT_AC12CRCE_MASK 0x4UL /**< Bit mask for SDIO_AC12CRCE */ +#define _SDIO_FEVTERRSTAT_AC12CRCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12CRCE_DEFAULT (_SDIO_FEVTERRSTAT_AC12CRCE_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12EBE (0x1UL << 3) /**< Force Event for Auto CMD End Bit Error */ +#define _SDIO_FEVTERRSTAT_AC12EBE_SHIFT 3 /**< Shift value for SDIO_AC12EBE */ +#define _SDIO_FEVTERRSTAT_AC12EBE_MASK 0x8UL /**< Bit mask for SDIO_AC12EBE */ +#define _SDIO_FEVTERRSTAT_AC12EBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12EBE_DEFAULT (_SDIO_FEVTERRSTAT_AC12EBE_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12INDXE (0x1UL << 4) /**< Force Event for Auto CMD Index Error */ +#define _SDIO_FEVTERRSTAT_AC12INDXE_SHIFT 4 /**< Shift value for SDIO_AC12INDXE */ +#define _SDIO_FEVTERRSTAT_AC12INDXE_MASK 0x10UL /**< Bit mask for SDIO_AC12INDXE */ +#define _SDIO_FEVTERRSTAT_AC12INDXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12INDXE_DEFAULT (_SDIO_FEVTERRSTAT_AC12INDXE_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CNIBAC12E (0x1UL << 7) /**< Force Event for Command Not Issued By Auto CMD12 Error */ +#define _SDIO_FEVTERRSTAT_CNIBAC12E_SHIFT 7 /**< Shift value for SDIO_CNIBAC12E */ +#define _SDIO_FEVTERRSTAT_CNIBAC12E_MASK 0x80UL /**< Bit mask for SDIO_CNIBAC12E */ +#define _SDIO_FEVTERRSTAT_CNIBAC12E_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CNIBAC12E_DEFAULT (_SDIO_FEVTERRSTAT_CNIBAC12E_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CMDTOE (0x1UL << 16) /**< Force Event for Command Timeout Error */ +#define _SDIO_FEVTERRSTAT_CMDTOE_SHIFT 16 /**< Shift value for SDIO_CMDTOE */ +#define _SDIO_FEVTERRSTAT_CMDTOE_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOE */ +#define _SDIO_FEVTERRSTAT_CMDTOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CMDTOE_DEFAULT (_SDIO_FEVTERRSTAT_CMDTOE_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CMDCRCE (0x1UL << 17) /**< Force Event for Command CRC Error */ +#define _SDIO_FEVTERRSTAT_CMDCRCE_SHIFT 17 /**< Shift value for SDIO_CMDCRCE */ +#define _SDIO_FEVTERRSTAT_CMDCRCE_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCE */ +#define _SDIO_FEVTERRSTAT_CMDCRCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CMDCRCE_DEFAULT (_SDIO_FEVTERRSTAT_CMDCRCE_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CMDEBE (0x1UL << 18) /**< Force Event for Command End Bit Error */ +#define _SDIO_FEVTERRSTAT_CMDEBE_SHIFT 18 /**< Shift value for SDIO_CMDEBE */ +#define _SDIO_FEVTERRSTAT_CMDEBE_MASK 0x40000UL /**< Bit mask for SDIO_CMDEBE */ +#define _SDIO_FEVTERRSTAT_CMDEBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CMDEBE_DEFAULT (_SDIO_FEVTERRSTAT_CMDEBE_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CMDINDXE (0x1UL << 19) /**< Force Event for Command Index Error */ +#define _SDIO_FEVTERRSTAT_CMDINDXE_SHIFT 19 /**< Shift value for SDIO_CMDINDXE */ +#define _SDIO_FEVTERRSTAT_CMDINDXE_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDXE */ +#define _SDIO_FEVTERRSTAT_CMDINDXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CMDINDXE_DEFAULT (_SDIO_FEVTERRSTAT_CMDINDXE_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_DATTOE (0x1UL << 20) /**< Force Event for Data Timeout Error */ +#define _SDIO_FEVTERRSTAT_DATTOE_SHIFT 20 /**< Shift value for SDIO_DATTOE */ +#define _SDIO_FEVTERRSTAT_DATTOE_MASK 0x100000UL /**< Bit mask for SDIO_DATTOE */ +#define _SDIO_FEVTERRSTAT_DATTOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_DATTOE_DEFAULT (_SDIO_FEVTERRSTAT_DATTOE_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_DATCRCE (0x1UL << 21) /**< Force Event for Data CRC Error */ +#define _SDIO_FEVTERRSTAT_DATCRCE_SHIFT 21 /**< Shift value for SDIO_DATCRCE */ +#define _SDIO_FEVTERRSTAT_DATCRCE_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCE */ +#define _SDIO_FEVTERRSTAT_DATCRCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_DATCRCE_DEFAULT (_SDIO_FEVTERRSTAT_DATCRCE_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_DATEBE (0x1UL << 22) /**< Force Event for Data End Bit Error */ +#define _SDIO_FEVTERRSTAT_DATEBE_SHIFT 22 /**< Shift value for SDIO_DATEBE */ +#define _SDIO_FEVTERRSTAT_DATEBE_MASK 0x400000UL /**< Bit mask for SDIO_DATEBE */ +#define _SDIO_FEVTERRSTAT_DATEBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_DATEBE_DEFAULT (_SDIO_FEVTERRSTAT_DATEBE_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CURLIMITE (0x1UL << 23) /**< Force Event for Current Limit Error */ +#define _SDIO_FEVTERRSTAT_CURLIMITE_SHIFT 23 /**< Shift value for SDIO_CURLIMITE */ +#define _SDIO_FEVTERRSTAT_CURLIMITE_MASK 0x800000UL /**< Bit mask for SDIO_CURLIMITE */ +#define _SDIO_FEVTERRSTAT_CURLIMITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_CURLIMITE_DEFAULT (_SDIO_FEVTERRSTAT_CURLIMITE_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12E (0x1UL << 24) /**< Force Event for Auto CMD Error */ +#define _SDIO_FEVTERRSTAT_AC12E_SHIFT 24 /**< Shift value for SDIO_AC12E */ +#define _SDIO_FEVTERRSTAT_AC12E_MASK 0x1000000UL /**< Bit mask for SDIO_AC12E */ +#define _SDIO_FEVTERRSTAT_AC12E_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_AC12E_DEFAULT (_SDIO_FEVTERRSTAT_AC12E_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_ADMAE (0x1UL << 25) /**< Force Event for ADMA Error */ +#define _SDIO_FEVTERRSTAT_ADMAE_SHIFT 25 /**< Shift value for SDIO_ADMAE */ +#define _SDIO_FEVTERRSTAT_ADMAE_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAE */ +#define _SDIO_FEVTERRSTAT_ADMAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_ADMAE_DEFAULT (_SDIO_FEVTERRSTAT_ADMAE_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_TUNINGE (0x1UL << 26) /**< Force Event for Tuning Errro */ +#define _SDIO_FEVTERRSTAT_TUNINGE_SHIFT 26 /**< Shift value for SDIO_TUNINGE */ +#define _SDIO_FEVTERRSTAT_TUNINGE_MASK 0x4000000UL /**< Bit mask for SDIO_TUNINGE */ +#define _SDIO_FEVTERRSTAT_TUNINGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_TUNINGE_DEFAULT (_SDIO_FEVTERRSTAT_TUNINGE_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ +#define _SDIO_FEVTERRSTAT_VENSPECE_SHIFT 28 /**< Shift value for SDIO_VENSPECE */ +#define _SDIO_FEVTERRSTAT_VENSPECE_MASK 0xF0000000UL /**< Bit mask for SDIO_VENSPECE */ +#define _SDIO_FEVTERRSTAT_VENSPECE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */ +#define SDIO_FEVTERRSTAT_VENSPECE_DEFAULT (_SDIO_FEVTERRSTAT_VENSPECE_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */ + +/* Bit fields for SDIO ADMAES */ +#define _SDIO_ADMAES_RESETVALUE 0x00000000UL /**< Default value for SDIO_ADMAES */ +#define _SDIO_ADMAES_MASK 0x00000007UL /**< Mask for SDIO_ADMAES */ +#define _SDIO_ADMAES_ADMAES_SHIFT 0 /**< Shift value for SDIO_ADMAES */ +#define _SDIO_ADMAES_ADMAES_MASK 0x3UL /**< Bit mask for SDIO_ADMAES */ +#define _SDIO_ADMAES_ADMAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ADMAES */ +#define SDIO_ADMAES_ADMAES_DEFAULT (_SDIO_ADMAES_ADMAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ADMAES */ +#define SDIO_ADMAES_ADMALME (0x1UL << 2) /**< ADMA Length Mismatch Error */ +#define _SDIO_ADMAES_ADMALME_SHIFT 2 /**< Shift value for SDIO_ADMALME */ +#define _SDIO_ADMAES_ADMALME_MASK 0x4UL /**< Bit mask for SDIO_ADMALME */ +#define _SDIO_ADMAES_ADMALME_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ADMAES */ +#define SDIO_ADMAES_ADMALME_DEFAULT (_SDIO_ADMAES_ADMALME_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_ADMAES */ + +/* Bit fields for SDIO ADSADDR */ +#define _SDIO_ADSADDR_RESETVALUE 0x00000000UL /**< Default value for SDIO_ADSADDR */ +#define _SDIO_ADSADDR_MASK 0xFFFFFFFFUL /**< Mask for SDIO_ADSADDR */ +#define _SDIO_ADSADDR_ADSADDR_SHIFT 0 /**< Shift value for SDIO_ADSADDR */ +#define _SDIO_ADSADDR_ADSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_ADSADDR */ +#define _SDIO_ADSADDR_ADSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ADSADDR */ +#define SDIO_ADSADDR_ADSADDR_DEFAULT (_SDIO_ADSADDR_ADSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ADSADDR */ + +/* Bit fields for SDIO PRSTVAL0 */ +#define _SDIO_PRSTVAL0_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_INITSDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_INITSDCLKFREQVAL */ +#define _SDIO_PRSTVAL0_INITSDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_INITSDCLKFREQVAL */ +#define _SDIO_PRSTVAL0_INITSDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_INITSDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL0_INITSDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_INITCLCKGENVAL (0x1UL << 10) /**< Clock Generator Select Value for Initialization */ +#define _SDIO_PRSTVAL0_INITCLCKGENVAL_SHIFT 10 /**< Shift value for SDIO_INITCLCKGENVAL */ +#define _SDIO_PRSTVAL0_INITCLCKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_INITCLCKGENVAL */ +#define _SDIO_PRSTVAL0_INITCLCKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_INITCLCKGENVAL_DEFAULT (_SDIO_PRSTVAL0_INITCLCKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_INITDRVSTVAL_SHIFT 14 /**< Shift value for SDIO_INITDRVSTVAL */ +#define _SDIO_PRSTVAL0_INITDRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_INITDRVSTVAL */ +#define _SDIO_PRSTVAL0_INITDRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_INITDRVSTVAL_DEFAULT (_SDIO_PRSTVAL0_INITDRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_INITDRVSTVAL_TYPEB (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_INITDRVSTVAL_TYPEA (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_INITDRVSTVAL_TYPEC (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_INITDRVSTVAL_TYPED (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_DSPSDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_DSPSDCLKFREQVAL */ +#define _SDIO_PRSTVAL0_DSPSDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_DSPSDCLKFREQVAL */ +#define _SDIO_PRSTVAL0_DSPSDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_DSPSDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL0_DSPSDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_DSPCLKGENVAL (0x1UL << 26) /**< Clock Generator Select Value for Default Speed */ +#define _SDIO_PRSTVAL0_DSPCLKGENVAL_SHIFT 26 /**< Shift value for SDIO_DSPCLKGENVAL */ +#define _SDIO_PRSTVAL0_DSPCLKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_DSPCLKGENVAL */ +#define _SDIO_PRSTVAL0_DSPCLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_DSPCLKGENVAL_DEFAULT (_SDIO_PRSTVAL0_DSPCLKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_DSPDRVSTVAL_SHIFT 30 /**< Shift value for SDIO_DSPDRVSTVAL */ +#define _SDIO_PRSTVAL0_DSPDRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_DSPDRVSTVAL */ +#define _SDIO_PRSTVAL0_DSPDRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL0 */ +#define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_DSPDRVSTVAL_DEFAULT (_SDIO_PRSTVAL0_DSPDRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEB (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEA (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEC (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL0 */ +#define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPED (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL0 */ + +/* Bit fields for SDIO PRSTVAL2 */ +#define _SDIO_PRSTVAL2_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_HSPSDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_HSPSDCLKFREQVAL */ +#define _SDIO_PRSTVAL2_HSPSDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_HSPSDCLKFREQVAL */ +#define _SDIO_PRSTVAL2_HSPSDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_HSPSDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL2_HSPSDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_HSPCLKGENVAL (0x1UL << 10) /**< Clock Generator Select Value for High Speed */ +#define _SDIO_PRSTVAL2_HSPCLKGENVAL_SHIFT 10 /**< Shift value for SDIO_HSPCLKGENVAL */ +#define _SDIO_PRSTVAL2_HSPCLKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_HSPCLKGENVAL */ +#define _SDIO_PRSTVAL2_HSPCLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_HSPCLKGENVAL_DEFAULT (_SDIO_PRSTVAL2_HSPCLKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_HSPDRVSTVAL_SHIFT 14 /**< Shift value for SDIO_HSPDRVSTVAL */ +#define _SDIO_PRSTVAL2_HSPDRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_HSPDRVSTVAL */ +#define _SDIO_PRSTVAL2_HSPDRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_HSPDRVSTVAL_DEFAULT (_SDIO_PRSTVAL2_HSPDRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEB (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEA (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEC (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPED (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_SDR12SDCLKFREQVAL */ +#define _SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR12SDCLKFREQVAL */ +#define _SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_SDR12CLKGENVAL (0x1UL << 26) /**< Clock Generator Select Value for SDR12 */ +#define _SDIO_PRSTVAL2_SDR12CLKGENVAL_SHIFT 26 /**< Shift value for SDIO_SDR12CLKGENVAL */ +#define _SDIO_PRSTVAL2_SDR12CLKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_SDR12CLKGENVAL */ +#define _SDIO_PRSTVAL2_SDR12CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_SDR12CLKGENVAL_DEFAULT (_SDIO_PRSTVAL2_SDR12CLKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_SDR12DRVSTVAL_SHIFT 30 /**< Shift value for SDIO_SDR12DRVSTVAL */ +#define _SDIO_PRSTVAL2_SDR12DRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_SDR12DRVSTVAL */ +#define _SDIO_PRSTVAL2_SDR12DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL2 */ +#define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_SDR12DRVSTVAL_DEFAULT (_SDIO_PRSTVAL2_SDR12DRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEB (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEA (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEC (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL2 */ +#define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPED (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL2 */ + +/* Bit fields for SDIO PRSTVAL4 */ +#define _SDIO_PRSTVAL4_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_SDR25SDCLKFREQVAL */ +#define _SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_SDR25SDCLKFREQVAL */ +#define _SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR25CLKGENVAL (0x1UL << 10) /**< Clock Generator Select Value for SDR25 */ +#define _SDIO_PRSTVAL4_SDR25CLKGENVAL_SHIFT 10 /**< Shift value for SDIO_SDR25CLKGENVAL */ +#define _SDIO_PRSTVAL4_SDR25CLKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_SDR25CLKGENVAL */ +#define _SDIO_PRSTVAL4_SDR25CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR25CLKGENVAL_DEFAULT (_SDIO_PRSTVAL4_SDR25CLKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR25DRVSTVAL_SHIFT 14 /**< Shift value for SDIO_SDR25DRVSTVAL */ +#define _SDIO_PRSTVAL4_SDR25DRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_SDR25DRVSTVAL */ +#define _SDIO_PRSTVAL4_SDR25DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR25DRVSTVAL_DEFAULT (_SDIO_PRSTVAL4_SDR25DRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEB (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEA (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEC (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPED (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_SDR50SDCLKFREQVAL */ +#define _SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR50SDCLKFREQVAL */ +#define _SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR50CLCKGENVAL (0x1UL << 26) /**< Clock Generator Select Value for SDR50 */ +#define _SDIO_PRSTVAL4_SDR50CLCKGENVAL_SHIFT 26 /**< Shift value for SDIO_SDR50CLCKGENVAL */ +#define _SDIO_PRSTVAL4_SDR50CLCKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_SDR50CLCKGENVAL */ +#define _SDIO_PRSTVAL4_SDR50CLCKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR50CLCKGENVAL_DEFAULT (_SDIO_PRSTVAL4_SDR50CLCKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR50DRVSTVAL_SHIFT 30 /**< Shift value for SDIO_SDR50DRVSTVAL */ +#define _SDIO_PRSTVAL4_SDR50DRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_SDR50DRVSTVAL */ +#define _SDIO_PRSTVAL4_SDR50DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL4 */ +#define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR50DRVSTVAL_DEFAULT (_SDIO_PRSTVAL4_SDR50DRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEB (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEA (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEC (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL4 */ +#define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPED (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL4 */ + +/* Bit fields for SDIO PRSTVAL6 */ +#define _SDIO_PRSTVAL6_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_SDR104SDCLKFREQVAL */ +#define _SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_SDR104SDCLKFREQVAL */ +#define _SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_SDR104CLKGENVAL (0x1UL << 10) /**< Clock Generator Select Value for SDR104 */ +#define _SDIO_PRSTVAL6_SDR104CLKGENVAL_SHIFT 10 /**< Shift value for SDIO_SDR104CLKGENVAL */ +#define _SDIO_PRSTVAL6_SDR104CLKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_SDR104CLKGENVAL */ +#define _SDIO_PRSTVAL6_SDR104CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_SDR104CLKGENVAL_DEFAULT (_SDIO_PRSTVAL6_SDR104CLKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_SDR104DRVSTVAL_SHIFT 14 /**< Shift value for SDIO_SDR104DRVSTVAL */ +#define _SDIO_PRSTVAL6_SDR104DRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_SDR104DRVSTVAL */ +#define _SDIO_PRSTVAL6_SDR104DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_SDR104DRVSTVAL_DEFAULT (_SDIO_PRSTVAL6_SDR104DRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEB (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEA (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEC (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPED (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_DDR50SDCLKFREQVAL */ +#define _SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_DDR50SDCLKFREQVAL */ +#define _SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_DDR50CLKGENVAL (0x1UL << 26) /**< Clock Generator Select Value for DDR50 */ +#define _SDIO_PRSTVAL6_DDR50CLKGENVAL_SHIFT 26 /**< Shift value for SDIO_DDR50CLKGENVAL */ +#define _SDIO_PRSTVAL6_DDR50CLKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_DDR50CLKGENVAL */ +#define _SDIO_PRSTVAL6_DDR50CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_DDR50CLKGENVAL_DEFAULT (_SDIO_PRSTVAL6_DDR50CLKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_DDR50DRVSTVAL_SHIFT 30 /**< Shift value for SDIO_DDR50DRVSTVAL */ +#define _SDIO_PRSTVAL6_DDR50DRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_DDR50DRVSTVAL */ +#define _SDIO_PRSTVAL6_DDR50DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL6 */ +#define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_DDR50DRVSTVAL_DEFAULT (_SDIO_PRSTVAL6_DDR50DRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEB (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEA (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEC (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL6 */ +#define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPED (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL6 */ + +/* Bit fields for SDIO BOOTTOCTRL */ +#define _SDIO_BOOTTOCTRL_RESETVALUE 0x00000000UL /**< Default value for SDIO_BOOTTOCTRL */ +#define _SDIO_BOOTTOCTRL_MASK 0xFFFFFFFFUL /**< Mask for SDIO_BOOTTOCTRL */ +#define _SDIO_BOOTTOCTRL_BOOTDATTOCNT_SHIFT 0 /**< Shift value for SDIO_BOOTDATTOCNT */ +#define _SDIO_BOOTTOCTRL_BOOTDATTOCNT_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_BOOTDATTOCNT */ +#define _SDIO_BOOTTOCTRL_BOOTDATTOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BOOTTOCTRL */ +#define SDIO_BOOTTOCTRL_BOOTDATTOCNT_DEFAULT (_SDIO_BOOTTOCTRL_BOOTDATTOCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_BOOTTOCTRL */ + +/* Bit fields for SDIO SLOTINTSTAT */ +#define _SDIO_SLOTINTSTAT_RESETVALUE 0x10020000UL /**< Default value for SDIO_SLOTINTSTAT */ +#define _SDIO_SLOTINTSTAT_MASK 0xFFFF0001UL /**< Mask for SDIO_SLOTINTSTAT */ +#define SDIO_SLOTINTSTAT_INTSLOT0 (0x1UL << 0) /**< Interrupt Signal for Slot#0 */ +#define _SDIO_SLOTINTSTAT_INTSLOT0_SHIFT 0 /**< Shift value for SDIO_INTSLOT0 */ +#define _SDIO_SLOTINTSTAT_INTSLOT0_MASK 0x1UL /**< Bit mask for SDIO_INTSLOT0 */ +#define _SDIO_SLOTINTSTAT_INTSLOT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_SLOTINTSTAT */ +#define SDIO_SLOTINTSTAT_INTSLOT0_DEFAULT (_SDIO_SLOTINTSTAT_INTSLOT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_SLOTINTSTAT */ +#define _SDIO_SLOTINTSTAT_SPECVERNUM_SHIFT 16 /**< Shift value for SDIO_SPECVERNUM */ +#define _SDIO_SLOTINTSTAT_SPECVERNUM_MASK 0xFF0000UL /**< Bit mask for SDIO_SPECVERNUM */ +#define _SDIO_SLOTINTSTAT_SPECVERNUM_DEFAULT 0x00000002UL /**< Mode DEFAULT for SDIO_SLOTINTSTAT */ +#define SDIO_SLOTINTSTAT_SPECVERNUM_DEFAULT (_SDIO_SLOTINTSTAT_SPECVERNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_SLOTINTSTAT */ +#define _SDIO_SLOTINTSTAT_VENDVERNUM_SHIFT 24 /**< Shift value for SDIO_VENDVERNUM */ +#define _SDIO_SLOTINTSTAT_VENDVERNUM_MASK 0xFF000000UL /**< Bit mask for SDIO_VENDVERNUM */ +#define _SDIO_SLOTINTSTAT_VENDVERNUM_DEFAULT 0x00000010UL /**< Mode DEFAULT for SDIO_SLOTINTSTAT */ +#define SDIO_SLOTINTSTAT_VENDVERNUM_DEFAULT (_SDIO_SLOTINTSTAT_VENDVERNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_SLOTINTSTAT */ + +/* Bit fields for SDIO CTRL */ +#define _SDIO_CTRL_RESETVALUE 0x00000000UL /**< Default value for SDIO_CTRL */ +#define _SDIO_CTRL_MASK 0x00030FFFUL /**< Mask for SDIO_CTRL */ +#define SDIO_CTRL_ITAPDLYEN (0x1UL << 0) /**< Selective Tap Delay Line Enable on Rxclk_in */ +#define _SDIO_CTRL_ITAPDLYEN_SHIFT 0 /**< Shift value for SDIO_ITAPDLYEN */ +#define _SDIO_CTRL_ITAPDLYEN_MASK 0x1UL /**< Bit mask for SDIO_ITAPDLYEN */ +#define _SDIO_CTRL_ITAPDLYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ +#define SDIO_CTRL_ITAPDLYEN_DEFAULT (_SDIO_CTRL_ITAPDLYEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CTRL */ +#define _SDIO_CTRL_ITAPDLYSEL_SHIFT 1 /**< Shift value for SDIO_ITAPDLYSEL */ +#define _SDIO_CTRL_ITAPDLYSEL_MASK 0x3EUL /**< Bit mask for SDIO_ITAPDLYSEL */ +#define _SDIO_CTRL_ITAPDLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ +#define SDIO_CTRL_ITAPDLYSEL_DEFAULT (_SDIO_CTRL_ITAPDLYSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CTRL */ +#define SDIO_CTRL_ITAPCHGWIN (0x1UL << 6) /**< Gating Signal for Tap Delay Change */ +#define _SDIO_CTRL_ITAPCHGWIN_SHIFT 6 /**< Shift value for SDIO_ITAPCHGWIN */ +#define _SDIO_CTRL_ITAPCHGWIN_MASK 0x40UL /**< Bit mask for SDIO_ITAPCHGWIN */ +#define _SDIO_CTRL_ITAPCHGWIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ +#define SDIO_CTRL_ITAPCHGWIN_DEFAULT (_SDIO_CTRL_ITAPCHGWIN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CTRL */ +#define SDIO_CTRL_OTAPDLYEN (0x1UL << 7) /**< Selective Tap Delay Line Enable on SDIO_CLK Pin */ +#define _SDIO_CTRL_OTAPDLYEN_SHIFT 7 /**< Shift value for SDIO_OTAPDLYEN */ +#define _SDIO_CTRL_OTAPDLYEN_MASK 0x80UL /**< Bit mask for SDIO_OTAPDLYEN */ +#define _SDIO_CTRL_OTAPDLYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ +#define SDIO_CTRL_OTAPDLYEN_DEFAULT (_SDIO_CTRL_OTAPDLYEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_CTRL */ +#define _SDIO_CTRL_OTAPDLYSEL_SHIFT 8 /**< Shift value for SDIO_OTAPDLYSEL */ +#define _SDIO_CTRL_OTAPDLYSEL_MASK 0xF00UL /**< Bit mask for SDIO_OTAPDLYSEL */ +#define _SDIO_CTRL_OTAPDLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ +#define SDIO_CTRL_OTAPDLYSEL_DEFAULT (_SDIO_CTRL_OTAPDLYSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CTRL */ +#define _SDIO_CTRL_TXDLYMUXSEL_SHIFT 16 /**< Shift value for SDIO_TXDLYMUXSEL */ +#define _SDIO_CTRL_TXDLYMUXSEL_MASK 0x30000UL /**< Bit mask for SDIO_TXDLYMUXSEL */ +#define _SDIO_CTRL_TXDLYMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */ +#define SDIO_CTRL_TXDLYMUXSEL_DEFAULT (_SDIO_CTRL_TXDLYMUXSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CTRL */ + +/* Bit fields for SDIO CFG0 */ +#define _SDIO_CFG0_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFG0 */ +#define _SDIO_CFG0_MASK 0x7FFFFFFFUL /**< Mask for SDIO_CFG0 */ +#define _SDIO_CFG0_TUNINGCNT_SHIFT 0 /**< Shift value for SDIO_TUNINGCNT */ +#define _SDIO_CFG0_TUNINGCNT_MASK 0x3FUL /**< Bit mask for SDIO_TUNINGCNT */ +#define _SDIO_CFG0_TUNINGCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_TUNINGCNT_DEFAULT (_SDIO_CFG0_TUNINGCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define _SDIO_CFG0_TOUTCLKFREQ_SHIFT 6 /**< Shift value for SDIO_TOUTCLKFREQ */ +#define _SDIO_CFG0_TOUTCLKFREQ_MASK 0xFC0UL /**< Bit mask for SDIO_TOUTCLKFREQ */ +#define _SDIO_CFG0_TOUTCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_TOUTCLKFREQ_DEFAULT (_SDIO_CFG0_TOUTCLKFREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_TOUTCLKUNIT (0x1UL << 12) /**< Timeout Clock Unit in kHz or MHz */ +#define _SDIO_CFG0_TOUTCLKUNIT_SHIFT 12 /**< Shift value for SDIO_TOUTCLKUNIT */ +#define _SDIO_CFG0_TOUTCLKUNIT_MASK 0x1000UL /**< Bit mask for SDIO_TOUTCLKUNIT */ +#define _SDIO_CFG0_TOUTCLKUNIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_TOUTCLKUNIT_DEFAULT (_SDIO_CFG0_TOUTCLKUNIT_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define _SDIO_CFG0_BASECLKFREQ_SHIFT 13 /**< Shift value for SDIO_BASECLKFREQ */ +#define _SDIO_CFG0_BASECLKFREQ_MASK 0x1FE000UL /**< Bit mask for SDIO_BASECLKFREQ */ +#define _SDIO_CFG0_BASECLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_BASECLKFREQ_DEFAULT (_SDIO_CFG0_BASECLKFREQ_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define _SDIO_CFG0_MAXBLKLEN_SHIFT 21 /**< Shift value for SDIO_MAXBLKLEN */ +#define _SDIO_CFG0_MAXBLKLEN_MASK 0x600000UL /**< Bit mask for SDIO_MAXBLKLEN */ +#define _SDIO_CFG0_MAXBLKLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define _SDIO_CFG0_MAXBLKLEN_512B 0x00000000UL /**< Mode 512B for SDIO_CFG0 */ +#define _SDIO_CFG0_MAXBLKLEN_1024B 0x00000001UL /**< Mode 1024B for SDIO_CFG0 */ +#define _SDIO_CFG0_MAXBLKLEN_2048B 0x00000002UL /**< Mode 2048B for SDIO_CFG0 */ +#define SDIO_CFG0_MAXBLKLEN_DEFAULT (_SDIO_CFG0_MAXBLKLEN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_MAXBLKLEN_512B (_SDIO_CFG0_MAXBLKLEN_512B << 21) /**< Shifted mode 512B for SDIO_CFG0 */ +#define SDIO_CFG0_MAXBLKLEN_1024B (_SDIO_CFG0_MAXBLKLEN_1024B << 21) /**< Shifted mode 1024B for SDIO_CFG0 */ +#define SDIO_CFG0_MAXBLKLEN_2048B (_SDIO_CFG0_MAXBLKLEN_2048B << 21) /**< Shifted mode 2048B for SDIO_CFG0 */ +#define SDIO_CFG0_C8BITSUP (0x1UL << 23) /**< 8-bit Interface Support */ +#define _SDIO_CFG0_C8BITSUP_SHIFT 23 /**< Shift value for SDIO_C8BITSUP */ +#define _SDIO_CFG0_C8BITSUP_MASK 0x800000UL /**< Bit mask for SDIO_C8BITSUP */ +#define _SDIO_CFG0_C8BITSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_C8BITSUP_DEFAULT (_SDIO_CFG0_C8BITSUP_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_CADMA2SUP (0x1UL << 24) /**< ADMA2 Mode Support */ +#define _SDIO_CFG0_CADMA2SUP_SHIFT 24 /**< Shift value for SDIO_CADMA2SUP */ +#define _SDIO_CFG0_CADMA2SUP_MASK 0x1000000UL /**< Bit mask for SDIO_CADMA2SUP */ +#define _SDIO_CFG0_CADMA2SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_CADMA2SUP_DEFAULT (_SDIO_CFG0_CADMA2SUP_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_CHSSUP (0x1UL << 25) /**< High Speed Mode Support */ +#define _SDIO_CFG0_CHSSUP_SHIFT 25 /**< Shift value for SDIO_CHSSUP */ +#define _SDIO_CFG0_CHSSUP_MASK 0x2000000UL /**< Bit mask for SDIO_CHSSUP */ +#define _SDIO_CFG0_CHSSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_CHSSUP_DEFAULT (_SDIO_CFG0_CHSSUP_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_CSDMASUP (0x1UL << 26) /**< SDMA Mode Support */ +#define _SDIO_CFG0_CSDMASUP_SHIFT 26 /**< Shift value for SDIO_CSDMASUP */ +#define _SDIO_CFG0_CSDMASUP_MASK 0x4000000UL /**< Bit mask for SDIO_CSDMASUP */ +#define _SDIO_CFG0_CSDMASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_CSDMASUP_DEFAULT (_SDIO_CFG0_CSDMASUP_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_CSUSPRESSUP (0x1UL << 27) /**< Suspend/Resume Support */ +#define _SDIO_CFG0_CSUSPRESSUP_SHIFT 27 /**< Shift value for SDIO_CSUSPRESSUP */ +#define _SDIO_CFG0_CSUSPRESSUP_MASK 0x8000000UL /**< Bit mask for SDIO_CSUSPRESSUP */ +#define _SDIO_CFG0_CSUSPRESSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_CSUSPRESSUP_DEFAULT (_SDIO_CFG0_CSUSPRESSUP_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_C3P3VSUP (0x1UL << 28) /**< Core 3P3V Support */ +#define _SDIO_CFG0_C3P3VSUP_SHIFT 28 /**< Shift value for SDIO_C3P3VSUP */ +#define _SDIO_CFG0_C3P3VSUP_MASK 0x10000000UL /**< Bit mask for SDIO_C3P3VSUP */ +#define _SDIO_CFG0_C3P3VSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_C3P3VSUP_DEFAULT (_SDIO_CFG0_C3P3VSUP_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_C3P0VSUP (0x1UL << 29) /**< 3P0V Support */ +#define _SDIO_CFG0_C3P0VSUP_SHIFT 29 /**< Shift value for SDIO_C3P0VSUP */ +#define _SDIO_CFG0_C3P0VSUP_MASK 0x20000000UL /**< Bit mask for SDIO_C3P0VSUP */ +#define _SDIO_CFG0_C3P0VSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_C3P0VSUP_DEFAULT (_SDIO_CFG0_C3P0VSUP_DEFAULT << 29) /**< Shifted mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_C1P8VSUP (0x1UL << 30) /**< 1P8V Support */ +#define _SDIO_CFG0_C1P8VSUP_SHIFT 30 /**< Shift value for SDIO_C1P8VSUP */ +#define _SDIO_CFG0_C1P8VSUP_MASK 0x40000000UL /**< Bit mask for SDIO_C1P8VSUP */ +#define _SDIO_CFG0_C1P8VSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */ +#define SDIO_CFG0_C1P8VSUP_DEFAULT (_SDIO_CFG0_C1P8VSUP_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_CFG0 */ + +/* Bit fields for SDIO CFG1 */ +#define _SDIO_CFG1_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFG1 */ +#define _SDIO_CFG1_MASK 0x0005FFFFUL /**< Mask for SDIO_CFG1 */ +#define SDIO_CFG1_ASYNCINTRSUP (0x1UL << 0) /**< Asynchronous Interrupt Support */ +#define _SDIO_CFG1_ASYNCINTRSUP_SHIFT 0 /**< Shift value for SDIO_ASYNCINTRSUP */ +#define _SDIO_CFG1_ASYNCINTRSUP_MASK 0x1UL /**< Bit mask for SDIO_ASYNCINTRSUP */ +#define _SDIO_CFG1_ASYNCINTRSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_ASYNCINTRSUP_DEFAULT (_SDIO_CFG1_ASYNCINTRSUP_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define _SDIO_CFG1_SLOTTYPE_SHIFT 1 /**< Shift value for SDIO_SLOTTYPE */ +#define _SDIO_CFG1_SLOTTYPE_MASK 0x6UL /**< Bit mask for SDIO_SLOTTYPE */ +#define _SDIO_CFG1_SLOTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define _SDIO_CFG1_SLOTTYPE_RMSDSLOT 0x00000000UL /**< Mode RMSDSLOT for SDIO_CFG1 */ +#define _SDIO_CFG1_SLOTTYPE_EMSDSLOT 0x00000001UL /**< Mode EMSDSLOT for SDIO_CFG1 */ +#define _SDIO_CFG1_SLOTTYPE_SHBUSSLOT 0x00000002UL /**< Mode SHBUSSLOT for SDIO_CFG1 */ +#define SDIO_CFG1_SLOTTYPE_DEFAULT (_SDIO_CFG1_SLOTTYPE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_SLOTTYPE_RMSDSLOT (_SDIO_CFG1_SLOTTYPE_RMSDSLOT << 1) /**< Shifted mode RMSDSLOT for SDIO_CFG1 */ +#define SDIO_CFG1_SLOTTYPE_EMSDSLOT (_SDIO_CFG1_SLOTTYPE_EMSDSLOT << 1) /**< Shifted mode EMSDSLOT for SDIO_CFG1 */ +#define SDIO_CFG1_SLOTTYPE_SHBUSSLOT (_SDIO_CFG1_SLOTTYPE_SHBUSSLOT << 1) /**< Shifted mode SHBUSSLOT for SDIO_CFG1 */ +#define SDIO_CFG1_CSDR50SUP (0x1UL << 3) /**< Core Support SDR50 */ +#define _SDIO_CFG1_CSDR50SUP_SHIFT 3 /**< Shift value for SDIO_CSDR50SUP */ +#define _SDIO_CFG1_CSDR50SUP_MASK 0x8UL /**< Bit mask for SDIO_CSDR50SUP */ +#define _SDIO_CFG1_CSDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_CSDR50SUP_DEFAULT (_SDIO_CFG1_CSDR50SUP_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_CSDR104SUP (0x1UL << 4) /**< Support SDR104 */ +#define _SDIO_CFG1_CSDR104SUP_SHIFT 4 /**< Shift value for SDIO_CSDR104SUP */ +#define _SDIO_CFG1_CSDR104SUP_MASK 0x10UL /**< Bit mask for SDIO_CSDR104SUP */ +#define _SDIO_CFG1_CSDR104SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_CSDR104SUP_DEFAULT (_SDIO_CFG1_CSDR104SUP_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_CDDR50SUP (0x1UL << 5) /**< Support DDR50 */ +#define _SDIO_CFG1_CDDR50SUP_SHIFT 5 /**< Shift value for SDIO_CDDR50SUP */ +#define _SDIO_CFG1_CDDR50SUP_MASK 0x20UL /**< Bit mask for SDIO_CDDR50SUP */ +#define _SDIO_CFG1_CDDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_CDDR50SUP_DEFAULT (_SDIO_CFG1_CDDR50SUP_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_CDRVASUP (0x1UL << 6) /**< Support Type a Driver */ +#define _SDIO_CFG1_CDRVASUP_SHIFT 6 /**< Shift value for SDIO_CDRVASUP */ +#define _SDIO_CFG1_CDRVASUP_MASK 0x40UL /**< Bit mask for SDIO_CDRVASUP */ +#define _SDIO_CFG1_CDRVASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_CDRVASUP_DEFAULT (_SDIO_CFG1_CDRVASUP_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_CDRVCSUP (0x1UL << 7) /**< Support Type C Driver */ +#define _SDIO_CFG1_CDRVCSUP_SHIFT 7 /**< Shift value for SDIO_CDRVCSUP */ +#define _SDIO_CFG1_CDRVCSUP_MASK 0x80UL /**< Bit mask for SDIO_CDRVCSUP */ +#define _SDIO_CFG1_CDRVCSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_CDRVCSUP_DEFAULT (_SDIO_CFG1_CDRVCSUP_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_CDRVDSUP (0x1UL << 8) /**< Support Type D Driver */ +#define _SDIO_CFG1_CDRVDSUP_SHIFT 8 /**< Shift value for SDIO_CDRVDSUP */ +#define _SDIO_CFG1_CDRVDSUP_MASK 0x100UL /**< Bit mask for SDIO_CDRVDSUP */ +#define _SDIO_CFG1_CDRVDSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_CDRVDSUP_DEFAULT (_SDIO_CFG1_CDRVDSUP_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define _SDIO_CFG1_RETUNTMRCTL_SHIFT 9 /**< Shift value for SDIO_RETUNTMRCTL */ +#define _SDIO_CFG1_RETUNTMRCTL_MASK 0x1E00UL /**< Bit mask for SDIO_RETUNTMRCTL */ +#define _SDIO_CFG1_RETUNTMRCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_RETUNTMRCTL_DEFAULT (_SDIO_CFG1_RETUNTMRCTL_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_TUNSDR50 (0x1UL << 13) /**< Tuning for SDR50 */ +#define _SDIO_CFG1_TUNSDR50_SHIFT 13 /**< Shift value for SDIO_TUNSDR50 */ +#define _SDIO_CFG1_TUNSDR50_MASK 0x2000UL /**< Bit mask for SDIO_TUNSDR50 */ +#define _SDIO_CFG1_TUNSDR50_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_TUNSDR50_DEFAULT (_SDIO_CFG1_TUNSDR50_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define _SDIO_CFG1_RETUNMODES_SHIFT 14 /**< Shift value for SDIO_RETUNMODES */ +#define _SDIO_CFG1_RETUNMODES_MASK 0xC000UL /**< Bit mask for SDIO_RETUNMODES */ +#define _SDIO_CFG1_RETUNMODES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_RETUNMODES_DEFAULT (_SDIO_CFG1_RETUNMODES_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_SPISUP (0x1UL << 16) /**< SPI Support */ +#define _SDIO_CFG1_SPISUP_SHIFT 16 /**< Shift value for SDIO_SPISUP */ +#define _SDIO_CFG1_SPISUP_MASK 0x10000UL /**< Bit mask for SDIO_SPISUP */ +#define _SDIO_CFG1_SPISUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_SPISUP_DEFAULT (_SDIO_CFG1_SPISUP_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_ASYNCWKUPEN (0x1UL << 18) /**< Asynchronous Wakeup Enable */ +#define _SDIO_CFG1_ASYNCWKUPEN_SHIFT 18 /**< Shift value for SDIO_ASYNCWKUPEN */ +#define _SDIO_CFG1_ASYNCWKUPEN_MASK 0x40000UL /**< Bit mask for SDIO_ASYNCWKUPEN */ +#define _SDIO_CFG1_ASYNCWKUPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */ +#define SDIO_CFG1_ASYNCWKUPEN_DEFAULT (_SDIO_CFG1_ASYNCWKUPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_CFG1 */ + +/* Bit fields for SDIO CFGPRESETVAL0 */ +#define _SDIO_CFGPRESETVAL0_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL0 */ +#define _SDIO_CFGPRESETVAL0_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL0 */ +#define _SDIO_CFGPRESETVAL0_INITSDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_INITSDCLKFREQ */ +#define _SDIO_CFGPRESETVAL0_INITSDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_INITSDCLKFREQ */ +#define _SDIO_CFGPRESETVAL0_INITSDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ +#define SDIO_CFGPRESETVAL0_INITSDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL0_INITSDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ +#define SDIO_CFGPRESETVAL0_INITCLKGENEN (0x1UL << 10) /**< Initial Clock Gen Enable */ +#define _SDIO_CFGPRESETVAL0_INITCLKGENEN_SHIFT 10 /**< Shift value for SDIO_INITCLKGENEN */ +#define _SDIO_CFGPRESETVAL0_INITCLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_INITCLKGENEN */ +#define _SDIO_CFGPRESETVAL0_INITCLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ +#define SDIO_CFGPRESETVAL0_INITCLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL0_INITCLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ +#define _SDIO_CFGPRESETVAL0_INITDRVST_SHIFT 11 /**< Shift value for SDIO_INITDRVST */ +#define _SDIO_CFGPRESETVAL0_INITDRVST_MASK 0x1800UL /**< Bit mask for SDIO_INITDRVST */ +#define _SDIO_CFGPRESETVAL0_INITDRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ +#define SDIO_CFGPRESETVAL0_INITDRVST_DEFAULT (_SDIO_CFGPRESETVAL0_INITDRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ +#define _SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_DSPSDCLKFREQ */ +#define _SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_DSPSDCLKFREQ */ +#define _SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ +#define SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ +#define SDIO_CFGPRESETVAL0_DSPCLKGENEN (0x1UL << 26) /**< Default Speed Clock Gen Enable */ +#define _SDIO_CFGPRESETVAL0_DSPCLKGENEN_SHIFT 26 /**< Shift value for SDIO_DSPCLKGENEN */ +#define _SDIO_CFGPRESETVAL0_DSPCLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_DSPCLKGENEN */ +#define _SDIO_CFGPRESETVAL0_DSPCLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ +#define SDIO_CFGPRESETVAL0_DSPCLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL0_DSPCLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ +#define _SDIO_CFGPRESETVAL0_DSPDRVST_SHIFT 27 /**< Shift value for SDIO_DSPDRVST */ +#define _SDIO_CFGPRESETVAL0_DSPDRVST_MASK 0x18000000UL /**< Bit mask for SDIO_DSPDRVST */ +#define _SDIO_CFGPRESETVAL0_DSPDRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */ +#define SDIO_CFGPRESETVAL0_DSPDRVST_DEFAULT (_SDIO_CFGPRESETVAL0_DSPDRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */ + +/* Bit fields for SDIO CFGPRESETVAL1 */ +#define _SDIO_CFGPRESETVAL1_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL1 */ +#define _SDIO_CFGPRESETVAL1_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL1 */ +#define _SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_HSPSDCLKFREQ */ +#define _SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_HSPSDCLKFREQ */ +#define _SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ +#define SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ +#define SDIO_CFGPRESETVAL1_HSPCLKGENEN (0x1UL << 10) /**< High Speed SD_CLK Gen Enable */ +#define _SDIO_CFGPRESETVAL1_HSPCLKGENEN_SHIFT 10 /**< Shift value for SDIO_HSPCLKGENEN */ +#define _SDIO_CFGPRESETVAL1_HSPCLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_HSPCLKGENEN */ +#define _SDIO_CFGPRESETVAL1_HSPCLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ +#define SDIO_CFGPRESETVAL1_HSPCLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL1_HSPCLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ +#define _SDIO_CFGPRESETVAL1_HSPDRVST_SHIFT 11 /**< Shift value for SDIO_HSPDRVST */ +#define _SDIO_CFGPRESETVAL1_HSPDRVST_MASK 0x1800UL /**< Bit mask for SDIO_HSPDRVST */ +#define _SDIO_CFGPRESETVAL1_HSPDRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ +#define SDIO_CFGPRESETVAL1_HSPDRVST_DEFAULT (_SDIO_CFGPRESETVAL1_HSPDRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ +#define _SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_SDR12SDCLKFREQ */ +#define _SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR12SDCLKFREQ */ +#define _SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ +#define SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ +#define SDIO_CFGPRESETVAL1_SDR12CLKGENEN (0x1UL << 26) /**< SDR12 Speed Clock Gen Enable */ +#define _SDIO_CFGPRESETVAL1_SDR12CLKGENEN_SHIFT 26 /**< Shift value for SDIO_SDR12CLKGENEN */ +#define _SDIO_CFGPRESETVAL1_SDR12CLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_SDR12CLKGENEN */ +#define _SDIO_CFGPRESETVAL1_SDR12CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ +#define SDIO_CFGPRESETVAL1_SDR12CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL1_SDR12CLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ +#define _SDIO_CFGPRESETVAL1_SDR12DRVST_SHIFT 27 /**< Shift value for SDIO_SDR12DRVST */ +#define _SDIO_CFGPRESETVAL1_SDR12DRVST_MASK 0x18000000UL /**< Bit mask for SDIO_SDR12DRVST */ +#define _SDIO_CFGPRESETVAL1_SDR12DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */ +#define SDIO_CFGPRESETVAL1_SDR12DRVST_DEFAULT (_SDIO_CFGPRESETVAL1_SDR12DRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */ + +/* Bit fields for SDIO CFGPRESETVAL2 */ +#define _SDIO_CFGPRESETVAL2_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL2 */ +#define _SDIO_CFGPRESETVAL2_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL2 */ +#define _SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_SDR25SDCLKFREQ */ +#define _SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_SDR25SDCLKFREQ */ +#define _SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ +#define SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ +#define SDIO_CFGPRESETVAL2_SDR25CLKGENEN (0x1UL << 10) /**< SDR25 SD_CLK Gen Enable */ +#define _SDIO_CFGPRESETVAL2_SDR25CLKGENEN_SHIFT 10 /**< Shift value for SDIO_SDR25CLKGENEN */ +#define _SDIO_CFGPRESETVAL2_SDR25CLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_SDR25CLKGENEN */ +#define _SDIO_CFGPRESETVAL2_SDR25CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ +#define SDIO_CFGPRESETVAL2_SDR25CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL2_SDR25CLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ +#define _SDIO_CFGPRESETVAL2_SDR25DRVST_SHIFT 11 /**< Shift value for SDIO_SDR25DRVST */ +#define _SDIO_CFGPRESETVAL2_SDR25DRVST_MASK 0x1800UL /**< Bit mask for SDIO_SDR25DRVST */ +#define _SDIO_CFGPRESETVAL2_SDR25DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ +#define SDIO_CFGPRESETVAL2_SDR25DRVST_DEFAULT (_SDIO_CFGPRESETVAL2_SDR25DRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ +#define _SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_SDR50SDCLKFREQ */ +#define _SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR50SDCLKFREQ */ +#define _SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ +#define SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ +#define SDIO_CFGPRESETVAL2_SDR50CLKGENEN (0x1UL << 26) /**< SDR50 Speed Clock Gen Enable */ +#define _SDIO_CFGPRESETVAL2_SDR50CLKGENEN_SHIFT 26 /**< Shift value for SDIO_SDR50CLKGENEN */ +#define _SDIO_CFGPRESETVAL2_SDR50CLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_SDR50CLKGENEN */ +#define _SDIO_CFGPRESETVAL2_SDR50CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ +#define SDIO_CFGPRESETVAL2_SDR50CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL2_SDR50CLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ +#define _SDIO_CFGPRESETVAL2_SDR50DRVST_SHIFT 27 /**< Shift value for SDIO_SDR50DRVST */ +#define _SDIO_CFGPRESETVAL2_SDR50DRVST_MASK 0x18000000UL /**< Bit mask for SDIO_SDR50DRVST */ +#define _SDIO_CFGPRESETVAL2_SDR50DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */ +#define SDIO_CFGPRESETVAL2_SDR50DRVST_DEFAULT (_SDIO_CFGPRESETVAL2_SDR50DRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */ + +/* Bit fields for SDIO CFGPRESETVAL3 */ +#define _SDIO_CFGPRESETVAL3_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL3 */ +#define _SDIO_CFGPRESETVAL3_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL3 */ +#define _SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_SDR104SDCLKFREQ */ +#define _SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_SDR104SDCLKFREQ */ +#define _SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ +#define SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ +#define SDIO_CFGPRESETVAL3_SDR104CLKGENEN (0x1UL << 10) /**< SDR104 SD_CLK Gen Enable */ +#define _SDIO_CFGPRESETVAL3_SDR104CLKGENEN_SHIFT 10 /**< Shift value for SDIO_SDR104CLKGENEN */ +#define _SDIO_CFGPRESETVAL3_SDR104CLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_SDR104CLKGENEN */ +#define _SDIO_CFGPRESETVAL3_SDR104CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ +#define SDIO_CFGPRESETVAL3_SDR104CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL3_SDR104CLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ +#define _SDIO_CFGPRESETVAL3_SDR104DRVST_SHIFT 11 /**< Shift value for SDIO_SDR104DRVST */ +#define _SDIO_CFGPRESETVAL3_SDR104DRVST_MASK 0x1800UL /**< Bit mask for SDIO_SDR104DRVST */ +#define _SDIO_CFGPRESETVAL3_SDR104DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ +#define SDIO_CFGPRESETVAL3_SDR104DRVST_DEFAULT (_SDIO_CFGPRESETVAL3_SDR104DRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ +#define _SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_DDR50SDCLKFREQ */ +#define _SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_DDR50SDCLKFREQ */ +#define _SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ +#define SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ +#define SDIO_CFGPRESETVAL3_DDR50CLKGENEN (0x1UL << 26) /**< DDR50 Speed Clock Gen Enable */ +#define _SDIO_CFGPRESETVAL3_DDR50CLKGENEN_SHIFT 26 /**< Shift value for SDIO_DDR50CLKGENEN */ +#define _SDIO_CFGPRESETVAL3_DDR50CLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_DDR50CLKGENEN */ +#define _SDIO_CFGPRESETVAL3_DDR50CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ +#define SDIO_CFGPRESETVAL3_DDR50CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL3_DDR50CLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ +#define _SDIO_CFGPRESETVAL3_DDR50DRVST_SHIFT 27 /**< Shift value for SDIO_DDR50DRVST */ +#define _SDIO_CFGPRESETVAL3_DDR50DRVST_MASK 0x18000000UL /**< Bit mask for SDIO_DDR50DRVST */ +#define _SDIO_CFGPRESETVAL3_DDR50DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */ +#define SDIO_CFGPRESETVAL3_DDR50DRVST_DEFAULT (_SDIO_CFGPRESETVAL3_DDR50DRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */ + +/* Bit fields for SDIO ROUTELOC0 */ +#define _SDIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_MASK 0x01030301UL /**< Mask for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_DATLOC_SHIFT 0 /**< Shift value for SDIO_DATLOC */ +#define _SDIO_ROUTELOC0_DATLOC_MASK 0x1UL /**< Bit mask for SDIO_DATLOC */ +#define _SDIO_ROUTELOC0_DATLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_DATLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_DATLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_DATLOC_LOC0 (_SDIO_ROUTELOC0_DATLOC_LOC0 << 0) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_DATLOC_DEFAULT (_SDIO_ROUTELOC0_DATLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_DATLOC_LOC1 (_SDIO_ROUTELOC0_DATLOC_LOC1 << 0) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_CDLOC_SHIFT 8 /**< Shift value for SDIO_CDLOC */ +#define _SDIO_ROUTELOC0_CDLOC_MASK 0x300UL /**< Bit mask for SDIO_CDLOC */ +#define _SDIO_ROUTELOC0_CDLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_CDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_CDLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_CDLOC_LOC2 0x00000002UL /**< Mode LOC2 for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_CDLOC_LOC3 0x00000003UL /**< Mode LOC3 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_CDLOC_LOC0 (_SDIO_ROUTELOC0_CDLOC_LOC0 << 8) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_CDLOC_DEFAULT (_SDIO_ROUTELOC0_CDLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_CDLOC_LOC1 (_SDIO_ROUTELOC0_CDLOC_LOC1 << 8) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_CDLOC_LOC2 (_SDIO_ROUTELOC0_CDLOC_LOC2 << 8) /**< Shifted mode LOC2 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_CDLOC_LOC3 (_SDIO_ROUTELOC0_CDLOC_LOC3 << 8) /**< Shifted mode LOC3 for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_WPLOC_SHIFT 16 /**< Shift value for SDIO_WPLOC */ +#define _SDIO_ROUTELOC0_WPLOC_MASK 0x30000UL /**< Bit mask for SDIO_WPLOC */ +#define _SDIO_ROUTELOC0_WPLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_WPLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_WPLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_WPLOC_LOC2 0x00000002UL /**< Mode LOC2 for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_WPLOC_LOC3 0x00000003UL /**< Mode LOC3 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_WPLOC_LOC0 (_SDIO_ROUTELOC0_WPLOC_LOC0 << 16) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_WPLOC_DEFAULT (_SDIO_ROUTELOC0_WPLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_WPLOC_LOC1 (_SDIO_ROUTELOC0_WPLOC_LOC1 << 16) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_WPLOC_LOC2 (_SDIO_ROUTELOC0_WPLOC_LOC2 << 16) /**< Shifted mode LOC2 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_WPLOC_LOC3 (_SDIO_ROUTELOC0_WPLOC_LOC3 << 16) /**< Shifted mode LOC3 for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for SDIO_CLKLOC */ +#define _SDIO_ROUTELOC0_CLKLOC_MASK 0x1000000UL /**< Bit mask for SDIO_CLKLOC */ +#define _SDIO_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */ +#define _SDIO_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_CLKLOC_LOC0 (_SDIO_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_CLKLOC_DEFAULT (_SDIO_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */ +#define SDIO_ROUTELOC0_CLKLOC_LOC1 (_SDIO_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */ + +/* Bit fields for SDIO ROUTELOC1 */ +#define _SDIO_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for SDIO_ROUTELOC1 */ +#define _SDIO_ROUTELOC1_MASK 0x00000001UL /**< Mask for SDIO_ROUTELOC1 */ +#define _SDIO_ROUTELOC1_CMDLOC_SHIFT 0 /**< Shift value for SDIO_CMDLOC */ +#define _SDIO_ROUTELOC1_CMDLOC_MASK 0x1UL /**< Bit mask for SDIO_CMDLOC */ +#define _SDIO_ROUTELOC1_CMDLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC1 */ +#define _SDIO_ROUTELOC1_CMDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC1 */ +#define _SDIO_ROUTELOC1_CMDLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC1 */ +#define SDIO_ROUTELOC1_CMDLOC_LOC0 (_SDIO_ROUTELOC1_CMDLOC_LOC0 << 0) /**< Shifted mode LOC0 for SDIO_ROUTELOC1 */ +#define SDIO_ROUTELOC1_CMDLOC_DEFAULT (_SDIO_ROUTELOC1_CMDLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ROUTELOC1 */ +#define SDIO_ROUTELOC1_CMDLOC_LOC1 (_SDIO_ROUTELOC1_CMDLOC_LOC1 << 0) /**< Shifted mode LOC1 for SDIO_ROUTELOC1 */ + +/* Bit fields for SDIO ROUTEPEN */ +#define _SDIO_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for SDIO_ROUTEPEN */ +#define _SDIO_ROUTEPEN_MASK 0x000003FFUL /**< Mask for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_CLKPEN (0x1UL << 0) /**< CLK I/O Enable */ +#define _SDIO_ROUTEPEN_CLKPEN_SHIFT 0 /**< Shift value for SDIO_CLKPEN */ +#define _SDIO_ROUTEPEN_CLKPEN_MASK 0x1UL /**< Bit mask for SDIO_CLKPEN */ +#define _SDIO_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_CLKPEN_DEFAULT (_SDIO_ROUTEPEN_CLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_CMDPEN (0x1UL << 1) /**< CMD I/O Enable */ +#define _SDIO_ROUTEPEN_CMDPEN_SHIFT 1 /**< Shift value for SDIO_CMDPEN */ +#define _SDIO_ROUTEPEN_CMDPEN_MASK 0x2UL /**< Bit mask for SDIO_CMDPEN */ +#define _SDIO_ROUTEPEN_CMDPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_CMDPEN_DEFAULT (_SDIO_ROUTEPEN_CMDPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D0PEN (0x1UL << 2) /**< Dat0 I/O Enable */ +#define _SDIO_ROUTEPEN_D0PEN_SHIFT 2 /**< Shift value for SDIO_D0PEN */ +#define _SDIO_ROUTEPEN_D0PEN_MASK 0x4UL /**< Bit mask for SDIO_D0PEN */ +#define _SDIO_ROUTEPEN_D0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D0PEN_DEFAULT (_SDIO_ROUTEPEN_D0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D1PEN (0x1UL << 3) /**< Dat1 I/O Enable */ +#define _SDIO_ROUTEPEN_D1PEN_SHIFT 3 /**< Shift value for SDIO_D1PEN */ +#define _SDIO_ROUTEPEN_D1PEN_MASK 0x8UL /**< Bit mask for SDIO_D1PEN */ +#define _SDIO_ROUTEPEN_D1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D1PEN_DEFAULT (_SDIO_ROUTEPEN_D1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D2PEN (0x1UL << 4) /**< Dat2 I/O Enable */ +#define _SDIO_ROUTEPEN_D2PEN_SHIFT 4 /**< Shift value for SDIO_D2PEN */ +#define _SDIO_ROUTEPEN_D2PEN_MASK 0x10UL /**< Bit mask for SDIO_D2PEN */ +#define _SDIO_ROUTEPEN_D2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D2PEN_DEFAULT (_SDIO_ROUTEPEN_D2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D3PEN (0x1UL << 5) /**< Dat3 I/O Enable */ +#define _SDIO_ROUTEPEN_D3PEN_SHIFT 5 /**< Shift value for SDIO_D3PEN */ +#define _SDIO_ROUTEPEN_D3PEN_MASK 0x20UL /**< Bit mask for SDIO_D3PEN */ +#define _SDIO_ROUTEPEN_D3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D3PEN_DEFAULT (_SDIO_ROUTEPEN_D3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D4PEN (0x1UL << 6) /**< Dat4 I/O Enable */ +#define _SDIO_ROUTEPEN_D4PEN_SHIFT 6 /**< Shift value for SDIO_D4PEN */ +#define _SDIO_ROUTEPEN_D4PEN_MASK 0x40UL /**< Bit mask for SDIO_D4PEN */ +#define _SDIO_ROUTEPEN_D4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D4PEN_DEFAULT (_SDIO_ROUTEPEN_D4PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D5PEN (0x1UL << 7) /**< Dat5 Enable */ +#define _SDIO_ROUTEPEN_D5PEN_SHIFT 7 /**< Shift value for SDIO_D5PEN */ +#define _SDIO_ROUTEPEN_D5PEN_MASK 0x80UL /**< Bit mask for SDIO_D5PEN */ +#define _SDIO_ROUTEPEN_D5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D5PEN_DEFAULT (_SDIO_ROUTEPEN_D5PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D6PEN (0x1UL << 8) /**< Dat6 Enable */ +#define _SDIO_ROUTEPEN_D6PEN_SHIFT 8 /**< Shift value for SDIO_D6PEN */ +#define _SDIO_ROUTEPEN_D6PEN_MASK 0x100UL /**< Bit mask for SDIO_D6PEN */ +#define _SDIO_ROUTEPEN_D6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D6PEN_DEFAULT (_SDIO_ROUTEPEN_D6PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D7PEN (0x1UL << 9) /**< Data7 I/O Enable */ +#define _SDIO_ROUTEPEN_D7PEN_SHIFT 9 /**< Shift value for SDIO_D7PEN */ +#define _SDIO_ROUTEPEN_D7PEN_MASK 0x200UL /**< Bit mask for SDIO_D7PEN */ +#define _SDIO_ROUTEPEN_D7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */ +#define SDIO_ROUTEPEN_D7PEN_DEFAULT (_SDIO_ROUTEPEN_D7PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */ + +/** @} */ +/** @} End of group EFM32GG11B_SDIO */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_smu.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_smu.h new file mode 100644 index 0000000000000..6a1b15788d3c1 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_smu.h @@ -0,0 +1,596 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_SMU register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_SMU SMU + * @{ + * @brief EFM32GG11B_SMU Register Declaration + ******************************************************************************/ +/** SMU Register Declaration */ +typedef struct { + uint32_t RESERVED0[3U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9U]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ + + uint32_t RESERVED3[13U]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_SMU + * @{ + * @defgroup EFM32GG11B_SMU_BitFields SMU Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ +#define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ +#define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ +#define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ +#define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ +#define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ +#define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ +#define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ +#define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ +#define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ +#define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ETH (0x1UL << 16) /**< Ethernet Controller access control bit */ +#define _SMU_PPUPATD0_ETH_SHIFT 16 /**< Shift value for SMU_ETH */ +#define _SMU_PPUPATD0_ETH_MASK 0x10000UL /**< Bit mask for SMU_ETH */ +#define _SMU_PPUPATD0_ETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ETH_DEFAULT (_SMU_PPUPATD0_ETH_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ +#define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ +#define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ +#define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ +#define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ +#define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ +#define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ +#define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_QSPI0 (0x1UL << 3) /**< Quad-SPI access control bit */ +#define _SMU_PPUPATD1_QSPI0_SHIFT 3 /**< Shift value for SMU_QSPI0 */ +#define _SMU_PPUPATD1_QSPI0_MASK 0x8UL /**< Bit mask for SMU_QSPI0 */ +#define _SMU_PPUPATD1_QSPI0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_QSPI0_DEFAULT (_SMU_PPUPATD1_QSPI0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ +#define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ +#define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SDIO (0x1UL << 7) /**< SDIO Controller access control bit */ +#define _SMU_PPUPATD1_SDIO_SHIFT 7 /**< Shift value for SMU_SDIO */ +#define _SMU_PPUPATD1_SDIO_MASK 0x80UL /**< Bit mask for SMU_SDIO */ +#define _SMU_PPUPATD1_SDIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SDIO_DEFAULT (_SMU_PPUPATD1_SDIO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ +#define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ +#define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ +#define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ +#define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ +#define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ +#define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ +#define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ +#define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ +#define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ +#define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ +#define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ +#define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ +#define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USB (0x1UL << 25) /**< Universal Serial Bus Interface access control bit */ +#define _SMU_PPUPATD1_USB_SHIFT 25 /**< Shift value for SMU_USB */ +#define _SMU_PPUPATD1_USB_MASK 0x2000000UL /**< Bit mask for SMU_USB */ +#define _SMU_PPUPATD1_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USB_DEFAULT (_SMU_PPUPATD1_USB_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ +#define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ +#define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ +#define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ +#define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUPATD2 */ +#define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ +#define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ETH 0x00000010UL /**< Mode ETH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_QSPI0 0x00000023UL /**< Mode QSPI0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SDIO 0x00000027UL /**< Mode SDIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USB 0x00000039UL /**< Mode USB for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ETH (_SMU_PPUFS_PERIPHID_ETH << 0) /**< Shifted mode ETH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_QSPI0 (_SMU_PPUFS_PERIPHID_QSPI0 << 0) /**< Shifted mode QSPI0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SDIO (_SMU_PPUFS_PERIPHID_SDIO << 0) /**< Shifted mode SDIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USB (_SMU_PPUFS_PERIPHID_USB << 0) /**< Shifted mode USB for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ + +/** @} */ +/** @} End of group EFM32GG11B_SMU */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_timer.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_timer.h new file mode 100644 index 0000000000000..1fa62abce9d4f --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_timer.h @@ -0,0 +1,1338 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_TIMER register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_TIMER TIMER + * @{ + * @brief EFM32GG11B_TIMER Register Declaration + ******************************************************************************/ +/** TIMER Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + + uint32_t RESERVED2[8U]; /**< Reserved registers */ + TIMER_CC_TypeDef CC[4U]; /**< Compare/Capture Channel */ + + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTTIME; /**< DTI Time Control Register */ + __IOM uint32_t DTFC; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_TIMER + * @{ + * @defgroup EFM32GG11B_TIMER_BitFields TIMER Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ +#define _TIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ +#define _TIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _TIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DISSYNCOUT_DEFAULT (_TIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ +#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _TIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _TIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _TIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV3_DEFAULT (_TIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _TIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _TIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _TIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV3_DEFAULT (_TIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _TIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _TIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _TIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_DEFAULT (_TIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_LOWRISE (_TIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_HIGHFALL (_TIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x00000FF7UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _TIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC3_DEFAULT (_TIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF3_DEFAULT (_TIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IFS */ +#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */ +#define _TIMER_IFS_MASK 0x00000FF7UL /**< Mask for TIMER_IFS */ +#define TIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _TIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_DIRCHG_DEFAULT (_TIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _TIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC3_DEFAULT (_TIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _TIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF3_DEFAULT (_TIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFS */ + +/* Bit fields for TIMER IFC */ +#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */ +#define _TIMER_IFC_MASK 0x00000FF7UL /**< Mask for TIMER_IFC */ +#define TIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _TIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_DIRCHG_DEFAULT (_TIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _TIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC3_DEFAULT (_TIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _TIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF3_DEFAULT (_TIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFC */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x00000FF7UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _TIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC3_DEFAULT (_TIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _TIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF3_DEFAULT (_TIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER ROUTEPEN */ +#define _TIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTEPEN */ +#define _TIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _TIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _TIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _TIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC0PEN_DEFAULT (_TIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _TIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _TIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _TIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC1PEN_DEFAULT (_TIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _TIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _TIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _TIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC2PEN_DEFAULT (_TIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _TIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _TIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _TIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC3PEN_DEFAULT (_TIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _TIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _TIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _TIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _TIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _TIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _TIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ + +/* Bit fields for TIMER ROUTELOC0 */ +#define _TIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _TIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC0 (_TIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_DEFAULT (_TIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC1 (_TIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC2 (_TIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC3 (_TIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC4 (_TIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC5 (_TIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC6 (_TIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC7 (_TIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _TIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC0 (_TIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_DEFAULT (_TIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC1 (_TIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC2 (_TIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC3 (_TIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC4 (_TIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC5 (_TIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC6 (_TIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC7 (_TIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _TIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC0 (_TIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_DEFAULT (_TIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC1 (_TIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC2 (_TIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC3 (_TIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC4 (_TIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC5 (_TIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC6 (_TIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC7 (_TIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _TIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC0 (_TIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_DEFAULT (_TIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC1 (_TIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC2 (_TIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC3 (_TIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC4 (_TIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC5 (_TIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC6 (_TIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC7 (_TIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ + +/* Bit fields for TIMER ROUTELOC2 */ +#define _TIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _TIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC0 (_TIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC1 (_TIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC2 (_TIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC3 (_TIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC4 (_TIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _TIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC0 (_TIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC1 (_TIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC2 (_TIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC3 (_TIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC4 (_TIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _TIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC0 (_TIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC1 (_TIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC2 (_TIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC3 (_TIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC4 (_TIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH12 (_TIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH13 (_TIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH14 (_TIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH15 (_TIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH16 (_TIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH17 (_TIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH18 (_TIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH19 (_TIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH20 (_TIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH21 (_TIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH22 (_TIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH23 (_TIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _TIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_DEFAULT (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_PULSE (_TIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_LEVEL (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _TIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _TIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_CCV */ +#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */ +#define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */ + +/* Bit fields for TIMER CC_CCVP */ +#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */ +#define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */ + +/* Bit fields for TIMER CC_CCVB */ +#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */ +#define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH12 (_TIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH13 (_TIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH14 (_TIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH15 (_TIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH16 (_TIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH17 (_TIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH18 (_TIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH19 (_TIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH20 (_TIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH21 (_TIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH22 (_TIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH23 (_TIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTAR_DEFAULT (_TIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTFATS_DEFAULT (_TIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTTIME */ +#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */ +#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */ + +/* Bit fields for TIMER DTFC */ +#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */ +#define _TIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH8 (_TIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH9 (_TIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH10 (_TIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH11 (_TIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH12 (_TIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH13 (_TIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH14 (_TIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH15 (_TIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH16 (_TIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH17 (_TIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH18 (_TIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH19 (_TIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH20 (_TIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH21 (_TIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH22 (_TIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH23 (_TIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH8 (_TIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH9 (_TIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH10 (_TIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH11 (_TIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH12 (_TIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH13 (_TIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH14 (_TIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH15 (_TIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH16 (_TIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH17 (_TIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH18 (_TIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH19 (_TIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH20 (_TIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH21 (_TIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH22 (_TIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH23 (_TIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} */ +/** @} End of group EFM32GG11B_TIMER */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_timer_cc.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_timer_cc.h new file mode 100644 index 0000000000000..5f2cc897da30d --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_timer_cc.h @@ -0,0 +1,61 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_TIMER_CC register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief TIMER_CC TIMER CC Register + * @ingroup EFM32GG11B_TIMER + ******************************************************************************/ +typedef struct { + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t CCV; /**< CC Channel Value Register */ + __IM uint32_t CCVP; /**< CC Channel Value Peek Register */ + __IOM uint32_t CCVB; /**< CC Channel Buffer Register */ +} TIMER_CC_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_trng.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_trng.h new file mode 100644 index 0000000000000..13ac914b76c06 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_trng.h @@ -0,0 +1,295 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_TRNG register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_TRNG TRNG + * @{ + * @brief EFM32GG11B_TRNG Register Declaration + ******************************************************************************/ +/** TRNG Register Declaration */ +typedef struct { + __IOM uint32_t CONTROL; /**< Main Control Register */ + __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */ + __IOM uint32_t KEY0; /**< Key Register 0 */ + __IOM uint32_t KEY1; /**< Key Register 1 */ + __IOM uint32_t KEY2; /**< Key Register 2 */ + __IOM uint32_t KEY3; /**< Key Register 3 */ + __IOM uint32_t TESTDATA; /**< Test Data Register */ + + uint32_t RESERVED1[3U]; /**< Reserved for future use **/ + __IOM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */ + uint32_t RESERVED2[50U]; /**< Reserved for future use **/ + __IM uint32_t FIFO; /**< FIFO Data */ +} TRNG_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_TRNG + * @{ + * @defgroup EFM32GG11B_TRNG_BitFields TRNG Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for TRNG CONTROL */ +#define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */ +#define _TRNG_CONTROL_MASK 0x00003FFDUL /**< Mask for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */ +#define _TRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for TRNG_ENABLE */ +#define _TRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for TRNG_ENABLE */ +#define _TRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for TRNG_CONTROL */ +#define _TRNG_CONTROL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_DEFAULT (_TRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_DISABLED (_TRNG_CONTROL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_ENABLED (_TRNG_CONTROL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN (0x1UL << 2) /**< Test Enable */ +#define _TRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for TRNG_TESTEN */ +#define _TRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for TRNG_TESTEN */ +#define _TRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for TRNG_CONTROL */ +#define _TRNG_CONTROL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_DEFAULT (_TRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_NOISE (_TRNG_CONTROL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_TESTDATA (_TRNG_CONTROL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */ +#define _TRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for TRNG_CONDBYPASS */ +#define _TRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for TRNG_CONDBYPASS */ +#define _TRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt Enable for Repetition Count Test Failure */ +#define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */ +#define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */ +#define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt Enable for Adaptive Proportion Test Failure (64-sample Window) */ +#define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */ +#define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */ +#define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt Enable for Adaptive Proportion Test Failure (4096-sample Window) */ +#define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */ +#define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */ +#define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt Enable for FIFO Full */ +#define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */ +#define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */ +#define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FULLIEN_DEFAULT (_TRNG_CONTROL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET (0x1UL << 8) /**< Software Reset */ +#define _TRNG_CONTROL_SOFTRESET_SHIFT 8 /**< Shift value for TRNG_SOFTRESET */ +#define _TRNG_CONTROL_SOFTRESET_MASK 0x100UL /**< Bit mask for TRNG_SOFTRESET */ +#define _TRNG_CONTROL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_DEFAULT (_TRNG_CONTROL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_NORMAL (_TRNG_CONTROL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_RESET (_TRNG_CONTROL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for TRNG_CONTROL */ +#define TRNG_CONTROL_PREIEN (0x1UL << 9) /**< Interrupt enable for AIS31 preliminary noise alarm */ +#define _TRNG_CONTROL_PREIEN_SHIFT 9 /**< Shift value for TRNG_PREIEN */ +#define _TRNG_CONTROL_PREIEN_MASK 0x200UL /**< Bit mask for TRNG_PREIEN */ +#define _TRNG_CONTROL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_PREIEN_DEFAULT (_TRNG_CONTROL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ALMIEN (0x1UL << 10) /**< Interrupt enable for AIS31 noise alarm */ +#define _TRNG_CONTROL_ALMIEN_SHIFT 10 /**< Shift value for TRNG_ALMIEN */ +#define _TRNG_CONTROL_ALMIEN_MASK 0x400UL /**< Bit mask for TRNG_ALMIEN */ +#define _TRNG_CONTROL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ALMIEN_DEFAULT (_TRNG_CONTROL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */ +#define _TRNG_CONTROL_FORCERUN_SHIFT 11 /**< Shift value for TRNG_FORCERUN */ +#define _TRNG_CONTROL_FORCERUN_MASK 0x800UL /**< Bit mask for TRNG_FORCERUN */ +#define _TRNG_CONTROL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_DEFAULT (_TRNG_CONTROL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_NORMAL (_TRNG_CONTROL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_RUN (_TRNG_CONTROL_FORCERUN_RUN << 11) /**< Shifted mode RUN for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */ +#define _TRNG_CONTROL_BYPNIST_SHIFT 12 /**< Shift value for TRNG_BYPNIST */ +#define _TRNG_CONTROL_BYPNIST_MASK 0x1000UL /**< Bit mask for TRNG_BYPNIST */ +#define _TRNG_CONTROL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_DEFAULT (_TRNG_CONTROL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_NORMAL (_TRNG_CONTROL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_BYPASS (_TRNG_CONTROL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */ +#define _TRNG_CONTROL_BYPAIS31_SHIFT 13 /**< Shift value for TRNG_BYPAIS31 */ +#define _TRNG_CONTROL_BYPAIS31_MASK 0x2000UL /**< Bit mask for TRNG_BYPAIS31 */ +#define _TRNG_CONTROL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_DEFAULT (_TRNG_CONTROL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_NORMAL (_TRNG_CONTROL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_BYPASS (_TRNG_CONTROL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for TRNG_CONTROL */ + +/* Bit fields for TRNG FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFOLEVEL_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFOLEVEL_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFOLEVEL */ +#define TRNG_FIFOLEVEL_VALUE_DEFAULT (_TRNG_FIFOLEVEL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFOLEVEL */ + +/* Bit fields for TRNG FIFODEPTH */ +#define _TRNG_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for TRNG_FIFODEPTH */ +#define _TRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFODEPTH */ +#define _TRNG_FIFODEPTH_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFODEPTH_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFODEPTH_VALUE_DEFAULT 0x00000040UL /**< Mode DEFAULT for TRNG_FIFODEPTH */ +#define TRNG_FIFODEPTH_VALUE_DEFAULT (_TRNG_FIFODEPTH_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFODEPTH */ + +/* Bit fields for TRNG KEY0 */ +#define _TRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY0 */ +#define _TRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY0 */ +#define _TRNG_KEY0_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY0_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY0_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY0 */ +#define TRNG_KEY0_VALUE_DEFAULT (_TRNG_KEY0_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY0 */ + +/* Bit fields for TRNG KEY1 */ +#define _TRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY1 */ +#define _TRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY1 */ +#define _TRNG_KEY1_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY1_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY1_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY1 */ +#define TRNG_KEY1_VALUE_DEFAULT (_TRNG_KEY1_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY1 */ + +/* Bit fields for TRNG KEY2 */ +#define _TRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY2 */ +#define _TRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY2 */ +#define _TRNG_KEY2_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY2_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY2_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY2 */ +#define TRNG_KEY2_VALUE_DEFAULT (_TRNG_KEY2_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY2 */ + +/* Bit fields for TRNG KEY3 */ +#define _TRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY3 */ +#define _TRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY3 */ +#define _TRNG_KEY3_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY3_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY3_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY3 */ +#define TRNG_KEY3_VALUE_DEFAULT (_TRNG_KEY3_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY3 */ + +/* Bit fields for TRNG TESTDATA */ +#define _TRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for TRNG_TESTDATA */ +#define _TRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for TRNG_TESTDATA */ +#define _TRNG_TESTDATA_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_TESTDATA */ +#define TRNG_TESTDATA_VALUE_DEFAULT (_TRNG_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_TESTDATA */ + +/* Bit fields for TRNG STATUS */ +#define _TRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for TRNG_STATUS */ +#define _TRNG_STATUS_MASK 0x000003F1UL /**< Mask for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */ +#define _TRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for TRNG_TESTDATABUSY */ +#define _TRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for TRNG_TESTDATABUSY */ +#define _TRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define _TRNG_STATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for TRNG_STATUS */ +#define _TRNG_STATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */ +#define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test Interrupt Status */ +#define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */ +#define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */ +#define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_REPCOUNTIF_DEFAULT (_TRNG_STATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT64IF (0x1UL << 5) /**< Adaptive Proportion test failure (64-sample window) interrupt status */ +#define _TRNG_STATUS_APT64IF_SHIFT 5 /**< Shift value for TRNG_APT64IF */ +#define _TRNG_STATUS_APT64IF_MASK 0x20UL /**< Bit mask for TRNG_APT64IF */ +#define _TRNG_STATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT64IF_DEFAULT (_TRNG_STATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT4096IF (0x1UL << 6) /**< Adaptive Proportion test failure (4096-sample window) interrupt status */ +#define _TRNG_STATUS_APT4096IF_SHIFT 6 /**< Shift value for TRNG_APT4096IF */ +#define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */ +#define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO Full Interrupt Status */ +#define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */ +#define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */ +#define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_FULLIF_DEFAULT (_TRNG_STATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm interrupt status */ +#define _TRNG_STATUS_PREIF_SHIFT 8 /**< Shift value for TRNG_PREIF */ +#define _TRNG_STATUS_PREIF_MASK 0x100UL /**< Bit mask for TRNG_PREIF */ +#define _TRNG_STATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_PREIF_DEFAULT (_TRNG_STATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */ +#define _TRNG_STATUS_ALMIF_SHIFT 9 /**< Shift value for TRNG_ALMIF */ +#define _TRNG_STATUS_ALMIF_MASK 0x200UL /**< Bit mask for TRNG_ALMIF */ +#define _TRNG_STATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_ALMIF_DEFAULT (_TRNG_STATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_STATUS */ + +/* Bit fields for TRNG INITWAITVAL */ +#define _TRNG_INITWAITVAL_RESETVALUE 0x000000FFUL /**< Default value for TRNG_INITWAITVAL */ +#define _TRNG_INITWAITVAL_MASK 0x000000FFUL /**< Mask for TRNG_INITWAITVAL */ +#define _TRNG_INITWAITVAL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_INITWAITVAL_VALUE_MASK 0xFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_INITWAITVAL_VALUE_DEFAULT 0x000000FFUL /**< Mode DEFAULT for TRNG_INITWAITVAL */ +#define TRNG_INITWAITVAL_VALUE_DEFAULT (_TRNG_INITWAITVAL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_INITWAITVAL */ + +/* Bit fields for TRNG FIFO */ +#define _TRNG_FIFO_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFO */ +#define _TRNG_FIFO_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFO */ +#define _TRNG_FIFO_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFO_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */ +#define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */ + +/** @} */ +/** @} End of group EFM32GG11B_TRNG */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_uart.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_uart.h new file mode 100644 index 0000000000000..7825023ad4ab3 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_uart.h @@ -0,0 +1,1744 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_UART register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_UART + * @{ + * @defgroup EFM32GG11B_UART_BitFields UART Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for UART CTRL */ +#define _UART_CTRL_RESETVALUE 0x00000000UL /**< Default value for UART_CTRL */ +#define _UART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for UART_CTRL */ +#define UART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _UART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _UART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _UART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SYNC_DEFAULT (_UART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _UART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _UART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _UART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_LOOPBK_DEFAULT (_UART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _UART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _UART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _UART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CCEN_DEFAULT (_UART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _UART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _UART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _UART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_MPM_DEFAULT (_UART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _UART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _UART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _UART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_MPAB_DEFAULT (_UART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _UART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _UART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for UART_CTRL */ +#define _UART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for UART_CTRL */ +#define _UART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for UART_CTRL */ +#define _UART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for UART_CTRL */ +#define UART_CTRL_OVS_DEFAULT (_UART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_OVS_X16 (_UART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for UART_CTRL */ +#define UART_CTRL_OVS_X8 (_UART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for UART_CTRL */ +#define UART_CTRL_OVS_X6 (_UART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for UART_CTRL */ +#define UART_CTRL_OVS_X4 (_UART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for UART_CTRL */ +#define UART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _UART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _UART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _UART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for UART_CTRL */ +#define _UART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for UART_CTRL */ +#define UART_CTRL_CLKPOL_DEFAULT (_UART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CLKPOL_IDLELOW (_UART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for UART_CTRL */ +#define UART_CTRL_CLKPOL_IDLEHIGH (_UART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for UART_CTRL */ +#define UART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge for Setup/Sample */ +#define _UART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _UART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _UART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for UART_CTRL */ +#define _UART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for UART_CTRL */ +#define UART_CTRL_CLKPHA_DEFAULT (_UART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CLKPHA_SAMPLELEADING (_UART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for UART_CTRL */ +#define UART_CTRL_CLKPHA_SAMPLETRAILING (_UART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for UART_CTRL */ +#define UART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _UART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _UART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _UART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_MSBF_DEFAULT (_UART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CSMA (0x1UL << 11) /**< Action on Slave-Select in Master Mode */ +#define _UART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _UART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _UART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for UART_CTRL */ +#define _UART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for UART_CTRL */ +#define UART_CTRL_CSMA_DEFAULT (_UART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CSMA_NOACTION (_UART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for UART_CTRL */ +#define UART_CTRL_CSMA_GOTOSLAVEMODE (_UART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for UART_CTRL */ +#define UART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _UART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _UART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _UART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define _UART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for UART_CTRL */ +#define _UART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for UART_CTRL */ +#define UART_CTRL_TXBIL_DEFAULT (_UART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_TXBIL_EMPTY (_UART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for UART_CTRL */ +#define UART_CTRL_TXBIL_HALFFULL (_UART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for UART_CTRL */ +#define UART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _UART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _UART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _UART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_RXINV_DEFAULT (_UART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_TXINV (0x1UL << 14) /**< Transmitter Output Invert */ +#define _UART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _UART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _UART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_TXINV_DEFAULT (_UART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _UART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _UART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _UART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_CSINV_DEFAULT (_UART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _UART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _UART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _UART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_AUTOCS_DEFAULT (_UART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _UART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _UART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _UART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_AUTOTRI_DEFAULT (_UART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _UART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _UART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _UART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SCMODE_DEFAULT (_UART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _UART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _UART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _UART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SCRETRANS_DEFAULT (_UART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _UART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _UART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _UART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SKIPPERRF_DEFAULT (_UART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _UART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _UART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _UART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_BIT8DV_DEFAULT (_UART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA on Error */ +#define _UART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _UART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _UART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_ERRSDMA_DEFAULT (_UART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX on Error */ +#define _UART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _UART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _UART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_ERRSRX_DEFAULT (_UART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX on Error */ +#define _UART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _UART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _UART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_ERRSTX_DEFAULT (_UART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ +#define _UART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _UART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _UART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SSSEARLY_DEFAULT (_UART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap in Double Accesses */ +#define _UART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _UART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _UART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_BYTESWAP_DEFAULT (_UART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _UART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _UART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _UART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_AUTOTX_DEFAULT (_UART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _UART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _UART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _UART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_MVDIS_DEFAULT (_UART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ +#define _UART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _UART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _UART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */ +#define UART_CTRL_SMSDELAY_DEFAULT (_UART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_CTRL */ + +/* Bit fields for UART FRAME */ +#define _UART_FRAME_RESETVALUE 0x00001005UL /**< Default value for UART_FRAME */ +#define _UART_FRAME_MASK 0x0000330FUL /**< Mask for UART_FRAME */ +#define _UART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _UART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _UART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for UART_FRAME */ +#define _UART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for UART_FRAME */ +#define _UART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for UART_FRAME */ +#define _UART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for UART_FRAME */ +#define _UART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for UART_FRAME */ +#define _UART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for UART_FRAME */ +#define _UART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for UART_FRAME */ +#define _UART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for UART_FRAME */ +#define _UART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for UART_FRAME */ +#define UART_FRAME_DATABITS_FOUR (_UART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for UART_FRAME */ +#define UART_FRAME_DATABITS_FIVE (_UART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for UART_FRAME */ +#define UART_FRAME_DATABITS_SIX (_UART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for UART_FRAME */ +#define UART_FRAME_DATABITS_SEVEN (_UART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for UART_FRAME */ +#define UART_FRAME_DATABITS_DEFAULT (_UART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_FRAME */ +#define UART_FRAME_DATABITS_EIGHT (_UART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for UART_FRAME */ +#define UART_FRAME_DATABITS_NINE (_UART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for UART_FRAME */ +#define UART_FRAME_DATABITS_TEN (_UART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for UART_FRAME */ +#define UART_FRAME_DATABITS_ELEVEN (_UART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for UART_FRAME */ +#define UART_FRAME_DATABITS_TWELVE (_UART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for UART_FRAME */ +#define UART_FRAME_DATABITS_THIRTEEN (_UART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for UART_FRAME */ +#define UART_FRAME_DATABITS_FOURTEEN (_UART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for UART_FRAME */ +#define UART_FRAME_DATABITS_FIFTEEN (_UART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for UART_FRAME */ +#define UART_FRAME_DATABITS_SIXTEEN (_UART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for UART_FRAME */ +#define _UART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _UART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _UART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_FRAME */ +#define _UART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for UART_FRAME */ +#define _UART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for UART_FRAME */ +#define _UART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for UART_FRAME */ +#define UART_FRAME_PARITY_DEFAULT (_UART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_FRAME */ +#define UART_FRAME_PARITY_NONE (_UART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for UART_FRAME */ +#define UART_FRAME_PARITY_EVEN (_UART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for UART_FRAME */ +#define UART_FRAME_PARITY_ODD (_UART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for UART_FRAME */ +#define _UART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _UART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _UART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for UART_FRAME */ +#define _UART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_FRAME */ +#define _UART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for UART_FRAME */ +#define _UART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for UART_FRAME */ +#define _UART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for UART_FRAME */ +#define UART_FRAME_STOPBITS_HALF (_UART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for UART_FRAME */ +#define UART_FRAME_STOPBITS_DEFAULT (_UART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_FRAME */ +#define UART_FRAME_STOPBITS_ONE (_UART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for UART_FRAME */ +#define UART_FRAME_STOPBITS_ONEANDAHALF (_UART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for UART_FRAME */ +#define UART_FRAME_STOPBITS_TWO (_UART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for UART_FRAME */ + +/* Bit fields for UART TRIGCTRL */ +#define _UART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_MASK 0x001F1FF0UL /**< Mask for UART_TRIGCTRL */ +#define UART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _UART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _UART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _UART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_RXTEN_DEFAULT (_UART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _UART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _UART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _UART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TXTEN_DEFAULT (_UART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _UART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _UART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _UART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_AUTOTXTEN_DEFAULT (_UART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL */ +#define _UART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _UART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _UART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TXARX0EN_DEFAULT (_UART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL */ +#define _UART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _UART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _UART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TXARX1EN_DEFAULT (_UART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL */ +#define _UART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _UART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _UART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TXARX2EN_DEFAULT (_UART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times */ +#define _UART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _UART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _UART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_RXATX0EN_DEFAULT (_UART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times */ +#define _UART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _UART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _UART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_RXATX1EN_DEFAULT (_UART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times */ +#define _UART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _UART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _UART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_RXATX2EN_DEFAULT (_UART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */ +#define _UART_TRIGCTRL_TSEL_MASK 0x1F0000UL /**< Bit mask for USART_TSEL */ +#define _UART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for UART_TRIGCTRL */ +#define _UART_TRIGCTRL_TSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_DEFAULT (_UART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH0 (_UART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH1 (_UART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH2 (_UART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH3 (_UART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH4 (_UART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH5 (_UART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH6 (_UART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH7 (_UART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH8 (_UART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH9 (_UART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH10 (_UART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH11 (_UART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH12 (_UART_TRIGCTRL_TSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH13 (_UART_TRIGCTRL_TSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH14 (_UART_TRIGCTRL_TSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH15 (_UART_TRIGCTRL_TSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH16 (_UART_TRIGCTRL_TSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH17 (_UART_TRIGCTRL_TSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH18 (_UART_TRIGCTRL_TSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH19 (_UART_TRIGCTRL_TSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH20 (_UART_TRIGCTRL_TSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH21 (_UART_TRIGCTRL_TSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH22 (_UART_TRIGCTRL_TSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for UART_TRIGCTRL */ +#define UART_TRIGCTRL_TSEL_PRSCH23 (_UART_TRIGCTRL_TSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for UART_TRIGCTRL */ + +/* Bit fields for UART CMD */ +#define _UART_CMD_RESETVALUE 0x00000000UL /**< Default value for UART_CMD */ +#define _UART_CMD_MASK 0x00000FFFUL /**< Mask for UART_CMD */ +#define UART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _UART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _UART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _UART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_RXEN_DEFAULT (_UART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CMD */ +#define UART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _UART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _UART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _UART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_RXDIS_DEFAULT (_UART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CMD */ +#define UART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _UART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _UART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _UART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_TXEN_DEFAULT (_UART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CMD */ +#define UART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _UART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _UART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _UART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_TXDIS_DEFAULT (_UART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CMD */ +#define UART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ +#define _UART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _UART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _UART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_MASTEREN_DEFAULT (_UART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CMD */ +#define UART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ +#define _UART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _UART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _UART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_MASTERDIS_DEFAULT (_UART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CMD */ +#define UART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _UART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _UART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _UART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_RXBLOCKEN_DEFAULT (_UART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_CMD */ +#define UART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _UART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _UART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _UART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_RXBLOCKDIS_DEFAULT (_UART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_CMD */ +#define UART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _UART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _UART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _UART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_TXTRIEN_DEFAULT (_UART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CMD */ +#define UART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _UART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _UART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _UART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_TXTRIDIS_DEFAULT (_UART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CMD */ +#define UART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _UART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _UART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _UART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_CLEARTX_DEFAULT (_UART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CMD */ +#define UART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _UART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _UART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _UART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */ +#define UART_CMD_CLEARRX_DEFAULT (_UART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CMD */ + +/* Bit fields for UART STATUS */ +#define _UART_STATUS_RESETVALUE 0x00002040UL /**< Default value for UART_STATUS */ +#define _UART_STATUS_MASK 0x00037FFFUL /**< Mask for UART_STATUS */ +#define UART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _UART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _UART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _UART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXENS_DEFAULT (_UART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _UART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _UART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _UART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXENS_DEFAULT (_UART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ +#define _UART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _UART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _UART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_MASTER_DEFAULT (_UART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _UART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _UART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _UART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXBLOCK_DEFAULT (_UART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _UART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _UART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _UART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXTRI_DEFAULT (_UART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _UART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _UART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _UART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXC_DEFAULT (_UART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _UART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _UART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _UART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXBL_DEFAULT (_UART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _UART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _UART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _UART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXDATAV_DEFAULT (_UART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _UART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _UART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _UART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXFULL_DEFAULT (_UART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _UART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _UART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _UART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXBDRIGHT_DEFAULT (_UART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _UART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _UART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _UART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXBSRIGHT_DEFAULT (_UART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _UART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _UART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _UART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXDATAVRIGHT_DEFAULT (_UART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _UART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _UART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _UART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_RXFULLRIGHT_DEFAULT (_UART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _UART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _UART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _UART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXIDLE_DEFAULT (_UART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer Restarted Itself */ +#define _UART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _UART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _UART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TIMERRESTARTED_DEFAULT (_UART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_STATUS */ +#define _UART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _UART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _UART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */ +#define UART_STATUS_TXBUFCNT_DEFAULT (_UART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_STATUS */ + +/* Bit fields for UART CLKDIV */ +#define _UART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for UART_CLKDIV */ +#define _UART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for UART_CLKDIV */ +#define _UART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _UART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _UART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CLKDIV */ +#define UART_CLKDIV_DIV_DEFAULT (_UART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CLKDIV */ +#define UART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD Detection Enable */ +#define _UART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _UART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _UART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CLKDIV */ +#define UART_CLKDIV_AUTOBAUDEN_DEFAULT (_UART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_CLKDIV */ + +/* Bit fields for UART RXDATAX */ +#define _UART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAX */ +#define _UART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAX */ +#define _UART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _UART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _UART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */ +#define UART_RXDATAX_RXDATA_DEFAULT (_UART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAX */ +#define UART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _UART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _UART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _UART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */ +#define UART_RXDATAX_PERR_DEFAULT (_UART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAX */ +#define UART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _UART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _UART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _UART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */ +#define UART_RXDATAX_FERR_DEFAULT (_UART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAX */ + +/* Bit fields for UART RXDATA */ +#define _UART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATA */ +#define _UART_RXDATA_MASK 0x000000FFUL /**< Mask for UART_RXDATA */ +#define _UART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _UART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _UART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATA */ +#define UART_RXDATA_RXDATA_DEFAULT (_UART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATA */ + +/* Bit fields for UART RXDOUBLEX */ +#define _UART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _UART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _UART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_RXDATA0_DEFAULT (_UART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _UART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _UART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _UART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_PERR0_DEFAULT (_UART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _UART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _UART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _UART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_FERR0_DEFAULT (_UART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ +#define _UART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _UART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _UART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_RXDATA1_DEFAULT (_UART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _UART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _UART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _UART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_PERR1_DEFAULT (_UART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _UART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _UART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _UART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */ +#define UART_RXDOUBLEX_FERR1_DEFAULT (_UART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */ + +/* Bit fields for UART RXDOUBLE */ +#define _UART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLE */ +#define _UART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_RXDOUBLE */ +#define _UART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _UART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _UART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */ +#define UART_RXDOUBLE_RXDATA0_DEFAULT (_UART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLE */ +#define _UART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _UART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _UART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */ +#define UART_RXDOUBLE_RXDATA1_DEFAULT (_UART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_RXDOUBLE */ + +/* Bit fields for UART RXDATAXP */ +#define _UART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAXP */ +#define _UART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAXP */ +#define _UART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _UART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _UART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */ +#define UART_RXDATAXP_RXDATAP_DEFAULT (_UART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAXP */ +#define UART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _UART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _UART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _UART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */ +#define UART_RXDATAXP_PERRP_DEFAULT (_UART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAXP */ +#define UART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _UART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _UART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _UART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */ +#define UART_RXDATAXP_FERRP_DEFAULT (_UART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAXP */ + +/* Bit fields for UART RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _UART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _UART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_RXDATAP0_DEFAULT (_UART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _UART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _UART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _UART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_PERRP0_DEFAULT (_UART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _UART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _UART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _UART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_FERRP0_DEFAULT (_UART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ +#define _UART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _UART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _UART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_RXDATAP1_DEFAULT (_UART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _UART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _UART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _UART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_PERRP1_DEFAULT (_UART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _UART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _UART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _UART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */ +#define UART_RXDOUBLEXP_FERRP1_DEFAULT (_UART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */ + +/* Bit fields for UART TXDATAX */ +#define _UART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATAX */ +#define _UART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for UART_TXDATAX */ +#define _UART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _UART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _UART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_TXDATAX_DEFAULT (_UART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _UART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _UART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _UART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_UBRXAT_DEFAULT (_UART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _UART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _UART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _UART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_TXTRIAT_DEFAULT (_UART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */ +#define _UART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _UART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _UART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_TXBREAK_DEFAULT (_UART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _UART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _UART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _UART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_TXDISAT_DEFAULT (_UART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _UART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _UART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _UART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */ +#define UART_TXDATAX_RXENAT_DEFAULT (_UART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDATAX */ + +/* Bit fields for UART TXDATA */ +#define _UART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATA */ +#define _UART_TXDATA_MASK 0x000000FFUL /**< Mask for UART_TXDATA */ +#define _UART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _UART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _UART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATA */ +#define UART_TXDATA_TXDATA_DEFAULT (_UART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATA */ + +/* Bit fields for UART TXDOUBLEX */ +#define _UART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _UART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _UART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXDATA0_DEFAULT (_UART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _UART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _UART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _UART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_UBRXAT0_DEFAULT (_UART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _UART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _UART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _UART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXTRIAT0_DEFAULT (_UART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data as Break */ +#define _UART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _UART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _UART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXBREAK0_DEFAULT (_UART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _UART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _UART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _UART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXDISAT0_DEFAULT (_UART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _UART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _UART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _UART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_RXENAT0_DEFAULT (_UART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define _UART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _UART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _UART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXDATA1_DEFAULT (_UART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _UART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _UART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _UART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_UBRXAT1_DEFAULT (_UART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _UART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _UART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _UART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXTRIAT1_DEFAULT (_UART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data as Break */ +#define _UART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _UART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _UART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXBREAK1_DEFAULT (_UART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _UART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _UART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _UART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_TXDISAT1_DEFAULT (_UART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _UART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _UART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _UART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */ +#define UART_TXDOUBLEX_RXENAT1_DEFAULT (_UART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */ + +/* Bit fields for UART TXDOUBLE */ +#define _UART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLE */ +#define _UART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_TXDOUBLE */ +#define _UART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _UART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _UART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */ +#define UART_TXDOUBLE_TXDATA0_DEFAULT (_UART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLE */ +#define _UART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _UART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _UART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */ +#define UART_TXDOUBLE_TXDATA1_DEFAULT (_UART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_TXDOUBLE */ + +/* Bit fields for UART IF */ +#define _UART_IF_RESETVALUE 0x00000002UL /**< Default value for UART_IF */ +#define _UART_IF_MASK 0x0001FFFFUL /**< Mask for UART_IF */ +#define UART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _UART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _UART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _UART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_TXC_DEFAULT (_UART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _UART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _UART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _UART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_TXBL_DEFAULT (_UART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _UART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _UART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _UART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_RXDATAV_DEFAULT (_UART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _UART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _UART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _UART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_RXFULL_DEFAULT (_UART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _UART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _UART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _UART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_RXOF_DEFAULT (_UART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _UART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _UART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _UART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_RXUF_DEFAULT (_UART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _UART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _UART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _UART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_TXOF_DEFAULT (_UART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _UART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _UART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _UART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_TXUF_DEFAULT (_UART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _UART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _UART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _UART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_PERR_DEFAULT (_UART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _UART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _UART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _UART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_FERR_DEFAULT (_UART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _UART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _UART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _UART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_MPAF_DEFAULT (_UART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_SSM (0x1UL << 11) /**< Slave-Select in Master Mode Interrupt Flag */ +#define _UART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _UART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _UART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_SSM_DEFAULT (_UART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _UART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _UART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _UART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_CCF_DEFAULT (_UART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _UART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _UART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _UART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_TXIDLE_DEFAULT (_UART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_TCMP0 (0x1UL << 14) /**< Timer Comparator 0 Interrupt Flag */ +#define _UART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _UART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _UART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_TCMP0_DEFAULT (_UART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_TCMP1 (0x1UL << 15) /**< Timer Comparator 1 Interrupt Flag */ +#define _UART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _UART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _UART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_TCMP1_DEFAULT (_UART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IF */ +#define UART_IF_TCMP2 (0x1UL << 16) /**< Timer Comparator 2 Interrupt Flag */ +#define _UART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _UART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _UART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */ +#define UART_IF_TCMP2_DEFAULT (_UART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IF */ + +/* Bit fields for UART IFS */ +#define _UART_IFS_RESETVALUE 0x00000000UL /**< Default value for UART_IFS */ +#define _UART_IFS_MASK 0x0001FFF9UL /**< Mask for UART_IFS */ +#define UART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ +#define _UART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _UART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _UART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_TXC_DEFAULT (_UART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */ +#define _UART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _UART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _UART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_RXFULL_DEFAULT (_UART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */ +#define _UART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _UART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _UART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_RXOF_DEFAULT (_UART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */ +#define _UART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _UART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _UART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_RXUF_DEFAULT (_UART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */ +#define _UART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _UART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _UART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_TXOF_DEFAULT (_UART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */ +#define _UART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _UART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _UART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_TXUF_DEFAULT (_UART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */ +#define _UART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _UART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _UART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_PERR_DEFAULT (_UART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */ +#define _UART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _UART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _UART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_FERR_DEFAULT (_UART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */ +#define _UART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _UART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _UART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_MPAF_DEFAULT (_UART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */ +#define _UART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _UART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _UART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_SSM_DEFAULT (_UART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */ +#define _UART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _UART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _UART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_CCF_DEFAULT (_UART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */ +#define _UART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _UART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _UART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_TXIDLE_DEFAULT (_UART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */ +#define _UART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _UART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _UART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_TCMP0_DEFAULT (_UART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */ +#define _UART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _UART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _UART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_TCMP1_DEFAULT (_UART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IFS */ +#define UART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */ +#define _UART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _UART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _UART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */ +#define UART_IFS_TCMP2_DEFAULT (_UART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IFS */ + +/* Bit fields for UART IFC */ +#define _UART_IFC_RESETVALUE 0x00000000UL /**< Default value for UART_IFC */ +#define _UART_IFC_MASK 0x0001FFF9UL /**< Mask for UART_IFC */ +#define UART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ +#define _UART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _UART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _UART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_TXC_DEFAULT (_UART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */ +#define _UART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _UART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _UART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_RXFULL_DEFAULT (_UART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */ +#define _UART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _UART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _UART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_RXOF_DEFAULT (_UART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */ +#define _UART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _UART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _UART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_RXUF_DEFAULT (_UART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */ +#define _UART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _UART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _UART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_TXOF_DEFAULT (_UART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */ +#define _UART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _UART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _UART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_TXUF_DEFAULT (_UART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */ +#define _UART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _UART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _UART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_PERR_DEFAULT (_UART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */ +#define _UART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _UART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _UART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_FERR_DEFAULT (_UART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */ +#define _UART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _UART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _UART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_MPAF_DEFAULT (_UART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */ +#define _UART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _UART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _UART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_SSM_DEFAULT (_UART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */ +#define _UART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _UART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _UART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_CCF_DEFAULT (_UART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */ +#define _UART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _UART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _UART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_TXIDLE_DEFAULT (_UART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */ +#define _UART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _UART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _UART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_TCMP0_DEFAULT (_UART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */ +#define _UART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _UART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _UART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_TCMP1_DEFAULT (_UART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IFC */ +#define UART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */ +#define _UART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _UART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _UART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */ +#define UART_IFC_TCMP2_DEFAULT (_UART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IFC */ + +/* Bit fields for UART IEN */ +#define _UART_IEN_RESETVALUE 0x00000000UL /**< Default value for UART_IEN */ +#define _UART_IEN_MASK 0x0001FFFFUL /**< Mask for UART_IEN */ +#define UART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ +#define _UART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _UART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _UART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_TXC_DEFAULT (_UART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ +#define _UART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _UART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _UART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_TXBL_DEFAULT (_UART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ +#define _UART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _UART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _UART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_RXDATAV_DEFAULT (_UART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */ +#define _UART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _UART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _UART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_RXFULL_DEFAULT (_UART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */ +#define _UART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _UART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _UART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_RXOF_DEFAULT (_UART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */ +#define _UART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _UART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _UART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_RXUF_DEFAULT (_UART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */ +#define _UART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _UART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _UART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_TXOF_DEFAULT (_UART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */ +#define _UART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _UART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _UART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_TXUF_DEFAULT (_UART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */ +#define _UART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _UART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _UART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_PERR_DEFAULT (_UART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */ +#define _UART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _UART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _UART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_FERR_DEFAULT (_UART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */ +#define _UART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _UART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _UART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_MPAF_DEFAULT (_UART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */ +#define _UART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _UART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _UART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_SSM_DEFAULT (_UART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */ +#define _UART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _UART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _UART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_CCF_DEFAULT (_UART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */ +#define _UART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _UART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _UART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_TXIDLE_DEFAULT (_UART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */ +#define _UART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _UART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _UART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_TCMP0_DEFAULT (_UART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */ +#define _UART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _UART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _UART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_TCMP1_DEFAULT (_UART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_IEN */ +#define UART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */ +#define _UART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _UART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _UART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */ +#define UART_IEN_TCMP2_DEFAULT (_UART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_IEN */ + +/* Bit fields for UART IRCTRL */ +#define _UART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_IRCTRL */ +#define _UART_IRCTRL_MASK 0x00001F8FUL /**< Mask for UART_IRCTRL */ +#define UART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _UART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _UART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _UART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ +#define UART_IRCTRL_IREN_DEFAULT (_UART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IRCTRL */ +#define _UART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _UART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _UART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ +#define _UART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for UART_IRCTRL */ +#define _UART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for UART_IRCTRL */ +#define _UART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for UART_IRCTRL */ +#define _UART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for UART_IRCTRL */ +#define UART_IRCTRL_IRPW_DEFAULT (_UART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IRCTRL */ +#define UART_IRCTRL_IRPW_ONE (_UART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for UART_IRCTRL */ +#define UART_IRCTRL_IRPW_TWO (_UART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for UART_IRCTRL */ +#define UART_IRCTRL_IRPW_THREE (_UART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for UART_IRCTRL */ +#define UART_IRCTRL_IRPW_FOUR (_UART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for UART_IRCTRL */ +#define UART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _UART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _UART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _UART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ +#define UART_IRCTRL_IRFILT_DEFAULT (_UART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ +#define _UART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ +#define _UART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ +#define _UART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSEN_DEFAULT (_UART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */ +#define _UART_IRCTRL_IRPRSSEL_MASK 0x1F00UL /**< Bit mask for USART_IRPRSSEL */ +#define _UART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for UART_IRCTRL */ +#define _UART_IRCTRL_IRPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_DEFAULT (_UART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH0 (_UART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH1 (_UART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH2 (_UART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH3 (_UART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH4 (_UART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH5 (_UART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH6 (_UART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH7 (_UART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH8 (_UART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH9 (_UART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH10 (_UART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH11 (_UART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH12 (_UART_IRCTRL_IRPRSSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH13 (_UART_IRCTRL_IRPRSSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH14 (_UART_IRCTRL_IRPRSSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH15 (_UART_IRCTRL_IRPRSSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH16 (_UART_IRCTRL_IRPRSSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH17 (_UART_IRCTRL_IRPRSSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH18 (_UART_IRCTRL_IRPRSSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH19 (_UART_IRCTRL_IRPRSSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH20 (_UART_IRCTRL_IRPRSSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH21 (_UART_IRCTRL_IRPRSSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH22 (_UART_IRCTRL_IRPRSSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for UART_IRCTRL */ +#define UART_IRCTRL_IRPRSSEL_PRSCH23 (_UART_IRCTRL_IRPRSSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for UART_IRCTRL */ + +/* Bit fields for UART INPUT */ +#define _UART_INPUT_RESETVALUE 0x00000000UL /**< Default value for UART_INPUT */ +#define _UART_INPUT_MASK 0x00009F9FUL /**< Mask for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ +#define _UART_INPUT_RXPRSSEL_MASK 0x1FUL /**< Bit mask for USART_RXPRSSEL */ +#define _UART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for UART_INPUT */ +#define _UART_INPUT_RXPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_DEFAULT (_UART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH0 (_UART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH1 (_UART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH2 (_UART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH3 (_UART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH4 (_UART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH5 (_UART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH6 (_UART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH7 (_UART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH8 (_UART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH9 (_UART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH10 (_UART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH11 (_UART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH12 (_UART_INPUT_RXPRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH13 (_UART_INPUT_RXPRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH14 (_UART_INPUT_RXPRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH15 (_UART_INPUT_RXPRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH16 (_UART_INPUT_RXPRSSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH17 (_UART_INPUT_RXPRSSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH18 (_UART_INPUT_RXPRSSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH19 (_UART_INPUT_RXPRSSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH20 (_UART_INPUT_RXPRSSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH21 (_UART_INPUT_RXPRSSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH22 (_UART_INPUT_RXPRSSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for UART_INPUT */ +#define UART_INPUT_RXPRSSEL_PRSCH23 (_UART_INPUT_RXPRSSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for UART_INPUT */ +#define UART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */ +#define _UART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */ +#define _UART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */ +#define _UART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */ +#define UART_INPUT_RXPRS_DEFAULT (_UART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */ +#define _UART_INPUT_CLKPRSSEL_MASK 0x1F00UL /**< Bit mask for USART_CLKPRSSEL */ +#define _UART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for UART_INPUT */ +#define _UART_INPUT_CLKPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_DEFAULT (_UART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH0 (_UART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH1 (_UART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH2 (_UART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH3 (_UART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH4 (_UART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH5 (_UART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH6 (_UART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH7 (_UART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH8 (_UART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH9 (_UART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH10 (_UART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH11 (_UART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH12 (_UART_INPUT_CLKPRSSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH13 (_UART_INPUT_CLKPRSSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH14 (_UART_INPUT_CLKPRSSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH15 (_UART_INPUT_CLKPRSSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH16 (_UART_INPUT_CLKPRSSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH17 (_UART_INPUT_CLKPRSSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH18 (_UART_INPUT_CLKPRSSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH19 (_UART_INPUT_CLKPRSSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH20 (_UART_INPUT_CLKPRSSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH21 (_UART_INPUT_CLKPRSSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH22 (_UART_INPUT_CLKPRSSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for UART_INPUT */ +#define UART_INPUT_CLKPRSSEL_PRSCH23 (_UART_INPUT_CLKPRSSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for UART_INPUT */ +#define UART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */ +#define _UART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */ +#define _UART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */ +#define _UART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */ +#define UART_INPUT_CLKPRS_DEFAULT (_UART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_INPUT */ + +/* Bit fields for UART I2SCTRL */ +#define _UART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_I2SCTRL */ +#define _UART_I2SCTRL_MASK 0x0000071FUL /**< Mask for UART_I2SCTRL */ +#define UART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _UART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _UART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _UART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ +#define UART_I2SCTRL_EN_DEFAULT (_UART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_I2SCTRL */ +#define UART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _UART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _UART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _UART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ +#define UART_I2SCTRL_MONO_DEFAULT (_UART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_I2SCTRL */ +#define UART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _UART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _UART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _UART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ +#define _UART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for UART_I2SCTRL */ +#define _UART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for UART_I2SCTRL */ +#define UART_I2SCTRL_JUSTIFY_DEFAULT (_UART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_I2SCTRL */ +#define UART_I2SCTRL_JUSTIFY_LEFT (_UART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for UART_I2SCTRL */ +#define UART_I2SCTRL_JUSTIFY_RIGHT (_UART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for UART_I2SCTRL */ +#define UART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request for Left/Right Data */ +#define _UART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _UART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _UART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ +#define UART_I2SCTRL_DMASPLIT_DEFAULT (_UART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_I2SCTRL */ +#define UART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S Data */ +#define _UART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _UART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _UART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ +#define UART_I2SCTRL_DELAY_DEFAULT (_UART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_I2SCTRL */ +#define _UART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _UART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _UART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */ +#define _UART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for UART_I2SCTRL */ +#define _UART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for UART_I2SCTRL */ +#define _UART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for UART_I2SCTRL */ +#define _UART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for UART_I2SCTRL */ +#define _UART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for UART_I2SCTRL */ +#define _UART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for UART_I2SCTRL */ +#define _UART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for UART_I2SCTRL */ +#define _UART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for UART_I2SCTRL */ +#define UART_I2SCTRL_FORMAT_DEFAULT (_UART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_I2SCTRL */ +#define UART_I2SCTRL_FORMAT_W32D32 (_UART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for UART_I2SCTRL */ +#define UART_I2SCTRL_FORMAT_W32D24M (_UART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for UART_I2SCTRL */ +#define UART_I2SCTRL_FORMAT_W32D24 (_UART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for UART_I2SCTRL */ +#define UART_I2SCTRL_FORMAT_W32D16 (_UART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for UART_I2SCTRL */ +#define UART_I2SCTRL_FORMAT_W32D8 (_UART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for UART_I2SCTRL */ +#define UART_I2SCTRL_FORMAT_W16D16 (_UART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for UART_I2SCTRL */ +#define UART_I2SCTRL_FORMAT_W16D8 (_UART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for UART_I2SCTRL */ +#define UART_I2SCTRL_FORMAT_W8D8 (_UART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for UART_I2SCTRL */ + +/* Bit fields for UART TIMING */ +#define _UART_TIMING_RESETVALUE 0x00000000UL /**< Default value for UART_TIMING */ +#define _UART_TIMING_MASK 0x77770000UL /**< Mask for UART_TIMING */ +#define _UART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _UART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _UART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */ +#define _UART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMING */ +#define _UART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */ +#define _UART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */ +#define _UART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */ +#define _UART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */ +#define _UART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */ +#define _UART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */ +#define _UART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */ +#define UART_TIMING_TXDELAY_DEFAULT (_UART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMING */ +#define UART_TIMING_TXDELAY_DISABLE (_UART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMING */ +#define UART_TIMING_TXDELAY_ONE (_UART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for UART_TIMING */ +#define UART_TIMING_TXDELAY_TWO (_UART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for UART_TIMING */ +#define UART_TIMING_TXDELAY_THREE (_UART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for UART_TIMING */ +#define UART_TIMING_TXDELAY_SEVEN (_UART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for UART_TIMING */ +#define UART_TIMING_TXDELAY_TCMP0 (_UART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for UART_TIMING */ +#define UART_TIMING_TXDELAY_TCMP1 (_UART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for UART_TIMING */ +#define UART_TIMING_TXDELAY_TCMP2 (_UART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for UART_TIMING */ +#define _UART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _UART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _UART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */ +#define _UART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for UART_TIMING */ +#define _UART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */ +#define _UART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */ +#define _UART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */ +#define _UART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */ +#define _UART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */ +#define _UART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */ +#define _UART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */ +#define UART_TIMING_CSSETUP_DEFAULT (_UART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMING */ +#define UART_TIMING_CSSETUP_ZERO (_UART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for UART_TIMING */ +#define UART_TIMING_CSSETUP_ONE (_UART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for UART_TIMING */ +#define UART_TIMING_CSSETUP_TWO (_UART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for UART_TIMING */ +#define UART_TIMING_CSSETUP_THREE (_UART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for UART_TIMING */ +#define UART_TIMING_CSSETUP_SEVEN (_UART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for UART_TIMING */ +#define UART_TIMING_CSSETUP_TCMP0 (_UART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for UART_TIMING */ +#define UART_TIMING_CSSETUP_TCMP1 (_UART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for UART_TIMING */ +#define UART_TIMING_CSSETUP_TCMP2 (_UART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for UART_TIMING */ +#define _UART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _UART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _UART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */ +#define _UART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for UART_TIMING */ +#define _UART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */ +#define _UART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */ +#define _UART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */ +#define _UART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */ +#define _UART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */ +#define _UART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */ +#define _UART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */ +#define UART_TIMING_ICS_DEFAULT (_UART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMING */ +#define UART_TIMING_ICS_ZERO (_UART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for UART_TIMING */ +#define UART_TIMING_ICS_ONE (_UART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for UART_TIMING */ +#define UART_TIMING_ICS_TWO (_UART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for UART_TIMING */ +#define UART_TIMING_ICS_THREE (_UART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for UART_TIMING */ +#define UART_TIMING_ICS_SEVEN (_UART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for UART_TIMING */ +#define UART_TIMING_ICS_TCMP0 (_UART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for UART_TIMING */ +#define UART_TIMING_ICS_TCMP1 (_UART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for UART_TIMING */ +#define UART_TIMING_ICS_TCMP2 (_UART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for UART_TIMING */ +#define _UART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _UART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _UART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMING */ +#define _UART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for UART_TIMING */ +#define _UART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for UART_TIMING */ +#define _UART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for UART_TIMING */ +#define _UART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for UART_TIMING */ +#define _UART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for UART_TIMING */ +#define _UART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for UART_TIMING */ +#define _UART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for UART_TIMING */ +#define _UART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for UART_TIMING */ +#define UART_TIMING_CSHOLD_DEFAULT (_UART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_TIMING */ +#define UART_TIMING_CSHOLD_ZERO (_UART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for UART_TIMING */ +#define UART_TIMING_CSHOLD_ONE (_UART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for UART_TIMING */ +#define UART_TIMING_CSHOLD_TWO (_UART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for UART_TIMING */ +#define UART_TIMING_CSHOLD_THREE (_UART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for UART_TIMING */ +#define UART_TIMING_CSHOLD_SEVEN (_UART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for UART_TIMING */ +#define UART_TIMING_CSHOLD_TCMP0 (_UART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for UART_TIMING */ +#define UART_TIMING_CSHOLD_TCMP1 (_UART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for UART_TIMING */ +#define UART_TIMING_CSHOLD_TCMP2 (_UART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for UART_TIMING */ + +/* Bit fields for UART CTRLX */ +#define _UART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for UART_CTRLX */ +#define _UART_CTRLX_MASK 0x0000000FUL /**< Mask for UART_CTRLX */ +#define UART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug Halt */ +#define _UART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _UART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _UART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */ +#define UART_CTRLX_DBGHALT_DEFAULT (_UART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CTRLX */ +#define UART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _UART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _UART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _UART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */ +#define UART_CTRLX_CTSINV_DEFAULT (_UART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CTRLX */ +#define UART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function Enabled */ +#define _UART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _UART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _UART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */ +#define UART_CTRLX_CTSEN_DEFAULT (_UART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CTRLX */ +#define UART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _UART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _UART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _UART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRLX */ +#define UART_CTRLX_RTSINV_DEFAULT (_UART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CTRLX */ + +/* Bit fields for UART TIMECMP0 */ +#define _UART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for UART_TIMECMP0 */ +#define _UART_TIMECMP0_MASK 0x017700FFUL /**< Mask for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _UART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _UART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */ +#define UART_TIMECMP0_TCMPVAL_DEFAULT (_UART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _UART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _UART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for UART_TIMECMP0 */ +#define UART_TIMECMP0_TSTART_DEFAULT (_UART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMECMP0 */ +#define UART_TIMECMP0_TSTART_DISABLE (_UART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMECMP0 */ +#define UART_TIMECMP0_TSTART_TXEOF (_UART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for UART_TIMECMP0 */ +#define UART_TIMECMP0_TSTART_TXC (_UART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for UART_TIMECMP0 */ +#define UART_TIMECMP0_TSTART_RXACT (_UART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for UART_TIMECMP0 */ +#define UART_TIMECMP0_TSTART_RXEOF (_UART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _UART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _UART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for UART_TIMECMP0 */ +#define _UART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for UART_TIMECMP0 */ +#define UART_TIMECMP0_TSTOP_DEFAULT (_UART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMECMP0 */ +#define UART_TIMECMP0_TSTOP_TCMP0 (_UART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for UART_TIMECMP0 */ +#define UART_TIMECMP0_TSTOP_TXST (_UART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for UART_TIMECMP0 */ +#define UART_TIMECMP0_TSTOP_RXACT (_UART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for UART_TIMECMP0 */ +#define UART_TIMECMP0_TSTOP_RXACTN (_UART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for UART_TIMECMP0 */ +#define UART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _UART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _UART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _UART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP0 */ +#define UART_TIMECMP0_RESTARTEN_DEFAULT (_UART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMECMP0 */ + +/* Bit fields for UART TIMECMP1 */ +#define _UART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for UART_TIMECMP1 */ +#define _UART_TIMECMP1_MASK 0x017700FFUL /**< Mask for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _UART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _UART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */ +#define UART_TIMECMP1_TCMPVAL_DEFAULT (_UART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _UART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _UART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for UART_TIMECMP1 */ +#define UART_TIMECMP1_TSTART_DEFAULT (_UART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMECMP1 */ +#define UART_TIMECMP1_TSTART_DISABLE (_UART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMECMP1 */ +#define UART_TIMECMP1_TSTART_TXEOF (_UART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for UART_TIMECMP1 */ +#define UART_TIMECMP1_TSTART_TXC (_UART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for UART_TIMECMP1 */ +#define UART_TIMECMP1_TSTART_RXACT (_UART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for UART_TIMECMP1 */ +#define UART_TIMECMP1_TSTART_RXEOF (_UART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _UART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _UART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for UART_TIMECMP1 */ +#define _UART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for UART_TIMECMP1 */ +#define UART_TIMECMP1_TSTOP_DEFAULT (_UART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMECMP1 */ +#define UART_TIMECMP1_TSTOP_TCMP1 (_UART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for UART_TIMECMP1 */ +#define UART_TIMECMP1_TSTOP_TXST (_UART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for UART_TIMECMP1 */ +#define UART_TIMECMP1_TSTOP_RXACT (_UART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for UART_TIMECMP1 */ +#define UART_TIMECMP1_TSTOP_RXACTN (_UART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for UART_TIMECMP1 */ +#define UART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _UART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _UART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _UART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP1 */ +#define UART_TIMECMP1_RESTARTEN_DEFAULT (_UART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMECMP1 */ + +/* Bit fields for UART TIMECMP2 */ +#define _UART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for UART_TIMECMP2 */ +#define _UART_TIMECMP2_MASK 0x017700FFUL /**< Mask for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _UART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _UART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */ +#define UART_TIMECMP2_TCMPVAL_DEFAULT (_UART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _UART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _UART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for UART_TIMECMP2 */ +#define UART_TIMECMP2_TSTART_DEFAULT (_UART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TIMECMP2 */ +#define UART_TIMECMP2_TSTART_DISABLE (_UART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for UART_TIMECMP2 */ +#define UART_TIMECMP2_TSTART_TXEOF (_UART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for UART_TIMECMP2 */ +#define UART_TIMECMP2_TSTART_TXC (_UART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for UART_TIMECMP2 */ +#define UART_TIMECMP2_TSTART_RXACT (_UART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for UART_TIMECMP2 */ +#define UART_TIMECMP2_TSTART_RXEOF (_UART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _UART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _UART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for UART_TIMECMP2 */ +#define _UART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for UART_TIMECMP2 */ +#define UART_TIMECMP2_TSTOP_DEFAULT (_UART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_TIMECMP2 */ +#define UART_TIMECMP2_TSTOP_TCMP2 (_UART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for UART_TIMECMP2 */ +#define UART_TIMECMP2_TSTOP_TXST (_UART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for UART_TIMECMP2 */ +#define UART_TIMECMP2_TSTOP_RXACT (_UART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for UART_TIMECMP2 */ +#define UART_TIMECMP2_TSTOP_RXACTN (_UART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for UART_TIMECMP2 */ +#define UART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _UART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _UART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _UART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TIMECMP2 */ +#define UART_TIMECMP2_RESTARTEN_DEFAULT (_UART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_TIMECMP2 */ + +/* Bit fields for UART ROUTEPEN */ +#define _UART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTEPEN */ +#define _UART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for UART_ROUTEPEN */ +#define UART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ +#define _UART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ +#define _UART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ +#define _UART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ +#define UART_ROUTEPEN_RXPEN_DEFAULT (_UART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ +#define UART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ +#define _UART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ +#define _UART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ +#define _UART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ +#define UART_ROUTEPEN_TXPEN_DEFAULT (_UART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ +#define UART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */ +#define _UART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ +#define _UART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ +#define _UART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ +#define UART_ROUTEPEN_CSPEN_DEFAULT (_UART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ +#define UART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ +#define _UART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ +#define _UART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ +#define _UART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ +#define UART_ROUTEPEN_CLKPEN_DEFAULT (_UART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ +#define UART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */ +#define _UART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */ +#define _UART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */ +#define _UART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ +#define UART_ROUTEPEN_CTSPEN_DEFAULT (_UART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ +#define UART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */ +#define _UART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */ +#define _UART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */ +#define _UART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTEPEN */ +#define UART_ROUTEPEN_RTSPEN_DEFAULT (_UART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_ROUTEPEN */ + +/* Bit fields for UART ROUTELOC0 */ +#define _UART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_MASK 0x07070707UL /**< Mask for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */ +#define _UART_ROUTELOC0_RXLOC_MASK 0x7UL /**< Bit mask for USART_RXLOC */ +#define _UART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_RXLOC_LOC0 (_UART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_RXLOC_DEFAULT (_UART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_RXLOC_LOC1 (_UART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_RXLOC_LOC2 (_UART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_RXLOC_LOC3 (_UART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_RXLOC_LOC4 (_UART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_RXLOC_LOC5 (_UART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_RXLOC_LOC6 (_UART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */ +#define _UART_ROUTELOC0_TXLOC_MASK 0x700UL /**< Bit mask for USART_TXLOC */ +#define _UART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_TXLOC_LOC0 (_UART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_TXLOC_DEFAULT (_UART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_TXLOC_LOC1 (_UART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_TXLOC_LOC2 (_UART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_TXLOC_LOC3 (_UART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_TXLOC_LOC4 (_UART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_TXLOC_LOC5 (_UART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_TXLOC_LOC6 (_UART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */ +#define _UART_ROUTELOC0_CSLOC_MASK 0x70000UL /**< Bit mask for USART_CSLOC */ +#define _UART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CSLOC_LOC0 (_UART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CSLOC_DEFAULT (_UART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CSLOC_LOC1 (_UART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CSLOC_LOC2 (_UART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CSLOC_LOC3 (_UART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CSLOC_LOC4 (_UART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CSLOC_LOC5 (_UART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CSLOC_LOC6 (_UART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */ +#define _UART_ROUTELOC0_CLKLOC_MASK 0x7000000UL /**< Bit mask for USART_CLKLOC */ +#define _UART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC0 */ +#define _UART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CLKLOC_LOC0 (_UART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CLKLOC_DEFAULT (_UART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CLKLOC_LOC1 (_UART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CLKLOC_LOC2 (_UART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CLKLOC_LOC3 (_UART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CLKLOC_LOC4 (_UART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CLKLOC_LOC5 (_UART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for UART_ROUTELOC0 */ +#define UART_ROUTELOC0_CLKLOC_LOC6 (_UART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for UART_ROUTELOC0 */ + +/* Bit fields for UART ROUTELOC1 */ +#define _UART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_MASK 0x00000707UL /**< Mask for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */ +#define _UART_ROUTELOC1_CTSLOC_MASK 0x7UL /**< Bit mask for USART_CTSLOC */ +#define _UART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_CTSLOC_LOC0 (_UART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_CTSLOC_DEFAULT (_UART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_CTSLOC_LOC1 (_UART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_CTSLOC_LOC2 (_UART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_CTSLOC_LOC3 (_UART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_CTSLOC_LOC4 (_UART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_CTSLOC_LOC5 (_UART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_CTSLOC_LOC6 (_UART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */ +#define _UART_ROUTELOC1_RTSLOC_MASK 0x700UL /**< Bit mask for USART_RTSLOC */ +#define _UART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTELOC1 */ +#define _UART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_RTSLOC_LOC0 (_UART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_RTSLOC_DEFAULT (_UART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_RTSLOC_LOC1 (_UART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_RTSLOC_LOC2 (_UART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_RTSLOC_LOC3 (_UART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_RTSLOC_LOC4 (_UART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_RTSLOC_LOC5 (_UART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for UART_ROUTELOC1 */ +#define UART_ROUTELOC1_RTSLOC_LOC6 (_UART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for UART_ROUTELOC1 */ + +/** @} */ +/** @} End of group EFM32GG11B_UART */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usart.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usart.h new file mode 100644 index 0000000000000..0ff2ec0648e94 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usart.h @@ -0,0 +1,1784 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_USART register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_USART USART + * @{ + * @brief EFM32GG11B_USART Register Declaration + ******************************************************************************/ +/** USART Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t INPUT; /**< USART Input Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Used to Generate Interrupts and Various Delays */ + __IOM uint32_t TIMECMP1; /**< Used to Generate Interrupts and Various Delays */ + __IOM uint32_t TIMECMP2; /**< Used to Generate Interrupts and Various Delays */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ +} USART_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_USART + * @{ + * @defgroup EFM32GG11B_USART_BitFields USART Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge for Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action on Slave-Select in Master Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter Output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA on Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX on Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX on Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap in Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x001F1FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */ +#define _USART_TRIGCTRL_TSEL_MASK 0x1F0000UL /**< Bit mask for USART_TSEL */ +#define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH12 (_USART_TRIGCTRL_TSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH13 (_USART_TRIGCTRL_TSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH14 (_USART_TRIGCTRL_TSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH15 (_USART_TRIGCTRL_TSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH16 (_USART_TRIGCTRL_TSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH17 (_USART_TRIGCTRL_TSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH18 (_USART_TRIGCTRL_TSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH19 (_USART_TRIGCTRL_TSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH20 (_USART_TRIGCTRL_TSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH21 (_USART_TRIGCTRL_TSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH22 (_USART_TRIGCTRL_TSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH23 (_USART_TRIGCTRL_TSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer Restarted Itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD Detection Enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data as Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data as Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select in Master Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer Comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer Comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer Comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IFS */ +#define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */ +#define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */ +#define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ +#define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */ +#define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */ +#define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */ +#define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */ +#define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */ +#define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */ +#define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */ +#define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */ +#define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */ +#define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */ +#define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */ +#define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */ +#define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */ +#define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */ +#define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */ + +/* Bit fields for USART IFC */ +#define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */ +#define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */ +#define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ +#define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */ +#define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */ +#define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */ +#define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */ +#define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */ +#define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */ +#define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */ +#define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */ +#define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */ +#define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */ +#define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */ +#define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */ +#define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */ +#define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */ +#define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x00001F8FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ +#define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ +#define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ +#define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */ +#define _USART_IRCTRL_IRPRSSEL_MASK 0x1F00UL /**< Bit mask for USART_IRPRSSEL */ +#define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH12 (_USART_IRCTRL_IRPRSSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH13 (_USART_IRCTRL_IRPRSSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH14 (_USART_IRCTRL_IRPRSSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH15 (_USART_IRCTRL_IRPRSSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH16 (_USART_IRCTRL_IRPRSSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH17 (_USART_IRCTRL_IRPRSSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH18 (_USART_IRCTRL_IRPRSSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH19 (_USART_IRCTRL_IRPRSSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH20 (_USART_IRCTRL_IRPRSSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH21 (_USART_IRCTRL_IRPRSSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH22 (_USART_IRCTRL_IRPRSSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH23 (_USART_IRCTRL_IRPRSSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for USART_IRCTRL */ + +/* Bit fields for USART INPUT */ +#define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */ +#define _USART_INPUT_MASK 0x00009F9FUL /**< Mask for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ +#define _USART_INPUT_RXPRSSEL_MASK 0x1FUL /**< Bit mask for USART_RXPRSSEL */ +#define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH12 (_USART_INPUT_RXPRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH13 (_USART_INPUT_RXPRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH14 (_USART_INPUT_RXPRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH15 (_USART_INPUT_RXPRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH16 (_USART_INPUT_RXPRSSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH17 (_USART_INPUT_RXPRSSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH18 (_USART_INPUT_RXPRSSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH19 (_USART_INPUT_RXPRSSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH20 (_USART_INPUT_RXPRSSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH21 (_USART_INPUT_RXPRSSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH22 (_USART_INPUT_RXPRSSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH23 (_USART_INPUT_RXPRSSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for USART_INPUT */ +#define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */ +#define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */ +#define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */ +#define _USART_INPUT_CLKPRSSEL_MASK 0x1F00UL /**< Bit mask for USART_CLKPRSSEL */ +#define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH12 (_USART_INPUT_CLKPRSSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH13 (_USART_INPUT_CLKPRSSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH14 (_USART_INPUT_CLKPRSSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH15 (_USART_INPUT_CLKPRSSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH16 (_USART_INPUT_CLKPRSSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH17 (_USART_INPUT_CLKPRSSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH18 (_USART_INPUT_CLKPRSSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH19 (_USART_INPUT_CLKPRSSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH20 (_USART_INPUT_CLKPRSSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH21 (_USART_INPUT_CLKPRSSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH22 (_USART_INPUT_CLKPRSSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH23 (_USART_INPUT_CLKPRSSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for USART_INPUT */ +#define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */ +#define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */ +#define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request for Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S Data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug Halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function Enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ + +/* Bit fields for USART ROUTEPEN */ +#define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */ +#define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ +#define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ +#define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ +#define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ +#define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ +#define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ +#define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */ +#define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ +#define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ +#define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ +#define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ +#define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ +#define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */ +#define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */ +#define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */ +#define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */ +#define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */ +#define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */ +#define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ + +/* Bit fields for USART ROUTELOC0 */ +#define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_MASK 0x07070707UL /**< Mask for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */ +#define _USART_ROUTELOC0_RXLOC_MASK 0x7UL /**< Bit mask for USART_RXLOC */ +#define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */ +#define _USART_ROUTELOC0_TXLOC_MASK 0x700UL /**< Bit mask for USART_TXLOC */ +#define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */ +#define _USART_ROUTELOC0_CSLOC_MASK 0x70000UL /**< Bit mask for USART_CSLOC */ +#define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */ +#define _USART_ROUTELOC0_CLKLOC_MASK 0x7000000UL /**< Bit mask for USART_CLKLOC */ +#define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ + +/* Bit fields for USART ROUTELOC1 */ +#define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_MASK 0x00000707UL /**< Mask for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */ +#define _USART_ROUTELOC1_CTSLOC_MASK 0x7UL /**< Bit mask for USART_CTSLOC */ +#define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */ +#define _USART_ROUTELOC1_RTSLOC_MASK 0x700UL /**< Bit mask for USART_RTSLOC */ +#define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ + +/** @} */ +/** @} End of group EFM32GG11B_USART */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb.h new file mode 100644 index 0000000000000..c09d63690d0c2 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb.h @@ -0,0 +1,3115 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_USB register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_USB USB + * @{ + * @brief EFM32GG11B_USB Register Declaration + ******************************************************************************/ +/** USB Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< System Control Register */ + __IM uint32_t STATUS; /**< System Status Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t ROUTE; /**< I/O Routing Register */ + + uint32_t RESERVED0[4U]; /**< Reserved for future use **/ + __IOM uint32_t CDCONF; /**< Charger Detect Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t DATTRIM1; /**< Data TRIM 1 Values for USB DP and DM */ + + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t LEMCTRL; /**< USB LEM Control Register */ + + uint32_t RESERVED2[227312U]; /**< Reserved for future use **/ + __IOM uint32_t GOTGCTL; /**< OTG Control and Status Register */ + __IOM uint32_t GOTGINT; /**< OTG Interrupt Register */ + __IOM uint32_t GAHBCFG; /**< AHB Configuration Register */ + __IOM uint32_t GUSBCFG; /**< USB Configuration Register */ + __IOM uint32_t GRSTCTL; /**< Reset Register */ + __IOM uint32_t GINTSTS; /**< Interrupt Register */ + __IOM uint32_t GINTMSK; /**< Interrupt Mask Register */ + __IM uint32_t GRXSTSR; /**< Receive Status Debug Read Register */ + __IM uint32_t GRXSTSP; /**< Receive Status Read /Pop Register */ + __IOM uint32_t GRXFSIZ; /**< Receive FIFO Size Register */ + __IOM uint32_t GNPTXFSIZ; /**< Non-periodic Transmit FIFO Size Register */ + __IM uint32_t GNPTXSTS; /**< Non-periodic Transmit FIFO/Queue Status Register */ + uint32_t RESERVED3[4U]; /**< Reserved for future use **/ + __IM uint32_t GSNPSID; /**< Synopsys ID Register */ + + uint32_t RESERVED4[6U]; /**< Reserved for future use **/ + __IOM uint32_t GDFIFOCFG; /**< Global DFIFO Configuration Register */ + + uint32_t RESERVED5[40U]; /**< Reserved for future use **/ + __IOM uint32_t HPTXFSIZ; /**< Host Periodic Transmit FIFO Size Register */ + __IOM uint32_t DIEPTXF1; /**< Device IN Endpoint Transmit FIFO Size Register 1 */ + __IOM uint32_t DIEPTXF2; /**< Device IN Endpoint Transmit FIFO Size Register 2 */ + __IOM uint32_t DIEPTXF3; /**< Device IN Endpoint Transmit FIFO Size Register 3 */ + __IOM uint32_t DIEPTXF4; /**< Device IN Endpoint Transmit FIFO Size Register 4 */ + __IOM uint32_t DIEPTXF5; /**< Device IN Endpoint Transmit FIFO Size Register 5 */ + __IOM uint32_t DIEPTXF6; /**< Device IN Endpoint Transmit FIFO Size Register 6 */ + + uint32_t RESERVED6[185U]; /**< Reserved for future use **/ + __IOM uint32_t HCFG; /**< Host Configuration Register */ + __IOM uint32_t HFIR; /**< Host Frame Interval Register */ + __IM uint32_t HFNUM; /**< Host Frame Number/Frame Time Remaining Register */ + uint32_t RESERVED7[1U]; /**< Reserved for future use **/ + __IM uint32_t HPTXSTS; /**< Host Periodic Transmit FIFO/Queue Status Register */ + __IM uint32_t HAINT; /**< Host All Channels Interrupt Register */ + __IOM uint32_t HAINTMSK; /**< Host All Channels Interrupt Mask Register */ + uint32_t RESERVED8[9U]; /**< Reserved for future use **/ + __IOM uint32_t HPRT; /**< Host Port Control and Status Register */ + + uint32_t RESERVED9[47U]; /**< Reserved registers */ + USB_HC_TypeDef HC[14U]; /**< Host Channel Registers */ + + uint32_t RESERVED10[80U]; /**< Reserved for future use **/ + __IOM uint32_t DCFG; /**< Device Configuration Register */ + __IOM uint32_t DCTL; /**< Device Control Register */ + __IM uint32_t DSTS; /**< Device Status Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use **/ + __IOM uint32_t DIEPMSK; /**< Device IN Endpoint Common Interrupt Mask Register */ + __IOM uint32_t DOEPMSK; /**< Device OUT Endpoint Common Interrupt Mask Register */ + __IM uint32_t DAINT; /**< Device All Endpoints Interrupt Register */ + __IOM uint32_t DAINTMSK; /**< Device All Endpoints Interrupt Mask Register */ + uint32_t RESERVED12[2U]; /**< Reserved for future use **/ + __IOM uint32_t DVBUSDIS; /**< Device VBUS Discharge Time Register */ + __IOM uint32_t DVBUSPULSE; /**< Device VBUS Pulsing Time Register */ + __IOM uint32_t DTHRCTL; /**< Device Threshold Control Register */ + __IOM uint32_t DIEPEMPMSK; /**< Device IN Endpoint FIFO Empty Interrupt Mask Register */ + + uint32_t RESERVED13[50U]; /**< Reserved for future use **/ + __IOM uint32_t DIEP0CTL; /**< Device Control IN Endpoint 0 Control Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use **/ + __IOM uint32_t DIEP0INT; /**< Device IN Endpoint 0 Interrupt Register */ + uint32_t RESERVED15[1U]; /**< Reserved for future use **/ + __IOM uint32_t DIEP0TSIZ; /**< Device IN Endpoint 0 Transfer Size Register */ + __IOM uint32_t DIEP0DMAADDR; /**< Device IN Endpoint 0 DMA Address Register */ + __IM uint32_t DIEP0TXFSTS; /**< Device IN Endpoint Transmit FIFO Status Register 0 */ + + uint32_t RESERVED16[1U]; /**< Reserved registers */ + USB_DIEP_TypeDef DIEP[6U]; /**< Device IN Endpoint n Registers */ + + uint32_t RESERVED17[72U]; /**< Reserved for future use **/ + __IOM uint32_t DOEP0CTL; /**< Device Control OUT Endpoint 0 Control Register */ + uint32_t RESERVED18[1U]; /**< Reserved for future use **/ + __IOM uint32_t DOEP0INT; /**< Device OUT Endpoint 0 Interrupt Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use **/ + __IOM uint32_t DOEP0TSIZ; /**< Device OUT Endpoint 0 Transfer Size Register */ + __IOM uint32_t DOEP0DMAADDR; /**< Device OUT Endpoint 0 DMA Address Register */ + + uint32_t RESERVED20[2U]; /**< Reserved registers */ + USB_DOEP_TypeDef DOEP[6U]; /**< Device OUT Endpoint n Registers */ + + uint32_t RESERVED21[136U]; /**< Reserved for future use **/ + __IOM uint32_t PCGCCTL; /**< Power and Clock Gating Control Register */ + + uint32_t RESERVED22[127U]; /**< Reserved registers */ + __IOM uint32_t FIFO0D[512U]; /**< Device EP 0/Host Channel 0 FIFO */ + + uint32_t RESERVED23[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO1D[512U]; /**< Device EP 1/Host Channel 1 FIFO */ + + uint32_t RESERVED24[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO2D[512U]; /**< Device EP 2/Host Channel 2 FIFO */ + + uint32_t RESERVED25[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO3D[512U]; /**< Device EP 3/Host Channel 3 FIFO */ + + uint32_t RESERVED26[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO4D[512U]; /**< Device EP 4/Host Channel 4 FIFO */ + + uint32_t RESERVED27[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO5D[512U]; /**< Device EP 5/Host Channel 5 FIFO */ + + uint32_t RESERVED28[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO6D[512U]; /**< Device EP 6/Host Channel 6 FIFO */ + + uint32_t RESERVED29[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO7D[512U]; /**< Host Channel 7 FIFO */ + + uint32_t RESERVED30[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO8D[512U]; /**< Host Channel 8 FIFO */ + + uint32_t RESERVED31[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO9D[512U]; /**< Host Channel 9 FIFO */ + + uint32_t RESERVED32[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO10D[512U]; /**< Host Channel 10 FIFO */ + + uint32_t RESERVED33[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO11D[512U]; /**< Host Channel 11 FIFO */ + + uint32_t RESERVED34[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO12D[512U]; /**< Host Channel 12 FIFO */ + + uint32_t RESERVED35[512U]; /**< Reserved registers */ + __IOM uint32_t FIFO13D[512U]; /**< Host Channel 13 FIFO */ + + uint32_t RESERVED36[17920U]; /**< Reserved registers */ + __IOM uint32_t FIFORAM[512U]; /**< Direct Access to Data FIFO RAM for Debugging (2 KB) */ +} USB_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_USB + * @{ + * @defgroup EFM32GG11B_USB_BitFields USB Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for USB CTRL */ +#define _USB_CTRL_RESETVALUE 0x00000020UL /**< Default value for USB_CTRL */ +#define _USB_CTRL_MASK 0xFE0012B9UL /**< Mask for USB_CTRL */ +#define USB_CTRL_VBUSENAP (0x1UL << 0) /**< VBUSEN Active Polarity */ +#define _USB_CTRL_VBUSENAP_SHIFT 0 /**< Shift value for USB_VBUSENAP */ +#define _USB_CTRL_VBUSENAP_MASK 0x1UL /**< Bit mask for USB_VBUSENAP */ +#define _USB_CTRL_VBUSENAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_VBUSENAP_HIGH 0x00000000UL /**< Mode HIGH for USB_CTRL */ +#define _USB_CTRL_VBUSENAP_LOW 0x00000001UL /**< Mode LOW for USB_CTRL */ +#define USB_CTRL_VBUSENAP_DEFAULT (_USB_CTRL_VBUSENAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_VBUSENAP_HIGH (_USB_CTRL_VBUSENAP_HIGH << 0) /**< Shifted mode HIGH for USB_CTRL */ +#define USB_CTRL_VBUSENAP_LOW (_USB_CTRL_VBUSENAP_LOW << 0) /**< Shifted mode LOW for USB_CTRL */ +#define USB_CTRL_SELFPOWERED (0x1UL << 3) /**< PHY Power */ +#define _USB_CTRL_SELFPOWERED_SHIFT 3 /**< Shift value for USB_SELFPOWERED */ +#define _USB_CTRL_SELFPOWERED_MASK 0x8UL /**< Bit mask for USB_SELFPOWERED */ +#define _USB_CTRL_SELFPOWERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_SELFPOWERED_LOW 0x00000000UL /**< Mode LOW for USB_CTRL */ +#define _USB_CTRL_SELFPOWERED_HIGH 0x00000001UL /**< Mode HIGH for USB_CTRL */ +#define USB_CTRL_SELFPOWERED_DEFAULT (_USB_CTRL_SELFPOWERED_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_SELFPOWERED_LOW (_USB_CTRL_SELFPOWERED_LOW << 3) /**< Shifted mode LOW for USB_CTRL */ +#define USB_CTRL_SELFPOWERED_HIGH (_USB_CTRL_SELFPOWERED_HIGH << 3) /**< Shifted mode HIGH for USB_CTRL */ +#define _USB_CTRL_LEMOSCCTRL_SHIFT 4 /**< Shift value for USB_LEMOSCCTRL */ +#define _USB_CTRL_LEMOSCCTRL_MASK 0x30UL /**< Bit mask for USB_LEMOSCCTRL */ +#define _USB_CTRL_LEMOSCCTRL_NONE 0x00000000UL /**< Mode NONE for USB_CTRL */ +#define _USB_CTRL_LEMOSCCTRL_GATE 0x00000001UL /**< Mode GATE for USB_CTRL */ +#define _USB_CTRL_LEMOSCCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for USB_CTRL */ +#define USB_CTRL_LEMOSCCTRL_NONE (_USB_CTRL_LEMOSCCTRL_NONE << 4) /**< Shifted mode NONE for USB_CTRL */ +#define USB_CTRL_LEMOSCCTRL_GATE (_USB_CTRL_LEMOSCCTRL_GATE << 4) /**< Shifted mode GATE for USB_CTRL */ +#define USB_CTRL_LEMOSCCTRL_DEFAULT (_USB_CTRL_LEMOSCCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_LEMPHYCTRL (0x1UL << 7) /**< Low Energy Mode USB PHY Control */ +#define _USB_CTRL_LEMPHYCTRL_SHIFT 7 /**< Shift value for USB_LEMPHYCTRL */ +#define _USB_CTRL_LEMPHYCTRL_MASK 0x80UL /**< Bit mask for USB_LEMPHYCTRL */ +#define _USB_CTRL_LEMPHYCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_LEMPHYCTRL_NONE 0x00000000UL /**< Mode NONE for USB_CTRL */ +#define _USB_CTRL_LEMPHYCTRL_LEM 0x00000001UL /**< Mode LEM for USB_CTRL */ +#define USB_CTRL_LEMPHYCTRL_DEFAULT (_USB_CTRL_LEMPHYCTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_LEMPHYCTRL_NONE (_USB_CTRL_LEMPHYCTRL_NONE << 7) /**< Shifted mode NONE for USB_CTRL */ +#define USB_CTRL_LEMPHYCTRL_LEM (_USB_CTRL_LEMPHYCTRL_LEM << 7) /**< Shifted mode LEM for USB_CTRL */ +#define USB_CTRL_LEMIDLEEN (0x1UL << 9) /**< Low Energy Mode on Bus Idle Enable */ +#define _USB_CTRL_LEMIDLEEN_SHIFT 9 /**< Shift value for USB_LEMIDLEEN */ +#define _USB_CTRL_LEMIDLEEN_MASK 0x200UL /**< Bit mask for USB_LEMIDLEEN */ +#define _USB_CTRL_LEMIDLEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ +#define USB_CTRL_LEMIDLEEN_DEFAULT (_USB_CTRL_LEMIDLEEN_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_IDCDEN (0x1UL << 12) /**< ID Pull-up Enable */ +#define _USB_CTRL_IDCDEN_SHIFT 12 /**< Shift value for USB_IDCDEN */ +#define _USB_CTRL_IDCDEN_MASK 0x1000UL /**< Bit mask for USB_IDCDEN */ +#define _USB_CTRL_IDCDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_IDCDEN_DISABLED 0x00000000UL /**< Mode DISABLED for USB_CTRL */ +#define _USB_CTRL_IDCDEN_ENABLED 0x00000001UL /**< Mode ENABLED for USB_CTRL */ +#define USB_CTRL_IDCDEN_DEFAULT (_USB_CTRL_IDCDEN_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_IDCDEN_DISABLED (_USB_CTRL_IDCDEN_DISABLED << 12) /**< Shifted mode DISABLED for USB_CTRL */ +#define USB_CTRL_IDCDEN_ENABLED (_USB_CTRL_IDCDEN_ENABLED << 12) /**< Shifted mode ENABLED for USB_CTRL */ +#define USB_CTRL_OTGCLKCDIS (0x1UL << 25) /**< OTG CLKC Disable */ +#define _USB_CTRL_OTGCLKCDIS_SHIFT 25 /**< Shift value for USB_OTGCLKCDIS */ +#define _USB_CTRL_OTGCLKCDIS_MASK 0x2000000UL /**< Bit mask for USB_OTGCLKCDIS */ +#define _USB_CTRL_OTGCLKCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_OTGCLKCDIS_ENABLED 0x00000000UL /**< Mode ENABLED for USB_CTRL */ +#define _USB_CTRL_OTGCLKCDIS_DISABLED 0x00000001UL /**< Mode DISABLED for USB_CTRL */ +#define USB_CTRL_OTGCLKCDIS_DEFAULT (_USB_CTRL_OTGCLKCDIS_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_OTGCLKCDIS_ENABLED (_USB_CTRL_OTGCLKCDIS_ENABLED << 25) /**< Shifted mode ENABLED for USB_CTRL */ +#define USB_CTRL_OTGCLKCDIS_DISABLED (_USB_CTRL_OTGCLKCDIS_DISABLED << 25) /**< Shifted mode DISABLED for USB_CTRL */ +#define USB_CTRL_OTGIDINDIS (0x1UL << 26) /**< OTG ID Input Disable */ +#define _USB_CTRL_OTGIDINDIS_SHIFT 26 /**< Shift value for USB_OTGIDINDIS */ +#define _USB_CTRL_OTGIDINDIS_MASK 0x4000000UL /**< Bit mask for USB_OTGIDINDIS */ +#define _USB_CTRL_OTGIDINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_OTGIDINDIS_ENABLED 0x00000000UL /**< Mode ENABLED for USB_CTRL */ +#define _USB_CTRL_OTGIDINDIS_DISABLED 0x00000001UL /**< Mode DISABLED for USB_CTRL */ +#define USB_CTRL_OTGIDINDIS_DEFAULT (_USB_CTRL_OTGIDINDIS_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_OTGIDINDIS_ENABLED (_USB_CTRL_OTGIDINDIS_ENABLED << 26) /**< Shifted mode ENABLED for USB_CTRL */ +#define USB_CTRL_OTGIDINDIS_DISABLED (_USB_CTRL_OTGIDINDIS_DISABLED << 26) /**< Shifted mode DISABLED for USB_CTRL */ +#define USB_CTRL_OTGPHYCTRLDIS (0x1UL << 27) /**< OTG Control Signals to PHY Disable */ +#define _USB_CTRL_OTGPHYCTRLDIS_SHIFT 27 /**< Shift value for USB_OTGPHYCTRLDIS */ +#define _USB_CTRL_OTGPHYCTRLDIS_MASK 0x8000000UL /**< Bit mask for USB_OTGPHYCTRLDIS */ +#define _USB_CTRL_OTGPHYCTRLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_OTGPHYCTRLDIS_ENABLED 0x00000000UL /**< Mode ENABLED for USB_CTRL */ +#define _USB_CTRL_OTGPHYCTRLDIS_DISABLED 0x00000001UL /**< Mode DISABLED for USB_CTRL */ +#define USB_CTRL_OTGPHYCTRLDIS_DEFAULT (_USB_CTRL_OTGPHYCTRLDIS_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_OTGPHYCTRLDIS_ENABLED (_USB_CTRL_OTGPHYCTRLDIS_ENABLED << 27) /**< Shifted mode ENABLED for USB_CTRL */ +#define USB_CTRL_OTGPHYCTRLDIS_DISABLED (_USB_CTRL_OTGPHYCTRLDIS_DISABLED << 27) /**< Shifted mode DISABLED for USB_CTRL */ +#define _USB_CTRL_DCDEN_SHIFT 28 /**< Shift value for USB_DCDEN */ +#define _USB_CTRL_DCDEN_MASK 0x30000000UL /**< Bit mask for USB_DCDEN */ +#define _USB_CTRL_DCDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_DCDEN_DISABLED 0x00000000UL /**< Mode DISABLED for USB_CTRL */ +#define _USB_CTRL_DCDEN_TIMEOUT 0x00000002UL /**< Mode TIMEOUT for USB_CTRL */ +#define _USB_CTRL_DCDEN_ENABLED 0x00000003UL /**< Mode ENABLED for USB_CTRL */ +#define USB_CTRL_DCDEN_DEFAULT (_USB_CTRL_DCDEN_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_DCDEN_DISABLED (_USB_CTRL_DCDEN_DISABLED << 28) /**< Shifted mode DISABLED for USB_CTRL */ +#define USB_CTRL_DCDEN_TIMEOUT (_USB_CTRL_DCDEN_TIMEOUT << 28) /**< Shifted mode TIMEOUT for USB_CTRL */ +#define USB_CTRL_DCDEN_ENABLED (_USB_CTRL_DCDEN_ENABLED << 28) /**< Shifted mode ENABLED for USB_CTRL */ +#define USB_CTRL_PDEN (0x1UL << 30) /**< Primary Detection Enable */ +#define _USB_CTRL_PDEN_SHIFT 30 /**< Shift value for USB_PDEN */ +#define _USB_CTRL_PDEN_MASK 0x40000000UL /**< Bit mask for USB_PDEN */ +#define _USB_CTRL_PDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_PDEN_DISABLED 0x00000000UL /**< Mode DISABLED for USB_CTRL */ +#define _USB_CTRL_PDEN_ENABLED 0x00000001UL /**< Mode ENABLED for USB_CTRL */ +#define USB_CTRL_PDEN_DEFAULT (_USB_CTRL_PDEN_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_PDEN_DISABLED (_USB_CTRL_PDEN_DISABLED << 30) /**< Shifted mode DISABLED for USB_CTRL */ +#define USB_CTRL_PDEN_ENABLED (_USB_CTRL_PDEN_ENABLED << 30) /**< Shifted mode ENABLED for USB_CTRL */ +#define USB_CTRL_SDEN (0x1UL << 31) /**< Secondary Detection Enable */ +#define _USB_CTRL_SDEN_SHIFT 31 /**< Shift value for USB_SDEN */ +#define _USB_CTRL_SDEN_MASK 0x80000000UL /**< Bit mask for USB_SDEN */ +#define _USB_CTRL_SDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_SDEN_DISABLED 0x00000000UL /**< Mode DISABLED for USB_CTRL */ +#define _USB_CTRL_SDEN_ENABLED 0x00000001UL /**< Mode ENABLED for USB_CTRL */ +#define USB_CTRL_SDEN_DEFAULT (_USB_CTRL_SDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_SDEN_DISABLED (_USB_CTRL_SDEN_DISABLED << 31) /**< Shifted mode DISABLED for USB_CTRL */ +#define USB_CTRL_SDEN_ENABLED (_USB_CTRL_SDEN_ENABLED << 31) /**< Shifted mode ENABLED for USB_CTRL */ + +/* Bit fields for USB STATUS */ +#define _USB_STATUS_RESETVALUE 0x00000000UL /**< Default value for USB_STATUS */ +#define _USB_STATUS_MASK 0x0000BF05UL /**< Mask for USB_STATUS */ +#define USB_STATUS_VBUSDETH (0x1UL << 0) /**< VBUS Detect High */ +#define _USB_STATUS_VBUSDETH_SHIFT 0 /**< Shift value for USB_VBUSDETH */ +#define _USB_STATUS_VBUSDETH_MASK 0x1UL /**< Bit mask for USB_VBUSDETH */ +#define _USB_STATUS_VBUSDETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ +#define USB_STATUS_VBUSDETH_DEFAULT (_USB_STATUS_VBUSDETH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_STATUS */ +#define USB_STATUS_LEMACTIVE (0x1UL << 2) /**< Low Energy Mode Active */ +#define _USB_STATUS_LEMACTIVE_SHIFT 2 /**< Shift value for USB_LEMACTIVE */ +#define _USB_STATUS_LEMACTIVE_MASK 0x4UL /**< Bit mask for USB_LEMACTIVE */ +#define _USB_STATUS_LEMACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ +#define USB_STATUS_LEMACTIVE_DEFAULT (_USB_STATUS_LEMACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_STATUS */ +#define USB_STATUS_DCDTO (0x1UL << 8) /**< Data Contact Detection Timeout */ +#define _USB_STATUS_DCDTO_SHIFT 8 /**< Shift value for USB_DCDTO */ +#define _USB_STATUS_DCDTO_MASK 0x100UL /**< Bit mask for USB_DCDTO */ +#define _USB_STATUS_DCDTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ +#define _USB_STATUS_DCDTO_NOTIME 0x00000000UL /**< Mode NOTIME for USB_STATUS */ +#define _USB_STATUS_DCDTO_TIMEOUT 0x00000001UL /**< Mode TIMEOUT for USB_STATUS */ +#define USB_STATUS_DCDTO_DEFAULT (_USB_STATUS_DCDTO_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_STATUS */ +#define USB_STATUS_DCDTO_NOTIME (_USB_STATUS_DCDTO_NOTIME << 8) /**< Shifted mode NOTIME for USB_STATUS */ +#define USB_STATUS_DCDTO_TIMEOUT (_USB_STATUS_DCDTO_TIMEOUT << 8) /**< Shifted mode TIMEOUT for USB_STATUS */ +#define USB_STATUS_SDP (0x1UL << 9) /**< Standard Downstream Port Detected */ +#define _USB_STATUS_SDP_SHIFT 9 /**< Shift value for USB_SDP */ +#define _USB_STATUS_SDP_MASK 0x200UL /**< Bit mask for USB_SDP */ +#define _USB_STATUS_SDP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ +#define USB_STATUS_SDP_DEFAULT (_USB_STATUS_SDP_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_STATUS */ +#define USB_STATUS_CDP (0x1UL << 10) /**< Charging Downstream Port Detected */ +#define _USB_STATUS_CDP_SHIFT 10 /**< Shift value for USB_CDP */ +#define _USB_STATUS_CDP_MASK 0x400UL /**< Bit mask for USB_CDP */ +#define _USB_STATUS_CDP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ +#define USB_STATUS_CDP_DEFAULT (_USB_STATUS_CDP_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_STATUS */ +#define USB_STATUS_DCP (0x1UL << 11) /**< Dedicated Charging Port Detected */ +#define _USB_STATUS_DCP_SHIFT 11 /**< Shift value for USB_DCP */ +#define _USB_STATUS_DCP_MASK 0x800UL /**< Bit mask for USB_DCP */ +#define _USB_STATUS_DCP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ +#define USB_STATUS_DCP_DEFAULT (_USB_STATUS_DCP_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_STATUS */ +#define USB_STATUS_ACAFS (0x1UL << 12) /**< ACA Full Speed TypeB Device */ +#define _USB_STATUS_ACAFS_SHIFT 12 /**< Shift value for USB_ACAFS */ +#define _USB_STATUS_ACAFS_MASK 0x1000UL /**< Bit mask for USB_ACAFS */ +#define _USB_STATUS_ACAFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ +#define USB_STATUS_ACAFS_DEFAULT (_USB_STATUS_ACAFS_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_STATUS */ +#define USB_STATUS_ACALS (0x1UL << 13) /**< ACA Low Speed TypeB Device */ +#define _USB_STATUS_ACALS_SHIFT 13 /**< Shift value for USB_ACALS */ +#define _USB_STATUS_ACALS_MASK 0x2000UL /**< Bit mask for USB_ACALS */ +#define _USB_STATUS_ACALS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ +#define USB_STATUS_ACALS_DEFAULT (_USB_STATUS_ACALS_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_STATUS */ +#define USB_STATUS_USBCDBUSY (0x1UL << 15) /**< USB Charger Detect Busy */ +#define _USB_STATUS_USBCDBUSY_SHIFT 15 /**< Shift value for USB_USBCDBUSY */ +#define _USB_STATUS_USBCDBUSY_MASK 0x8000UL /**< Bit mask for USB_USBCDBUSY */ +#define _USB_STATUS_USBCDBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ +#define USB_STATUS_USBCDBUSY_DEFAULT (_USB_STATUS_USBCDBUSY_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_STATUS */ + +/* Bit fields for USB IF */ +#define _USB_IF_RESETVALUE 0x00000000UL /**< Default value for USB_IF */ +#define _USB_IF_MASK 0x00000F03UL /**< Mask for USB_IF */ +#define USB_IF_VBUSDETH (0x1UL << 0) /**< VBUS Detect High Interrupt Flag */ +#define _USB_IF_VBUSDETH_SHIFT 0 /**< Shift value for USB_VBUSDETH */ +#define _USB_IF_VBUSDETH_MASK 0x1UL /**< Bit mask for USB_VBUSDETH */ +#define _USB_IF_VBUSDETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ +#define USB_IF_VBUSDETH_DEFAULT (_USB_IF_VBUSDETH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IF */ +#define USB_IF_VBUSDETL (0x1UL << 1) /**< VBUS Detect Low Interrupt Flag */ +#define _USB_IF_VBUSDETL_SHIFT 1 /**< Shift value for USB_VBUSDETL */ +#define _USB_IF_VBUSDETL_MASK 0x2UL /**< Bit mask for USB_VBUSDETL */ +#define _USB_IF_VBUSDETL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ +#define USB_IF_VBUSDETL_DEFAULT (_USB_IF_VBUSDETL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IF */ +#define USB_IF_ERR (0x1UL << 8) /**< Detection Error Interrupt Flag */ +#define _USB_IF_ERR_SHIFT 8 /**< Shift value for USB_ERR */ +#define _USB_IF_ERR_MASK 0x100UL /**< Bit mask for USB_ERR */ +#define _USB_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ +#define USB_IF_ERR_DEFAULT (_USB_IF_ERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_IF */ +#define USB_IF_DCD (0x1UL << 9) /**< Data Contact Detection Complete Interrupt Flag */ +#define _USB_IF_DCD_SHIFT 9 /**< Shift value for USB_DCD */ +#define _USB_IF_DCD_MASK 0x200UL /**< Bit mask for USB_DCD */ +#define _USB_IF_DCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ +#define USB_IF_DCD_DEFAULT (_USB_IF_DCD_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_IF */ +#define USB_IF_PD (0x1UL << 10) /**< Primary Detection Complete Interrupt Flag */ +#define _USB_IF_PD_SHIFT 10 /**< Shift value for USB_PD */ +#define _USB_IF_PD_MASK 0x400UL /**< Bit mask for USB_PD */ +#define _USB_IF_PD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ +#define USB_IF_PD_DEFAULT (_USB_IF_PD_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_IF */ +#define USB_IF_SD (0x1UL << 11) /**< Secondary Detection Complete Interrupt Flag */ +#define _USB_IF_SD_SHIFT 11 /**< Shift value for USB_SD */ +#define _USB_IF_SD_MASK 0x800UL /**< Bit mask for USB_SD */ +#define _USB_IF_SD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IF */ +#define USB_IF_SD_DEFAULT (_USB_IF_SD_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_IF */ + +/* Bit fields for USB IFS */ +#define _USB_IFS_RESETVALUE 0x00000000UL /**< Default value for USB_IFS */ +#define _USB_IFS_MASK 0x00000F03UL /**< Mask for USB_IFS */ +#define USB_IFS_VBUSDETH (0x1UL << 0) /**< Set VBUSDETH Interrupt Flag */ +#define _USB_IFS_VBUSDETH_SHIFT 0 /**< Shift value for USB_VBUSDETH */ +#define _USB_IFS_VBUSDETH_MASK 0x1UL /**< Bit mask for USB_VBUSDETH */ +#define _USB_IFS_VBUSDETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ +#define USB_IFS_VBUSDETH_DEFAULT (_USB_IFS_VBUSDETH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IFS */ +#define USB_IFS_VBUSDETL (0x1UL << 1) /**< Set VBUSDETL Interrupt Flag */ +#define _USB_IFS_VBUSDETL_SHIFT 1 /**< Shift value for USB_VBUSDETL */ +#define _USB_IFS_VBUSDETL_MASK 0x2UL /**< Bit mask for USB_VBUSDETL */ +#define _USB_IFS_VBUSDETL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ +#define USB_IFS_VBUSDETL_DEFAULT (_USB_IFS_VBUSDETL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IFS */ +#define USB_IFS_ERR (0x1UL << 8) /**< Set ERR Interrupt Flag */ +#define _USB_IFS_ERR_SHIFT 8 /**< Shift value for USB_ERR */ +#define _USB_IFS_ERR_MASK 0x100UL /**< Bit mask for USB_ERR */ +#define _USB_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ +#define USB_IFS_ERR_DEFAULT (_USB_IFS_ERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_IFS */ +#define USB_IFS_DCD (0x1UL << 9) /**< Set DCD Interrupt Flag */ +#define _USB_IFS_DCD_SHIFT 9 /**< Shift value for USB_DCD */ +#define _USB_IFS_DCD_MASK 0x200UL /**< Bit mask for USB_DCD */ +#define _USB_IFS_DCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ +#define USB_IFS_DCD_DEFAULT (_USB_IFS_DCD_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_IFS */ +#define USB_IFS_PD (0x1UL << 10) /**< Set PD Interrupt Flag */ +#define _USB_IFS_PD_SHIFT 10 /**< Shift value for USB_PD */ +#define _USB_IFS_PD_MASK 0x400UL /**< Bit mask for USB_PD */ +#define _USB_IFS_PD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ +#define USB_IFS_PD_DEFAULT (_USB_IFS_PD_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_IFS */ +#define USB_IFS_SD (0x1UL << 11) /**< Set SD Interrupt Flag */ +#define _USB_IFS_SD_SHIFT 11 /**< Shift value for USB_SD */ +#define _USB_IFS_SD_MASK 0x800UL /**< Bit mask for USB_SD */ +#define _USB_IFS_SD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ +#define USB_IFS_SD_DEFAULT (_USB_IFS_SD_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_IFS */ + +/* Bit fields for USB IFC */ +#define _USB_IFC_RESETVALUE 0x00000000UL /**< Default value for USB_IFC */ +#define _USB_IFC_MASK 0x00000F03UL /**< Mask for USB_IFC */ +#define USB_IFC_VBUSDETH (0x1UL << 0) /**< Clear VBUSDETH Interrupt Flag */ +#define _USB_IFC_VBUSDETH_SHIFT 0 /**< Shift value for USB_VBUSDETH */ +#define _USB_IFC_VBUSDETH_MASK 0x1UL /**< Bit mask for USB_VBUSDETH */ +#define _USB_IFC_VBUSDETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ +#define USB_IFC_VBUSDETH_DEFAULT (_USB_IFC_VBUSDETH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IFC */ +#define USB_IFC_VBUSDETL (0x1UL << 1) /**< Clear VBUSDETL Interrupt Flag */ +#define _USB_IFC_VBUSDETL_SHIFT 1 /**< Shift value for USB_VBUSDETL */ +#define _USB_IFC_VBUSDETL_MASK 0x2UL /**< Bit mask for USB_VBUSDETL */ +#define _USB_IFC_VBUSDETL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ +#define USB_IFC_VBUSDETL_DEFAULT (_USB_IFC_VBUSDETL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IFC */ +#define USB_IFC_ERR (0x1UL << 8) /**< Clear ERR Interrupt Flag */ +#define _USB_IFC_ERR_SHIFT 8 /**< Shift value for USB_ERR */ +#define _USB_IFC_ERR_MASK 0x100UL /**< Bit mask for USB_ERR */ +#define _USB_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ +#define USB_IFC_ERR_DEFAULT (_USB_IFC_ERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_IFC */ +#define USB_IFC_DCD (0x1UL << 9) /**< Clear DCD Interrupt Flag */ +#define _USB_IFC_DCD_SHIFT 9 /**< Shift value for USB_DCD */ +#define _USB_IFC_DCD_MASK 0x200UL /**< Bit mask for USB_DCD */ +#define _USB_IFC_DCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ +#define USB_IFC_DCD_DEFAULT (_USB_IFC_DCD_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_IFC */ +#define USB_IFC_PD (0x1UL << 10) /**< Clear PD Interrupt Flag */ +#define _USB_IFC_PD_SHIFT 10 /**< Shift value for USB_PD */ +#define _USB_IFC_PD_MASK 0x400UL /**< Bit mask for USB_PD */ +#define _USB_IFC_PD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ +#define USB_IFC_PD_DEFAULT (_USB_IFC_PD_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_IFC */ +#define USB_IFC_SD (0x1UL << 11) /**< Clear SD Interrupt Flag */ +#define _USB_IFC_SD_SHIFT 11 /**< Shift value for USB_SD */ +#define _USB_IFC_SD_MASK 0x800UL /**< Bit mask for USB_SD */ +#define _USB_IFC_SD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ +#define USB_IFC_SD_DEFAULT (_USB_IFC_SD_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_IFC */ + +/* Bit fields for USB IEN */ +#define _USB_IEN_RESETVALUE 0x00000000UL /**< Default value for USB_IEN */ +#define _USB_IEN_MASK 0x00000F03UL /**< Mask for USB_IEN */ +#define USB_IEN_VBUSDETH (0x1UL << 0) /**< VBUSDETH Interrupt Enable */ +#define _USB_IEN_VBUSDETH_SHIFT 0 /**< Shift value for USB_VBUSDETH */ +#define _USB_IEN_VBUSDETH_MASK 0x1UL /**< Bit mask for USB_VBUSDETH */ +#define _USB_IEN_VBUSDETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ +#define USB_IEN_VBUSDETH_DEFAULT (_USB_IEN_VBUSDETH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IEN */ +#define USB_IEN_VBUSDETL (0x1UL << 1) /**< VBUSDETL Interrupt Enable */ +#define _USB_IEN_VBUSDETL_SHIFT 1 /**< Shift value for USB_VBUSDETL */ +#define _USB_IEN_VBUSDETL_MASK 0x2UL /**< Bit mask for USB_VBUSDETL */ +#define _USB_IEN_VBUSDETL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ +#define USB_IEN_VBUSDETL_DEFAULT (_USB_IEN_VBUSDETL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IEN */ +#define USB_IEN_ERR (0x1UL << 8) /**< ERR Interrupt Enable */ +#define _USB_IEN_ERR_SHIFT 8 /**< Shift value for USB_ERR */ +#define _USB_IEN_ERR_MASK 0x100UL /**< Bit mask for USB_ERR */ +#define _USB_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ +#define USB_IEN_ERR_DEFAULT (_USB_IEN_ERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_IEN */ +#define USB_IEN_DCD (0x1UL << 9) /**< DCD Interrupt Enable */ +#define _USB_IEN_DCD_SHIFT 9 /**< Shift value for USB_DCD */ +#define _USB_IEN_DCD_MASK 0x200UL /**< Bit mask for USB_DCD */ +#define _USB_IEN_DCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ +#define USB_IEN_DCD_DEFAULT (_USB_IEN_DCD_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_IEN */ +#define USB_IEN_PD (0x1UL << 10) /**< PD Interrupt Enable */ +#define _USB_IEN_PD_SHIFT 10 /**< Shift value for USB_PD */ +#define _USB_IEN_PD_MASK 0x400UL /**< Bit mask for USB_PD */ +#define _USB_IEN_PD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ +#define USB_IEN_PD_DEFAULT (_USB_IEN_PD_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_IEN */ +#define USB_IEN_SD (0x1UL << 11) /**< SD Interrupt Enable */ +#define _USB_IEN_SD_SHIFT 11 /**< Shift value for USB_SD */ +#define _USB_IEN_SD_MASK 0x800UL /**< Bit mask for USB_SD */ +#define _USB_IEN_SD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ +#define USB_IEN_SD_DEFAULT (_USB_IEN_SD_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_IEN */ + +/* Bit fields for USB ROUTE */ +#define _USB_ROUTE_RESETVALUE 0x00000000UL /**< Default value for USB_ROUTE */ +#define _USB_ROUTE_MASK 0x00000003UL /**< Mask for USB_ROUTE */ +#define USB_ROUTE_PHYPEN (0x1UL << 0) /**< USB PHY Pin Enable */ +#define _USB_ROUTE_PHYPEN_SHIFT 0 /**< Shift value for USB_PHYPEN */ +#define _USB_ROUTE_PHYPEN_MASK 0x1UL /**< Bit mask for USB_PHYPEN */ +#define _USB_ROUTE_PHYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */ +#define USB_ROUTE_PHYPEN_DEFAULT (_USB_ROUTE_PHYPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_ROUTE */ +#define USB_ROUTE_VBUSENPEN (0x1UL << 1) /**< VBUSEN Pin Enable */ +#define _USB_ROUTE_VBUSENPEN_SHIFT 1 /**< Shift value for USB_VBUSENPEN */ +#define _USB_ROUTE_VBUSENPEN_MASK 0x2UL /**< Bit mask for USB_VBUSENPEN */ +#define _USB_ROUTE_VBUSENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */ +#define USB_ROUTE_VBUSENPEN_DEFAULT (_USB_ROUTE_VBUSENPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_ROUTE */ + +/* Bit fields for USB CDCONF */ +#define _USB_CDCONF_RESETVALUE 0x00000000UL /**< Default value for USB_CDCONF */ +#define _USB_CDCONF_MASK 0x000003FFUL /**< Mask for USB_CDCONF */ +#define _USB_CDCONF_DCDTOCONF_SHIFT 0 /**< Shift value for USB_DCDTOCONF */ +#define _USB_CDCONF_DCDTOCONF_MASK 0x3FFUL /**< Bit mask for USB_DCDTOCONF */ +#define _USB_CDCONF_DCDTOCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CDCONF */ +#define USB_CDCONF_DCDTOCONF_DEFAULT (_USB_CDCONF_DCDTOCONF_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_CDCONF */ + +/* Bit fields for USB CMD */ +#define _USB_CMD_RESETVALUE 0x00000000UL /**< Default value for USB_CMD */ +#define _USB_CMD_MASK 0x00000003UL /**< Mask for USB_CMD */ +#define USB_CMD_STARTCD (0x1UL << 0) /**< Start Charger Detection Enabled */ +#define _USB_CMD_STARTCD_SHIFT 0 /**< Shift value for USB_STARTCD */ +#define _USB_CMD_STARTCD_MASK 0x1UL /**< Bit mask for USB_STARTCD */ +#define _USB_CMD_STARTCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CMD */ +#define USB_CMD_STARTCD_DEFAULT (_USB_CMD_STARTCD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_CMD */ +#define USB_CMD_STOPCD (0x1UL << 1) /**< Start Charger Detection in Progress */ +#define _USB_CMD_STOPCD_SHIFT 1 /**< Shift value for USB_STOPCD */ +#define _USB_CMD_STOPCD_MASK 0x2UL /**< Bit mask for USB_STOPCD */ +#define _USB_CMD_STOPCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CMD */ +#define USB_CMD_STOPCD_DEFAULT (_USB_CMD_STOPCD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_CMD */ + +/* Bit fields for USB DATTRIM1 */ +#define _USB_DATTRIM1_RESETVALUE 0x00000024UL /**< Default value for USB_DATTRIM1 */ +#define _USB_DATTRIM1_MASK 0x000FFFBFUL /**< Mask for USB_DATTRIM1 */ +#define _USB_DATTRIM1_ROUT_SHIFT 0 /**< Shift value for USB_ROUT */ +#define _USB_DATTRIM1_ROUT_MASK 0x3FUL /**< Bit mask for USB_ROUT */ +#define _USB_DATTRIM1_ROUT_DEFAULT 0x00000024UL /**< Mode DEFAULT for USB_DATTRIM1 */ +#define USB_DATTRIM1_ROUT_DEFAULT (_USB_DATTRIM1_ROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ +#define USB_DATTRIM1_ENDLYPULLUP (0x1UL << 7) /**< Enables Delay of Pull in TX Mode for Both FS and LS */ +#define _USB_DATTRIM1_ENDLYPULLUP_SHIFT 7 /**< Shift value for USB_ENDLYPULLUP */ +#define _USB_DATTRIM1_ENDLYPULLUP_MASK 0x80UL /**< Bit mask for USB_ENDLYPULLUP */ +#define _USB_DATTRIM1_ENDLYPULLUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ +#define USB_DATTRIM1_ENDLYPULLUP_DEFAULT (_USB_DATTRIM1_ENDLYPULLUP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ +#define _USB_DATTRIM1_DLYPULLUPFS_SHIFT 8 /**< Shift value for USB_DLYPULLUPFS */ +#define _USB_DATTRIM1_DLYPULLUPFS_MASK 0x300UL /**< Bit mask for USB_DLYPULLUPFS */ +#define _USB_DATTRIM1_DLYPULLUPFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ +#define USB_DATTRIM1_DLYPULLUPFS_DEFAULT (_USB_DATTRIM1_DLYPULLUPFS_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ +#define _USB_DATTRIM1_VCRSFS_SHIFT 10 /**< Shift value for USB_VCRSFS */ +#define _USB_DATTRIM1_VCRSFS_MASK 0xC00UL /**< Bit mask for USB_VCRSFS */ +#define _USB_DATTRIM1_VCRSFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ +#define USB_DATTRIM1_VCRSFS_DEFAULT (_USB_DATTRIM1_VCRSFS_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ +#define _USB_DATTRIM1_TFDMFS_SHIFT 12 /**< Shift value for USB_TFDMFS */ +#define _USB_DATTRIM1_TFDMFS_MASK 0x3000UL /**< Bit mask for USB_TFDMFS */ +#define _USB_DATTRIM1_TFDMFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ +#define USB_DATTRIM1_TFDMFS_DEFAULT (_USB_DATTRIM1_TFDMFS_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ +#define _USB_DATTRIM1_TRDMFS_SHIFT 14 /**< Shift value for USB_TRDMFS */ +#define _USB_DATTRIM1_TRDMFS_MASK 0xC000UL /**< Bit mask for USB_TRDMFS */ +#define _USB_DATTRIM1_TRDMFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ +#define USB_DATTRIM1_TRDMFS_DEFAULT (_USB_DATTRIM1_TRDMFS_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ +#define _USB_DATTRIM1_TFDPFS_SHIFT 16 /**< Shift value for USB_TFDPFS */ +#define _USB_DATTRIM1_TFDPFS_MASK 0x30000UL /**< Bit mask for USB_TFDPFS */ +#define _USB_DATTRIM1_TFDPFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ +#define USB_DATTRIM1_TFDPFS_DEFAULT (_USB_DATTRIM1_TFDPFS_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ +#define _USB_DATTRIM1_TRDPFS_SHIFT 18 /**< Shift value for USB_TRDPFS */ +#define _USB_DATTRIM1_TRDPFS_MASK 0xC0000UL /**< Bit mask for USB_TRDPFS */ +#define _USB_DATTRIM1_TRDPFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DATTRIM1 */ +#define USB_DATTRIM1_TRDPFS_DEFAULT (_USB_DATTRIM1_TRDPFS_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DATTRIM1 */ + +/* Bit fields for USB LEMCTRL */ +#define _USB_LEMCTRL_RESETVALUE 0x00000067UL /**< Default value for USB_LEMCTRL */ +#define _USB_LEMCTRL_MASK 0x000003FFUL /**< Mask for USB_LEMCTRL */ +#define _USB_LEMCTRL_TIMEBASE_SHIFT 0 /**< Shift value for USB_TIMEBASE */ +#define _USB_LEMCTRL_TIMEBASE_MASK 0x3FFUL /**< Bit mask for USB_TIMEBASE */ +#define _USB_LEMCTRL_TIMEBASE_DEFAULT 0x00000067UL /**< Mode DEFAULT for USB_LEMCTRL */ +#define USB_LEMCTRL_TIMEBASE_DEFAULT (_USB_LEMCTRL_TIMEBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_LEMCTRL */ + +/* Bit fields for USB GOTGCTL */ +#define _USB_GOTGCTL_RESETVALUE 0x00010000UL /**< Default value for USB_GOTGCTL */ +#define _USB_GOTGCTL_MASK 0x003F9FFFUL /**< Mask for USB_GOTGCTL */ +#define USB_GOTGCTL_SESREQSCS (0x1UL << 0) /**< Session Request Success */ +#define _USB_GOTGCTL_SESREQSCS_SHIFT 0 /**< Shift value for USB_SESREQSCS */ +#define _USB_GOTGCTL_SESREQSCS_MASK 0x1UL /**< Bit mask for USB_SESREQSCS */ +#define _USB_GOTGCTL_SESREQSCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_SESREQSCS_DEFAULT (_USB_GOTGCTL_SESREQSCS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_SESREQ (0x1UL << 1) /**< Session Request */ +#define _USB_GOTGCTL_SESREQ_SHIFT 1 /**< Shift value for USB_SESREQ */ +#define _USB_GOTGCTL_SESREQ_MASK 0x2UL /**< Bit mask for USB_SESREQ */ +#define _USB_GOTGCTL_SESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_SESREQ_DEFAULT (_USB_GOTGCTL_SESREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_VBVALIDOVEN (0x1UL << 2) /**< VBUS Valid Override Enable */ +#define _USB_GOTGCTL_VBVALIDOVEN_SHIFT 2 /**< Shift value for USB_VBVALIDOVEN */ +#define _USB_GOTGCTL_VBVALIDOVEN_MASK 0x4UL /**< Bit mask for USB_VBVALIDOVEN */ +#define _USB_GOTGCTL_VBVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_VBVALIDOVEN_DEFAULT (_USB_GOTGCTL_VBVALIDOVEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_VBVALIDOVVAL (0x1UL << 3) /**< VBUS Valid OverrideValue */ +#define _USB_GOTGCTL_VBVALIDOVVAL_SHIFT 3 /**< Shift value for USB_VBVALIDOVVAL */ +#define _USB_GOTGCTL_VBVALIDOVVAL_MASK 0x8UL /**< Bit mask for USB_VBVALIDOVVAL */ +#define _USB_GOTGCTL_VBVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_VBVALIDOVVAL_DEFAULT (_USB_GOTGCTL_VBVALIDOVVAL_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_AVALIDOVEN (0x1UL << 4) /**< A-Peripheral Session Valid Override Enable */ +#define _USB_GOTGCTL_AVALIDOVEN_SHIFT 4 /**< Shift value for USB_AVALIDOVEN */ +#define _USB_GOTGCTL_AVALIDOVEN_MASK 0x10UL /**< Bit mask for USB_AVALIDOVEN */ +#define _USB_GOTGCTL_AVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_AVALIDOVEN_DEFAULT (_USB_GOTGCTL_AVALIDOVEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_AVALIDOVVAL (0x1UL << 5) /**< A-Peripheral Session Valid OverrideValue */ +#define _USB_GOTGCTL_AVALIDOVVAL_SHIFT 5 /**< Shift value for USB_AVALIDOVVAL */ +#define _USB_GOTGCTL_AVALIDOVVAL_MASK 0x20UL /**< Bit mask for USB_AVALIDOVVAL */ +#define _USB_GOTGCTL_AVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_AVALIDOVVAL_DEFAULT (_USB_GOTGCTL_AVALIDOVVAL_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BVALIDOVEN (0x1UL << 6) /**< B-Peripheral Session Valid Override Enable */ +#define _USB_GOTGCTL_BVALIDOVEN_SHIFT 6 /**< Shift value for USB_BVALIDOVEN */ +#define _USB_GOTGCTL_BVALIDOVEN_MASK 0x40UL /**< Bit mask for USB_BVALIDOVEN */ +#define _USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BVALIDOVEN_DEFAULT (_USB_GOTGCTL_BVALIDOVEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BVALIDOVVAL (0x1UL << 7) /**< B-Peripheral Session Valid OverrideValue */ +#define _USB_GOTGCTL_BVALIDOVVAL_SHIFT 7 /**< Shift value for USB_BVALIDOVVAL */ +#define _USB_GOTGCTL_BVALIDOVVAL_MASK 0x80UL /**< Bit mask for USB_BVALIDOVVAL */ +#define _USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BVALIDOVVAL_DEFAULT (_USB_GOTGCTL_BVALIDOVVAL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HSTNEGSCS (0x1UL << 8) /**< Host Negotiation Success */ +#define _USB_GOTGCTL_HSTNEGSCS_SHIFT 8 /**< Shift value for USB_HSTNEGSCS */ +#define _USB_GOTGCTL_HSTNEGSCS_MASK 0x100UL /**< Bit mask for USB_HSTNEGSCS */ +#define _USB_GOTGCTL_HSTNEGSCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HSTNEGSCS_DEFAULT (_USB_GOTGCTL_HSTNEGSCS_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HNPREQ (0x1UL << 9) /**< HNP Request */ +#define _USB_GOTGCTL_HNPREQ_SHIFT 9 /**< Shift value for USB_HNPREQ */ +#define _USB_GOTGCTL_HNPREQ_MASK 0x200UL /**< Bit mask for USB_HNPREQ */ +#define _USB_GOTGCTL_HNPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HNPREQ_DEFAULT (_USB_GOTGCTL_HNPREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HSTSETHNPEN (0x1UL << 10) /**< Host Set HNP Enable */ +#define _USB_GOTGCTL_HSTSETHNPEN_SHIFT 10 /**< Shift value for USB_HSTSETHNPEN */ +#define _USB_GOTGCTL_HSTSETHNPEN_MASK 0x400UL /**< Bit mask for USB_HSTSETHNPEN */ +#define _USB_GOTGCTL_HSTSETHNPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HSTSETHNPEN_DEFAULT (_USB_GOTGCTL_HSTSETHNPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_DEVHNPEN (0x1UL << 11) /**< Device HNP Enabled */ +#define _USB_GOTGCTL_DEVHNPEN_SHIFT 11 /**< Shift value for USB_DEVHNPEN */ +#define _USB_GOTGCTL_DEVHNPEN_MASK 0x800UL /**< Bit mask for USB_DEVHNPEN */ +#define _USB_GOTGCTL_DEVHNPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_DEVHNPEN_DEFAULT (_USB_GOTGCTL_DEVHNPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_EHEN (0x1UL << 12) /**< Embedded Host Enable */ +#define _USB_GOTGCTL_EHEN_SHIFT 12 /**< Shift value for USB_EHEN */ +#define _USB_GOTGCTL_EHEN_MASK 0x1000UL /**< Bit mask for USB_EHEN */ +#define _USB_GOTGCTL_EHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_EHEN_DEFAULT (_USB_GOTGCTL_EHEN_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_DBNCEFLTRBYPASS (0x1UL << 15) /**< Debounce Filter Bypass */ +#define _USB_GOTGCTL_DBNCEFLTRBYPASS_SHIFT 15 /**< Shift value for USB_DBNCEFLTRBYPASS */ +#define _USB_GOTGCTL_DBNCEFLTRBYPASS_MASK 0x8000UL /**< Bit mask for USB_DBNCEFLTRBYPASS */ +#define _USB_GOTGCTL_DBNCEFLTRBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_DBNCEFLTRBYPASS_DEFAULT (_USB_GOTGCTL_DBNCEFLTRBYPASS_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_CONIDSTS (0x1UL << 16) /**< Connector ID Status */ +#define _USB_GOTGCTL_CONIDSTS_SHIFT 16 /**< Shift value for USB_CONIDSTS */ +#define _USB_GOTGCTL_CONIDSTS_MASK 0x10000UL /**< Bit mask for USB_CONIDSTS */ +#define _USB_GOTGCTL_CONIDSTS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_CONIDSTS_DEFAULT (_USB_GOTGCTL_CONIDSTS_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_DBNCTIME (0x1UL << 17) /**< Long/Short Debounce Time */ +#define _USB_GOTGCTL_DBNCTIME_SHIFT 17 /**< Shift value for USB_DBNCTIME */ +#define _USB_GOTGCTL_DBNCTIME_MASK 0x20000UL /**< Bit mask for USB_DBNCTIME */ +#define _USB_GOTGCTL_DBNCTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_DBNCTIME_DEFAULT (_USB_GOTGCTL_DBNCTIME_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_ASESVLD (0x1UL << 18) /**< A-Session Valid */ +#define _USB_GOTGCTL_ASESVLD_SHIFT 18 /**< Shift value for USB_ASESVLD */ +#define _USB_GOTGCTL_ASESVLD_MASK 0x40000UL /**< Bit mask for USB_ASESVLD */ +#define _USB_GOTGCTL_ASESVLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_ASESVLD_DEFAULT (_USB_GOTGCTL_ASESVLD_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BSESVLD (0x1UL << 19) /**< B-Session Valid */ +#define _USB_GOTGCTL_BSESVLD_SHIFT 19 /**< Shift value for USB_BSESVLD */ +#define _USB_GOTGCTL_BSESVLD_MASK 0x80000UL /**< Bit mask for USB_BSESVLD */ +#define _USB_GOTGCTL_BSESVLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BSESVLD_DEFAULT (_USB_GOTGCTL_BSESVLD_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_OTGVER (0x1UL << 20) /**< OTG Version */ +#define _USB_GOTGCTL_OTGVER_SHIFT 20 /**< Shift value for USB_OTGVER */ +#define _USB_GOTGCTL_OTGVER_MASK 0x100000UL /**< Bit mask for USB_OTGVER */ +#define _USB_GOTGCTL_OTGVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_OTGVER_DEFAULT (_USB_GOTGCTL_OTGVER_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_CURMOD (0x1UL << 21) /**< Current Mode of Operation */ +#define _USB_GOTGCTL_CURMOD_SHIFT 21 /**< Shift value for USB_CURMOD */ +#define _USB_GOTGCTL_CURMOD_MASK 0x200000UL /**< Bit mask for USB_CURMOD */ +#define _USB_GOTGCTL_CURMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_CURMOD_DEFAULT (_USB_GOTGCTL_CURMOD_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GOTGCTL */ + +/* Bit fields for USB GOTGINT */ +#define _USB_GOTGINT_RESETVALUE 0x00000000UL /**< Default value for USB_GOTGINT */ +#define _USB_GOTGINT_MASK 0x000E0304UL /**< Mask for USB_GOTGINT */ +#define USB_GOTGINT_SESENDDET (0x1UL << 2) /**< Session End Detected */ +#define _USB_GOTGINT_SESENDDET_SHIFT 2 /**< Shift value for USB_SESENDDET */ +#define _USB_GOTGINT_SESENDDET_MASK 0x4UL /**< Bit mask for USB_SESENDDET */ +#define _USB_GOTGINT_SESENDDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_SESENDDET_DEFAULT (_USB_GOTGINT_SESENDDET_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_SESREQSUCSTSCHNG (0x1UL << 8) /**< Session Request Success Status Change */ +#define _USB_GOTGINT_SESREQSUCSTSCHNG_SHIFT 8 /**< Shift value for USB_SESREQSUCSTSCHNG */ +#define _USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100UL /**< Bit mask for USB_SESREQSUCSTSCHNG */ +#define _USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT (_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_HSTNEGSUCSTSCHNG (0x1UL << 9) /**< Host Negotiation Success Status Change */ +#define _USB_GOTGINT_HSTNEGSUCSTSCHNG_SHIFT 9 /**< Shift value for USB_HSTNEGSUCSTSCHNG */ +#define _USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200UL /**< Bit mask for USB_HSTNEGSUCSTSCHNG */ +#define _USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT (_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_HSTNEGDET (0x1UL << 17) /**< Host Negotiation Detected */ +#define _USB_GOTGINT_HSTNEGDET_SHIFT 17 /**< Shift value for USB_HSTNEGDET */ +#define _USB_GOTGINT_HSTNEGDET_MASK 0x20000UL /**< Bit mask for USB_HSTNEGDET */ +#define _USB_GOTGINT_HSTNEGDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_HSTNEGDET_DEFAULT (_USB_GOTGINT_HSTNEGDET_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_ADEVTOUTCHG (0x1UL << 18) /**< A-Device Timeout Change */ +#define _USB_GOTGINT_ADEVTOUTCHG_SHIFT 18 /**< Shift value for USB_ADEVTOUTCHG */ +#define _USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000UL /**< Bit mask for USB_ADEVTOUTCHG */ +#define _USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_ADEVTOUTCHG_DEFAULT (_USB_GOTGINT_ADEVTOUTCHG_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_DBNCEDONE (0x1UL << 19) /**< Debounce Done */ +#define _USB_GOTGINT_DBNCEDONE_SHIFT 19 /**< Shift value for USB_DBNCEDONE */ +#define _USB_GOTGINT_DBNCEDONE_MASK 0x80000UL /**< Bit mask for USB_DBNCEDONE */ +#define _USB_GOTGINT_DBNCEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_DBNCEDONE_DEFAULT (_USB_GOTGINT_DBNCEDONE_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GOTGINT */ + +/* Bit fields for USB GAHBCFG */ +#define _USB_GAHBCFG_RESETVALUE 0x00000000UL /**< Default value for USB_GAHBCFG */ +#define _USB_GAHBCFG_MASK 0x00E001BFUL /**< Mask for USB_GAHBCFG */ +#define USB_GAHBCFG_GLBLINTRMSK (0x1UL << 0) /**< Global Interrupt Mask */ +#define _USB_GAHBCFG_GLBLINTRMSK_SHIFT 0 /**< Shift value for USB_GLBLINTRMSK */ +#define _USB_GAHBCFG_GLBLINTRMSK_MASK 0x1UL /**< Bit mask for USB_GLBLINTRMSK */ +#define _USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_GLBLINTRMSK_DEFAULT (_USB_GAHBCFG_GLBLINTRMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_SHIFT 1 /**< Shift value for USB_HBSTLEN */ +#define _USB_GAHBCFG_HBSTLEN_MASK 0x1EUL /**< Bit mask for USB_HBSTLEN */ +#define _USB_GAHBCFG_HBSTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_SINGLE 0x00000000UL /**< Mode SINGLE for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_INCR 0x00000001UL /**< Mode INCR for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_INCR4 0x00000003UL /**< Mode INCR4 for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_INCR8 0x00000005UL /**< Mode INCR8 for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_INCR16 0x00000007UL /**< Mode INCR16 for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_DEFAULT (_USB_GAHBCFG_HBSTLEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_SINGLE (_USB_GAHBCFG_HBSTLEN_SINGLE << 1) /**< Shifted mode SINGLE for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_INCR (_USB_GAHBCFG_HBSTLEN_INCR << 1) /**< Shifted mode INCR for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_INCR4 (_USB_GAHBCFG_HBSTLEN_INCR4 << 1) /**< Shifted mode INCR4 for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_INCR8 (_USB_GAHBCFG_HBSTLEN_INCR8 << 1) /**< Shifted mode INCR8 for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_INCR16 (_USB_GAHBCFG_HBSTLEN_INCR16 << 1) /**< Shifted mode INCR16 for USB_GAHBCFG */ +#define USB_GAHBCFG_DMAEN (0x1UL << 5) /**< DMA Enable */ +#define _USB_GAHBCFG_DMAEN_SHIFT 5 /**< Shift value for USB_DMAEN */ +#define _USB_GAHBCFG_DMAEN_MASK 0x20UL /**< Bit mask for USB_DMAEN */ +#define _USB_GAHBCFG_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_DMAEN_DEFAULT (_USB_GAHBCFG_DMAEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_NPTXFEMPLVL (0x1UL << 7) /**< Non-Periodic TxFIFO Empty Level */ +#define _USB_GAHBCFG_NPTXFEMPLVL_SHIFT 7 /**< Shift value for USB_NPTXFEMPLVL */ +#define _USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80UL /**< Bit mask for USB_NPTXFEMPLVL */ +#define _USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ +#define _USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY 0x00000000UL /**< Mode HALFEMPTY for USB_GAHBCFG */ +#define _USB_GAHBCFG_NPTXFEMPLVL_EMPTY 0x00000001UL /**< Mode EMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_NPTXFEMPLVL_DEFAULT (_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY << 7) /**< Shifted mode HALFEMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_NPTXFEMPLVL_EMPTY (_USB_GAHBCFG_NPTXFEMPLVL_EMPTY << 7) /**< Shifted mode EMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_PTXFEMPLVL (0x1UL << 8) /**< Periodic TxFIFO Empty Level */ +#define _USB_GAHBCFG_PTXFEMPLVL_SHIFT 8 /**< Shift value for USB_PTXFEMPLVL */ +#define _USB_GAHBCFG_PTXFEMPLVL_MASK 0x100UL /**< Bit mask for USB_PTXFEMPLVL */ +#define _USB_GAHBCFG_PTXFEMPLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ +#define _USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY 0x00000000UL /**< Mode HALFEMPTY for USB_GAHBCFG */ +#define _USB_GAHBCFG_PTXFEMPLVL_EMPTY 0x00000001UL /**< Mode EMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_PTXFEMPLVL_DEFAULT (_USB_GAHBCFG_PTXFEMPLVL_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY << 8) /**< Shifted mode HALFEMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_PTXFEMPLVL_EMPTY (_USB_GAHBCFG_PTXFEMPLVL_EMPTY << 8) /**< Shifted mode EMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_REMMEMSUPP (0x1UL << 21) /**< Remote Memory Support */ +#define _USB_GAHBCFG_REMMEMSUPP_SHIFT 21 /**< Shift value for USB_REMMEMSUPP */ +#define _USB_GAHBCFG_REMMEMSUPP_MASK 0x200000UL /**< Bit mask for USB_REMMEMSUPP */ +#define _USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_REMMEMSUPP_DEFAULT (_USB_GAHBCFG_REMMEMSUPP_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_NOTIALLDMAWRIT (0x1UL << 22) /**< Notify All Dma Write Transactions */ +#define _USB_GAHBCFG_NOTIALLDMAWRIT_SHIFT 22 /**< Shift value for USB_NOTIALLDMAWRIT */ +#define _USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000UL /**< Bit mask for USB_NOTIALLDMAWRIT */ +#define _USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT (_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_AHBSINGLE (0x1UL << 23) /**< AHB Single Support */ +#define _USB_GAHBCFG_AHBSINGLE_SHIFT 23 /**< Shift value for USB_AHBSINGLE */ +#define _USB_GAHBCFG_AHBSINGLE_MASK 0x800000UL /**< Bit mask for USB_AHBSINGLE */ +#define _USB_GAHBCFG_AHBSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_AHBSINGLE_DEFAULT (_USB_GAHBCFG_AHBSINGLE_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GAHBCFG */ + +/* Bit fields for USB GUSBCFG */ +#define _USB_GUSBCFG_RESETVALUE 0x00001400UL /**< Default value for USB_GUSBCFG */ +#define _USB_GUSBCFG_MASK 0xF0403F27UL /**< Mask for USB_GUSBCFG */ +#define _USB_GUSBCFG_TOUTCAL_SHIFT 0 /**< Shift value for USB_TOUTCAL */ +#define _USB_GUSBCFG_TOUTCAL_MASK 0x7UL /**< Bit mask for USB_TOUTCAL */ +#define _USB_GUSBCFG_TOUTCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_TOUTCAL_DEFAULT (_USB_GUSBCFG_TOUTCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FSINTF (0x1UL << 5) /**< Full-Speed Serial Interface Select */ +#define _USB_GUSBCFG_FSINTF_SHIFT 5 /**< Shift value for USB_FSINTF */ +#define _USB_GUSBCFG_FSINTF_MASK 0x20UL /**< Bit mask for USB_FSINTF */ +#define _USB_GUSBCFG_FSINTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FSINTF_DEFAULT (_USB_GUSBCFG_FSINTF_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_SRPCAP (0x1UL << 8) /**< SRP-Capable */ +#define _USB_GUSBCFG_SRPCAP_SHIFT 8 /**< Shift value for USB_SRPCAP */ +#define _USB_GUSBCFG_SRPCAP_MASK 0x100UL /**< Bit mask for USB_SRPCAP */ +#define _USB_GUSBCFG_SRPCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_SRPCAP_DEFAULT (_USB_GUSBCFG_SRPCAP_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_HNPCAP (0x1UL << 9) /**< HNP-Capable */ +#define _USB_GUSBCFG_HNPCAP_SHIFT 9 /**< Shift value for USB_HNPCAP */ +#define _USB_GUSBCFG_HNPCAP_MASK 0x200UL /**< Bit mask for USB_HNPCAP */ +#define _USB_GUSBCFG_HNPCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_HNPCAP_DEFAULT (_USB_GUSBCFG_HNPCAP_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GUSBCFG */ +#define _USB_GUSBCFG_USBTRDTIM_SHIFT 10 /**< Shift value for USB_USBTRDTIM */ +#define _USB_GUSBCFG_USBTRDTIM_MASK 0x3C00UL /**< Bit mask for USB_USBTRDTIM */ +#define _USB_GUSBCFG_USBTRDTIM_DEFAULT 0x00000005UL /**< Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_USBTRDTIM_DEFAULT (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_TERMSELDLPULSE (0x1UL << 22) /**< TermSel DLine Pulsing Selection */ +#define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT 22 /**< Shift value for USB_TERMSELDLPULSE */ +#define _USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000UL /**< Bit mask for USB_TERMSELDLPULSE */ +#define _USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ +#define _USB_GUSBCFG_TERMSELDLPULSE_TXVALID 0x00000000UL /**< Mode TXVALID for USB_GUSBCFG */ +#define _USB_GUSBCFG_TERMSELDLPULSE_TERMSEL 0x00000001UL /**< Mode TERMSEL for USB_GUSBCFG */ +#define USB_GUSBCFG_TERMSELDLPULSE_DEFAULT (_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_TERMSELDLPULSE_TXVALID (_USB_GUSBCFG_TERMSELDLPULSE_TXVALID << 22) /**< Shifted mode TXVALID for USB_GUSBCFG */ +#define USB_GUSBCFG_TERMSELDLPULSE_TERMSEL (_USB_GUSBCFG_TERMSELDLPULSE_TERMSEL << 22) /**< Shifted mode TERMSEL for USB_GUSBCFG */ +#define USB_GUSBCFG_TXENDDELAY (0x1UL << 28) /**< Tx End Delay */ +#define _USB_GUSBCFG_TXENDDELAY_SHIFT 28 /**< Shift value for USB_TXENDDELAY */ +#define _USB_GUSBCFG_TXENDDELAY_MASK 0x10000000UL /**< Bit mask for USB_TXENDDELAY */ +#define _USB_GUSBCFG_TXENDDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_TXENDDELAY_DEFAULT (_USB_GUSBCFG_TXENDDELAY_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FORCEHSTMODE (0x1UL << 29) /**< Force Host Mode */ +#define _USB_GUSBCFG_FORCEHSTMODE_SHIFT 29 /**< Shift value for USB_FORCEHSTMODE */ +#define _USB_GUSBCFG_FORCEHSTMODE_MASK 0x20000000UL /**< Bit mask for USB_FORCEHSTMODE */ +#define _USB_GUSBCFG_FORCEHSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FORCEHSTMODE_DEFAULT (_USB_GUSBCFG_FORCEHSTMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FORCEDEVMODE (0x1UL << 30) /**< Force Device Mode */ +#define _USB_GUSBCFG_FORCEDEVMODE_SHIFT 30 /**< Shift value for USB_FORCEDEVMODE */ +#define _USB_GUSBCFG_FORCEDEVMODE_MASK 0x40000000UL /**< Bit mask for USB_FORCEDEVMODE */ +#define _USB_GUSBCFG_FORCEDEVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FORCEDEVMODE_DEFAULT (_USB_GUSBCFG_FORCEDEVMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_CORRUPTTXPKT (0x1UL << 31) /**< Corrupt Tx packet (host and device) */ +#define _USB_GUSBCFG_CORRUPTTXPKT_SHIFT 31 /**< Shift value for USB_CORRUPTTXPKT */ +#define _USB_GUSBCFG_CORRUPTTXPKT_MASK 0x80000000UL /**< Bit mask for USB_CORRUPTTXPKT */ +#define _USB_GUSBCFG_CORRUPTTXPKT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_CORRUPTTXPKT_DEFAULT (_USB_GUSBCFG_CORRUPTTXPKT_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GUSBCFG */ + +/* Bit fields for USB GRSTCTL */ +#define _USB_GRSTCTL_RESETVALUE 0x80000000UL /**< Default value for USB_GRSTCTL */ +#define _USB_GRSTCTL_MASK 0xC00007F7UL /**< Mask for USB_GRSTCTL */ +#define USB_GRSTCTL_CSFTRST (0x1UL << 0) /**< Core Soft Reset (host and device) */ +#define _USB_GRSTCTL_CSFTRST_SHIFT 0 /**< Shift value for USB_CSFTRST */ +#define _USB_GRSTCTL_CSFTRST_MASK 0x1UL /**< Bit mask for USB_CSFTRST */ +#define _USB_GRSTCTL_CSFTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_CSFTRST_DEFAULT (_USB_GRSTCTL_CSFTRST_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_PIUFSSFTRST (0x1UL << 1) /**< PIU FS Dedicated Controller Soft Reset */ +#define _USB_GRSTCTL_PIUFSSFTRST_SHIFT 1 /**< Shift value for USB_PIUFSSFTRST */ +#define _USB_GRSTCTL_PIUFSSFTRST_MASK 0x2UL /**< Bit mask for USB_PIUFSSFTRST */ +#define _USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_PIUFSSFTRST_DEFAULT (_USB_GRSTCTL_PIUFSSFTRST_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_FRMCNTRRST (0x1UL << 2) /**< Host Frame Counter Reset */ +#define _USB_GRSTCTL_FRMCNTRRST_SHIFT 2 /**< Shift value for USB_FRMCNTRRST */ +#define _USB_GRSTCTL_FRMCNTRRST_MASK 0x4UL /**< Bit mask for USB_FRMCNTRRST */ +#define _USB_GRSTCTL_FRMCNTRRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_FRMCNTRRST_DEFAULT (_USB_GRSTCTL_FRMCNTRRST_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_RXFFLSH (0x1UL << 4) /**< RxFIFO Flush */ +#define _USB_GRSTCTL_RXFFLSH_SHIFT 4 /**< Shift value for USB_RXFFLSH */ +#define _USB_GRSTCTL_RXFFLSH_MASK 0x10UL /**< Bit mask for USB_RXFFLSH */ +#define _USB_GRSTCTL_RXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_RXFFLSH_DEFAULT (_USB_GRSTCTL_RXFFLSH_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFFLSH (0x1UL << 5) /**< TxFIFO Flush */ +#define _USB_GRSTCTL_TXFFLSH_SHIFT 5 /**< Shift value for USB_TXFFLSH */ +#define _USB_GRSTCTL_TXFFLSH_MASK 0x20UL /**< Bit mask for USB_TXFFLSH */ +#define _USB_GRSTCTL_TXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFFLSH_DEFAULT (_USB_GRSTCTL_TXFFLSH_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_SHIFT 6 /**< Shift value for USB_TXFNUM */ +#define _USB_GRSTCTL_TXFNUM_MASK 0x7C0UL /**< Bit mask for USB_TXFNUM */ +#define _USB_GRSTCTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F0 0x00000000UL /**< Mode F0 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F1 0x00000001UL /**< Mode F1 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F2 0x00000002UL /**< Mode F2 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F3 0x00000003UL /**< Mode F3 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F4 0x00000004UL /**< Mode F4 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F5 0x00000005UL /**< Mode F5 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F6 0x00000006UL /**< Mode F6 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_FALL 0x00000010UL /**< Mode FALL for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_DEFAULT (_USB_GRSTCTL_TXFNUM_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F0 (_USB_GRSTCTL_TXFNUM_F0 << 6) /**< Shifted mode F0 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F1 (_USB_GRSTCTL_TXFNUM_F1 << 6) /**< Shifted mode F1 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F2 (_USB_GRSTCTL_TXFNUM_F2 << 6) /**< Shifted mode F2 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F3 (_USB_GRSTCTL_TXFNUM_F3 << 6) /**< Shifted mode F3 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F4 (_USB_GRSTCTL_TXFNUM_F4 << 6) /**< Shifted mode F4 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F5 (_USB_GRSTCTL_TXFNUM_F5 << 6) /**< Shifted mode F5 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F6 (_USB_GRSTCTL_TXFNUM_F6 << 6) /**< Shifted mode F6 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_FALL (_USB_GRSTCTL_TXFNUM_FALL << 6) /**< Shifted mode FALL for USB_GRSTCTL */ +#define USB_GRSTCTL_DMAREQ (0x1UL << 30) /**< DMA Request Signal */ +#define _USB_GRSTCTL_DMAREQ_SHIFT 30 /**< Shift value for USB_DMAREQ */ +#define _USB_GRSTCTL_DMAREQ_MASK 0x40000000UL /**< Bit mask for USB_DMAREQ */ +#define _USB_GRSTCTL_DMAREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_DMAREQ_DEFAULT (_USB_GRSTCTL_DMAREQ_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_AHBIDLE (0x1UL << 31) /**< AHB Master Idle */ +#define _USB_GRSTCTL_AHBIDLE_SHIFT 31 /**< Shift value for USB_AHBIDLE */ +#define _USB_GRSTCTL_AHBIDLE_MASK 0x80000000UL /**< Bit mask for USB_AHBIDLE */ +#define _USB_GRSTCTL_AHBIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_AHBIDLE_DEFAULT (_USB_GRSTCTL_AHBIDLE_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GRSTCTL */ + +/* Bit fields for USB GINTSTS */ +#define _USB_GINTSTS_RESETVALUE 0x14000020UL /**< Default value for USB_GINTSTS */ +#define _USB_GINTSTS_MASK 0xF7FEFCFFUL /**< Mask for USB_GINTSTS */ +#define USB_GINTSTS_CURMOD (0x1UL << 0) /**< Current Mode of Operation (host and device) */ +#define _USB_GINTSTS_CURMOD_SHIFT 0 /**< Shift value for USB_CURMOD */ +#define _USB_GINTSTS_CURMOD_MASK 0x1UL /**< Bit mask for USB_CURMOD */ +#define _USB_GINTSTS_CURMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define _USB_GINTSTS_CURMOD_DEVICE 0x00000000UL /**< Mode DEVICE for USB_GINTSTS */ +#define _USB_GINTSTS_CURMOD_HOST 0x00000001UL /**< Mode HOST for USB_GINTSTS */ +#define USB_GINTSTS_CURMOD_DEFAULT (_USB_GINTSTS_CURMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_CURMOD_DEVICE (_USB_GINTSTS_CURMOD_DEVICE << 0) /**< Shifted mode DEVICE for USB_GINTSTS */ +#define USB_GINTSTS_CURMOD_HOST (_USB_GINTSTS_CURMOD_HOST << 0) /**< Shifted mode HOST for USB_GINTSTS */ +#define USB_GINTSTS_MODEMIS (0x1UL << 1) /**< Mode Mismatch Interrupt (host and device) */ +#define _USB_GINTSTS_MODEMIS_SHIFT 1 /**< Shift value for USB_MODEMIS */ +#define _USB_GINTSTS_MODEMIS_MASK 0x2UL /**< Bit mask for USB_MODEMIS */ +#define _USB_GINTSTS_MODEMIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_MODEMIS_DEFAULT (_USB_GINTSTS_MODEMIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_OTGINT (0x1UL << 2) /**< OTG Interrupt (host and device) */ +#define _USB_GINTSTS_OTGINT_SHIFT 2 /**< Shift value for USB_OTGINT */ +#define _USB_GINTSTS_OTGINT_MASK 0x4UL /**< Bit mask for USB_OTGINT */ +#define _USB_GINTSTS_OTGINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_OTGINT_DEFAULT (_USB_GINTSTS_OTGINT_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_SOF (0x1UL << 3) /**< Start of Frame (host and device) */ +#define _USB_GINTSTS_SOF_SHIFT 3 /**< Shift value for USB_SOF */ +#define _USB_GINTSTS_SOF_MASK 0x8UL /**< Bit mask for USB_SOF */ +#define _USB_GINTSTS_SOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_SOF_DEFAULT (_USB_GINTSTS_SOF_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_RXFLVL (0x1UL << 4) /**< RxFIFO Non-Empty (host and device) */ +#define _USB_GINTSTS_RXFLVL_SHIFT 4 /**< Shift value for USB_RXFLVL */ +#define _USB_GINTSTS_RXFLVL_MASK 0x10UL /**< Bit mask for USB_RXFLVL */ +#define _USB_GINTSTS_RXFLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_RXFLVL_DEFAULT (_USB_GINTSTS_RXFLVL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_NPTXFEMP (0x1UL << 5) /**< Non-Periodic TxFIFO Empty (host only) */ +#define _USB_GINTSTS_NPTXFEMP_SHIFT 5 /**< Shift value for USB_NPTXFEMP */ +#define _USB_GINTSTS_NPTXFEMP_MASK 0x20UL /**< Bit mask for USB_NPTXFEMP */ +#define _USB_GINTSTS_NPTXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_NPTXFEMP_DEFAULT (_USB_GINTSTS_NPTXFEMP_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_GINNAKEFF (0x1UL << 6) /**< Global IN Non-periodic NAK Effective (device only) */ +#define _USB_GINTSTS_GINNAKEFF_SHIFT 6 /**< Shift value for USB_GINNAKEFF */ +#define _USB_GINTSTS_GINNAKEFF_MASK 0x40UL /**< Bit mask for USB_GINNAKEFF */ +#define _USB_GINTSTS_GINNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_GINNAKEFF_DEFAULT (_USB_GINTSTS_GINNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_GOUTNAKEFF (0x1UL << 7) /**< Global OUT NAK Effective (device only) */ +#define _USB_GINTSTS_GOUTNAKEFF_SHIFT 7 /**< Shift value for USB_GOUTNAKEFF */ +#define _USB_GINTSTS_GOUTNAKEFF_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFF */ +#define _USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_GOUTNAKEFF_DEFAULT (_USB_GINTSTS_GOUTNAKEFF_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ERLYSUSP (0x1UL << 10) /**< Early Suspend (device only) */ +#define _USB_GINTSTS_ERLYSUSP_SHIFT 10 /**< Shift value for USB_ERLYSUSP */ +#define _USB_GINTSTS_ERLYSUSP_MASK 0x400UL /**< Bit mask for USB_ERLYSUSP */ +#define _USB_GINTSTS_ERLYSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ERLYSUSP_DEFAULT (_USB_GINTSTS_ERLYSUSP_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_USBSUSP (0x1UL << 11) /**< USB Suspend (device only) */ +#define _USB_GINTSTS_USBSUSP_SHIFT 11 /**< Shift value for USB_USBSUSP */ +#define _USB_GINTSTS_USBSUSP_MASK 0x800UL /**< Bit mask for USB_USBSUSP */ +#define _USB_GINTSTS_USBSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_USBSUSP_DEFAULT (_USB_GINTSTS_USBSUSP_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_USBRST (0x1UL << 12) /**< USB Reset (device only) */ +#define _USB_GINTSTS_USBRST_SHIFT 12 /**< Shift value for USB_USBRST */ +#define _USB_GINTSTS_USBRST_MASK 0x1000UL /**< Bit mask for USB_USBRST */ +#define _USB_GINTSTS_USBRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_USBRST_DEFAULT (_USB_GINTSTS_USBRST_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ENUMDONE (0x1UL << 13) /**< Enumeration Done (device only) */ +#define _USB_GINTSTS_ENUMDONE_SHIFT 13 /**< Shift value for USB_ENUMDONE */ +#define _USB_GINTSTS_ENUMDONE_MASK 0x2000UL /**< Bit mask for USB_ENUMDONE */ +#define _USB_GINTSTS_ENUMDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ENUMDONE_DEFAULT (_USB_GINTSTS_ENUMDONE_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ISOOUTDROP (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt (device only) */ +#define _USB_GINTSTS_ISOOUTDROP_SHIFT 14 /**< Shift value for USB_ISOOUTDROP */ +#define _USB_GINTSTS_ISOOUTDROP_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROP */ +#define _USB_GINTSTS_ISOOUTDROP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ISOOUTDROP_DEFAULT (_USB_GINTSTS_ISOOUTDROP_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_EOPF (0x1UL << 15) /**< End of Periodic Frame Interrupt */ +#define _USB_GINTSTS_EOPF_SHIFT 15 /**< Shift value for USB_EOPF */ +#define _USB_GINTSTS_EOPF_MASK 0x8000UL /**< Bit mask for USB_EOPF */ +#define _USB_GINTSTS_EOPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_EOPF_DEFAULT (_USB_GINTSTS_EOPF_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_EPMIS (0x1UL << 17) /**< Endpoint Mismatch Interrupt (device only) */ +#define _USB_GINTSTS_EPMIS_SHIFT 17 /**< Shift value for USB_EPMIS */ +#define _USB_GINTSTS_EPMIS_MASK 0x20000UL /**< Bit mask for USB_EPMIS */ +#define _USB_GINTSTS_EPMIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_EPMIS_DEFAULT (_USB_GINTSTS_EPMIS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_IEPINT (0x1UL << 18) /**< IN Endpoints Interrupt (device only) */ +#define _USB_GINTSTS_IEPINT_SHIFT 18 /**< Shift value for USB_IEPINT */ +#define _USB_GINTSTS_IEPINT_MASK 0x40000UL /**< Bit mask for USB_IEPINT */ +#define _USB_GINTSTS_IEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_IEPINT_DEFAULT (_USB_GINTSTS_IEPINT_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_OEPINT (0x1UL << 19) /**< OUT Endpoints Interrupt (device only) */ +#define _USB_GINTSTS_OEPINT_SHIFT 19 /**< Shift value for USB_OEPINT */ +#define _USB_GINTSTS_OEPINT_MASK 0x80000UL /**< Bit mask for USB_OEPINT */ +#define _USB_GINTSTS_OEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_OEPINT_DEFAULT (_USB_GINTSTS_OEPINT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_INCOMPISOIN (0x1UL << 20) /**< Incomplete Isochronous IN Transfer (device only) */ +#define _USB_GINTSTS_INCOMPISOIN_SHIFT 20 /**< Shift value for USB_INCOMPISOIN */ +#define _USB_GINTSTS_INCOMPISOIN_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOIN */ +#define _USB_GINTSTS_INCOMPISOIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_INCOMPISOIN_DEFAULT (_USB_GINTSTS_INCOMPISOIN_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_INCOMPLP (0x1UL << 21) /**< Incomplete Periodic Transfer (device only) */ +#define _USB_GINTSTS_INCOMPLP_SHIFT 21 /**< Shift value for USB_INCOMPLP */ +#define _USB_GINTSTS_INCOMPLP_MASK 0x200000UL /**< Bit mask for USB_INCOMPLP */ +#define _USB_GINTSTS_INCOMPLP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_INCOMPLP_DEFAULT (_USB_GINTSTS_INCOMPLP_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_FETSUSP (0x1UL << 22) /**< Data Fetch Suspended (device only) */ +#define _USB_GINTSTS_FETSUSP_SHIFT 22 /**< Shift value for USB_FETSUSP */ +#define _USB_GINTSTS_FETSUSP_MASK 0x400000UL /**< Bit mask for USB_FETSUSP */ +#define _USB_GINTSTS_FETSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_FETSUSP_DEFAULT (_USB_GINTSTS_FETSUSP_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_RESETDET (0x1UL << 23) /**< Reset detected Interrupt (device only) */ +#define _USB_GINTSTS_RESETDET_SHIFT 23 /**< Shift value for USB_RESETDET */ +#define _USB_GINTSTS_RESETDET_MASK 0x800000UL /**< Bit mask for USB_RESETDET */ +#define _USB_GINTSTS_RESETDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_RESETDET_DEFAULT (_USB_GINTSTS_RESETDET_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_PRTINT (0x1UL << 24) /**< Host Port Interrupt (host only) */ +#define _USB_GINTSTS_PRTINT_SHIFT 24 /**< Shift value for USB_PRTINT */ +#define _USB_GINTSTS_PRTINT_MASK 0x1000000UL /**< Bit mask for USB_PRTINT */ +#define _USB_GINTSTS_PRTINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_PRTINT_DEFAULT (_USB_GINTSTS_PRTINT_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_HCHINT (0x1UL << 25) /**< Host Channels Interrupt (host only) */ +#define _USB_GINTSTS_HCHINT_SHIFT 25 /**< Shift value for USB_HCHINT */ +#define _USB_GINTSTS_HCHINT_MASK 0x2000000UL /**< Bit mask for USB_HCHINT */ +#define _USB_GINTSTS_HCHINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_HCHINT_DEFAULT (_USB_GINTSTS_HCHINT_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_PTXFEMP (0x1UL << 26) /**< Periodic TxFIFO Empty (host only) */ +#define _USB_GINTSTS_PTXFEMP_SHIFT 26 /**< Shift value for USB_PTXFEMP */ +#define _USB_GINTSTS_PTXFEMP_MASK 0x4000000UL /**< Bit mask for USB_PTXFEMP */ +#define _USB_GINTSTS_PTXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_PTXFEMP_DEFAULT (_USB_GINTSTS_PTXFEMP_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_CONIDSTSCHNG (0x1UL << 28) /**< Connector ID Status Change (host and device) */ +#define _USB_GINTSTS_CONIDSTSCHNG_SHIFT 28 /**< Shift value for USB_CONIDSTSCHNG */ +#define _USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000UL /**< Bit mask for USB_CONIDSTSCHNG */ +#define _USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_CONIDSTSCHNG_DEFAULT (_USB_GINTSTS_CONIDSTSCHNG_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_DISCONNINT (0x1UL << 29) /**< Disconnect Detected Interrupt (host only) */ +#define _USB_GINTSTS_DISCONNINT_SHIFT 29 /**< Shift value for USB_DISCONNINT */ +#define _USB_GINTSTS_DISCONNINT_MASK 0x20000000UL /**< Bit mask for USB_DISCONNINT */ +#define _USB_GINTSTS_DISCONNINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_DISCONNINT_DEFAULT (_USB_GINTSTS_DISCONNINT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_SESSREQINT (0x1UL << 30) /**< Session Request/New Session Detected Interrupt (host and device) */ +#define _USB_GINTSTS_SESSREQINT_SHIFT 30 /**< Shift value for USB_SESSREQINT */ +#define _USB_GINTSTS_SESSREQINT_MASK 0x40000000UL /**< Bit mask for USB_SESSREQINT */ +#define _USB_GINTSTS_SESSREQINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_SESSREQINT_DEFAULT (_USB_GINTSTS_SESSREQINT_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_WKUPINT (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt (host and device) */ +#define _USB_GINTSTS_WKUPINT_SHIFT 31 /**< Shift value for USB_WKUPINT */ +#define _USB_GINTSTS_WKUPINT_MASK 0x80000000UL /**< Bit mask for USB_WKUPINT */ +#define _USB_GINTSTS_WKUPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_WKUPINT_DEFAULT (_USB_GINTSTS_WKUPINT_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GINTSTS */ + +/* Bit fields for USB GINTMSK */ +#define _USB_GINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_GINTMSK */ +#define _USB_GINTMSK_MASK 0xF7FEFCFEUL /**< Mask for USB_GINTMSK */ +#define USB_GINTMSK_MODEMISMSK (0x1UL << 1) /**< Mode Mismatch Interrupt Mask (host and device) */ +#define _USB_GINTMSK_MODEMISMSK_SHIFT 1 /**< Shift value for USB_MODEMISMSK */ +#define _USB_GINTMSK_MODEMISMSK_MASK 0x2UL /**< Bit mask for USB_MODEMISMSK */ +#define _USB_GINTMSK_MODEMISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_MODEMISMSK_DEFAULT (_USB_GINTMSK_MODEMISMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_OTGINTMSK (0x1UL << 2) /**< OTG Interrupt Mask (host and device) */ +#define _USB_GINTMSK_OTGINTMSK_SHIFT 2 /**< Shift value for USB_OTGINTMSK */ +#define _USB_GINTMSK_OTGINTMSK_MASK 0x4UL /**< Bit mask for USB_OTGINTMSK */ +#define _USB_GINTMSK_OTGINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_OTGINTMSK_DEFAULT (_USB_GINTMSK_OTGINTMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_SOFMSK (0x1UL << 3) /**< Start of Frame Mask (host and device) */ +#define _USB_GINTMSK_SOFMSK_SHIFT 3 /**< Shift value for USB_SOFMSK */ +#define _USB_GINTMSK_SOFMSK_MASK 0x8UL /**< Bit mask for USB_SOFMSK */ +#define _USB_GINTMSK_SOFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_SOFMSK_DEFAULT (_USB_GINTMSK_SOFMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_RXFLVLMSK (0x1UL << 4) /**< Receive FIFO Non-Empty Mask (host and device) */ +#define _USB_GINTMSK_RXFLVLMSK_SHIFT 4 /**< Shift value for USB_RXFLVLMSK */ +#define _USB_GINTMSK_RXFLVLMSK_MASK 0x10UL /**< Bit mask for USB_RXFLVLMSK */ +#define _USB_GINTMSK_RXFLVLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_RXFLVLMSK_DEFAULT (_USB_GINTMSK_RXFLVLMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_NPTXFEMPMSK (0x1UL << 5) /**< Non-Periodic TxFIFO Empty Mask (host only) */ +#define _USB_GINTMSK_NPTXFEMPMSK_SHIFT 5 /**< Shift value for USB_NPTXFEMPMSK */ +#define _USB_GINTMSK_NPTXFEMPMSK_MASK 0x20UL /**< Bit mask for USB_NPTXFEMPMSK */ +#define _USB_GINTMSK_NPTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_NPTXFEMPMSK_DEFAULT (_USB_GINTMSK_NPTXFEMPMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_GINNAKEFFMSK (0x1UL << 6) /**< Global Non-periodic IN NAK Effective Mask (device only) */ +#define _USB_GINTMSK_GINNAKEFFMSK_SHIFT 6 /**< Shift value for USB_GINNAKEFFMSK */ +#define _USB_GINTMSK_GINNAKEFFMSK_MASK 0x40UL /**< Bit mask for USB_GINNAKEFFMSK */ +#define _USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_GINNAKEFFMSK_DEFAULT (_USB_GINTMSK_GINNAKEFFMSK_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_GOUTNAKEFFMSK (0x1UL << 7) /**< Global OUT NAK Effective Mask (device only) */ +#define _USB_GINTMSK_GOUTNAKEFFMSK_SHIFT 7 /**< Shift value for USB_GOUTNAKEFFMSK */ +#define _USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFFMSK */ +#define _USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT (_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ERLYSUSPMSK (0x1UL << 10) /**< Early Suspend Mask (device only) */ +#define _USB_GINTMSK_ERLYSUSPMSK_SHIFT 10 /**< Shift value for USB_ERLYSUSPMSK */ +#define _USB_GINTMSK_ERLYSUSPMSK_MASK 0x400UL /**< Bit mask for USB_ERLYSUSPMSK */ +#define _USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ERLYSUSPMSK_DEFAULT (_USB_GINTMSK_ERLYSUSPMSK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_USBSUSPMSK (0x1UL << 11) /**< USB Suspend Mask (device only) */ +#define _USB_GINTMSK_USBSUSPMSK_SHIFT 11 /**< Shift value for USB_USBSUSPMSK */ +#define _USB_GINTMSK_USBSUSPMSK_MASK 0x800UL /**< Bit mask for USB_USBSUSPMSK */ +#define _USB_GINTMSK_USBSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_USBSUSPMSK_DEFAULT (_USB_GINTMSK_USBSUSPMSK_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_USBRSTMSK (0x1UL << 12) /**< USB Reset Mask (device only) */ +#define _USB_GINTMSK_USBRSTMSK_SHIFT 12 /**< Shift value for USB_USBRSTMSK */ +#define _USB_GINTMSK_USBRSTMSK_MASK 0x1000UL /**< Bit mask for USB_USBRSTMSK */ +#define _USB_GINTMSK_USBRSTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_USBRSTMSK_DEFAULT (_USB_GINTMSK_USBRSTMSK_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ENUMDONEMSK (0x1UL << 13) /**< Enumeration Done Mask (device only) */ +#define _USB_GINTMSK_ENUMDONEMSK_SHIFT 13 /**< Shift value for USB_ENUMDONEMSK */ +#define _USB_GINTMSK_ENUMDONEMSK_MASK 0x2000UL /**< Bit mask for USB_ENUMDONEMSK */ +#define _USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ENUMDONEMSK_DEFAULT (_USB_GINTMSK_ENUMDONEMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ISOOUTDROPMSK (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt Mask (device only) */ +#define _USB_GINTMSK_ISOOUTDROPMSK_SHIFT 14 /**< Shift value for USB_ISOOUTDROPMSK */ +#define _USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROPMSK */ +#define _USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ISOOUTDROPMSK_DEFAULT (_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_EOPFMSK (0x1UL << 15) /**< End of Periodic Frame Interrupt Mask (device only) */ +#define _USB_GINTMSK_EOPFMSK_SHIFT 15 /**< Shift value for USB_EOPFMSK */ +#define _USB_GINTMSK_EOPFMSK_MASK 0x8000UL /**< Bit mask for USB_EOPFMSK */ +#define _USB_GINTMSK_EOPFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_EOPFMSK_DEFAULT (_USB_GINTMSK_EOPFMSK_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_EPMISMSK (0x1UL << 17) /**< Endpoint Mismatch Interrupt Mask (device only) */ +#define _USB_GINTMSK_EPMISMSK_SHIFT 17 /**< Shift value for USB_EPMISMSK */ +#define _USB_GINTMSK_EPMISMSK_MASK 0x20000UL /**< Bit mask for USB_EPMISMSK */ +#define _USB_GINTMSK_EPMISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_EPMISMSK_DEFAULT (_USB_GINTMSK_EPMISMSK_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_IEPINTMSK (0x1UL << 18) /**< IN Endpoints Interrupt Mask (device only) */ +#define _USB_GINTMSK_IEPINTMSK_SHIFT 18 /**< Shift value for USB_IEPINTMSK */ +#define _USB_GINTMSK_IEPINTMSK_MASK 0x40000UL /**< Bit mask for USB_IEPINTMSK */ +#define _USB_GINTMSK_IEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_IEPINTMSK_DEFAULT (_USB_GINTMSK_IEPINTMSK_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_OEPINTMSK (0x1UL << 19) /**< OUT Endpoints Interrupt Mask (device only) */ +#define _USB_GINTMSK_OEPINTMSK_SHIFT 19 /**< Shift value for USB_OEPINTMSK */ +#define _USB_GINTMSK_OEPINTMSK_MASK 0x80000UL /**< Bit mask for USB_OEPINTMSK */ +#define _USB_GINTMSK_OEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_OEPINTMSK_DEFAULT (_USB_GINTMSK_OEPINTMSK_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_INCOMPISOINMSK (0x1UL << 20) /**< Incomplete Isochronous IN Transfer Mask (device only) */ +#define _USB_GINTMSK_INCOMPISOINMSK_SHIFT 20 /**< Shift value for USB_INCOMPISOINMSK */ +#define _USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOINMSK */ +#define _USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_INCOMPISOINMSK_DEFAULT (_USB_GINTMSK_INCOMPISOINMSK_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_INCOMPLPMSK (0x1UL << 21) /**< Incomplete Periodic Transfer Mask (host only) */ +#define _USB_GINTMSK_INCOMPLPMSK_SHIFT 21 /**< Shift value for USB_INCOMPLPMSK */ +#define _USB_GINTMSK_INCOMPLPMSK_MASK 0x200000UL /**< Bit mask for USB_INCOMPLPMSK */ +#define _USB_GINTMSK_INCOMPLPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_INCOMPLPMSK_DEFAULT (_USB_GINTMSK_INCOMPLPMSK_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_FETSUSPMSK (0x1UL << 22) /**< Data Fetch Suspended Mask (device only) */ +#define _USB_GINTMSK_FETSUSPMSK_SHIFT 22 /**< Shift value for USB_FETSUSPMSK */ +#define _USB_GINTMSK_FETSUSPMSK_MASK 0x400000UL /**< Bit mask for USB_FETSUSPMSK */ +#define _USB_GINTMSK_FETSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_FETSUSPMSK_DEFAULT (_USB_GINTMSK_FETSUSPMSK_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_RESETDETMSK (0x1UL << 23) /**< Reset detected Interrupt Mask (device only) */ +#define _USB_GINTMSK_RESETDETMSK_SHIFT 23 /**< Shift value for USB_RESETDETMSK */ +#define _USB_GINTMSK_RESETDETMSK_MASK 0x800000UL /**< Bit mask for USB_RESETDETMSK */ +#define _USB_GINTMSK_RESETDETMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_RESETDETMSK_DEFAULT (_USB_GINTMSK_RESETDETMSK_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_PRTINTMSK (0x1UL << 24) /**< Host Port Interrupt Mask (host only) */ +#define _USB_GINTMSK_PRTINTMSK_SHIFT 24 /**< Shift value for USB_PRTINTMSK */ +#define _USB_GINTMSK_PRTINTMSK_MASK 0x1000000UL /**< Bit mask for USB_PRTINTMSK */ +#define _USB_GINTMSK_PRTINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_PRTINTMSK_DEFAULT (_USB_GINTMSK_PRTINTMSK_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_HCHINTMSK (0x1UL << 25) /**< Host Channels Interrupt Mask (host only) */ +#define _USB_GINTMSK_HCHINTMSK_SHIFT 25 /**< Shift value for USB_HCHINTMSK */ +#define _USB_GINTMSK_HCHINTMSK_MASK 0x2000000UL /**< Bit mask for USB_HCHINTMSK */ +#define _USB_GINTMSK_HCHINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_HCHINTMSK_DEFAULT (_USB_GINTMSK_HCHINTMSK_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_PTXFEMPMSK (0x1UL << 26) /**< Periodic TxFIFO Empty Mask (host only) */ +#define _USB_GINTMSK_PTXFEMPMSK_SHIFT 26 /**< Shift value for USB_PTXFEMPMSK */ +#define _USB_GINTMSK_PTXFEMPMSK_MASK 0x4000000UL /**< Bit mask for USB_PTXFEMPMSK */ +#define _USB_GINTMSK_PTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_PTXFEMPMSK_DEFAULT (_USB_GINTMSK_PTXFEMPMSK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_CONIDSTSCHNGMSK (0x1UL << 28) /**< Connector ID Status Change Mask (host and device) */ +#define _USB_GINTMSK_CONIDSTSCHNGMSK_SHIFT 28 /**< Shift value for USB_CONIDSTSCHNGMSK */ +#define _USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000UL /**< Bit mask for USB_CONIDSTSCHNGMSK */ +#define _USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT (_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_DISCONNINTMSK (0x1UL << 29) /**< Disconnect Detected Interrupt Mask (host and device) */ +#define _USB_GINTMSK_DISCONNINTMSK_SHIFT 29 /**< Shift value for USB_DISCONNINTMSK */ +#define _USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000UL /**< Bit mask for USB_DISCONNINTMSK */ +#define _USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_DISCONNINTMSK_DEFAULT (_USB_GINTMSK_DISCONNINTMSK_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_SESSREQINTMSK (0x1UL << 30) /**< Session Request/New Session Detected Interrupt Mask (host and device) */ +#define _USB_GINTMSK_SESSREQINTMSK_SHIFT 30 /**< Shift value for USB_SESSREQINTMSK */ +#define _USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000UL /**< Bit mask for USB_SESSREQINTMSK */ +#define _USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_SESSREQINTMSK_DEFAULT (_USB_GINTMSK_SESSREQINTMSK_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_WKUPINTMSK (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt Mask (host and device) */ +#define _USB_GINTMSK_WKUPINTMSK_SHIFT 31 /**< Shift value for USB_WKUPINTMSK */ +#define _USB_GINTMSK_WKUPINTMSK_MASK 0x80000000UL /**< Bit mask for USB_WKUPINTMSK */ +#define _USB_GINTMSK_WKUPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_WKUPINTMSK_DEFAULT (_USB_GINTMSK_WKUPINTMSK_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GINTMSK */ + +/* Bit fields for USB GRXSTSR */ +#define _USB_GRXSTSR_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSR */ +#define _USB_GRXSTSR_MASK 0x01FFFFFFUL /**< Mask for USB_GRXSTSR */ +#define _USB_GRXSTSR_CHNUM_SHIFT 0 /**< Shift value for USB_CHNUM */ +#define _USB_GRXSTSR_CHNUM_MASK 0xFUL /**< Bit mask for USB_CHNUM */ +#define _USB_GRXSTSR_CHNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ +#define USB_GRXSTSR_CHNUM_DEFAULT (_USB_GRXSTSR_CHNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXSTSR */ +#define _USB_GRXSTSR_BCNT_SHIFT 4 /**< Shift value for USB_BCNT */ +#define _USB_GRXSTSR_BCNT_MASK 0x7FF0UL /**< Bit mask for USB_BCNT */ +#define _USB_GRXSTSR_BCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ +#define USB_GRXSTSR_BCNT_DEFAULT (_USB_GRXSTSR_BCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRXSTSR */ +#define _USB_GRXSTSR_DPID_SHIFT 15 /**< Shift value for USB_DPID */ +#define _USB_GRXSTSR_DPID_MASK 0x18000UL /**< Bit mask for USB_DPID */ +#define _USB_GRXSTSR_DPID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ +#define _USB_GRXSTSR_DPID_DATA0 0x00000000UL /**< Mode DATA0 for USB_GRXSTSR */ +#define _USB_GRXSTSR_DPID_DATA1 0x00000001UL /**< Mode DATA1 for USB_GRXSTSR */ +#define _USB_GRXSTSR_DPID_DATA2 0x00000002UL /**< Mode DATA2 for USB_GRXSTSR */ +#define _USB_GRXSTSR_DPID_MDATA 0x00000003UL /**< Mode MDATA for USB_GRXSTSR */ +#define USB_GRXSTSR_DPID_DEFAULT (_USB_GRXSTSR_DPID_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GRXSTSR */ +#define USB_GRXSTSR_DPID_DATA0 (_USB_GRXSTSR_DPID_DATA0 << 15) /**< Shifted mode DATA0 for USB_GRXSTSR */ +#define USB_GRXSTSR_DPID_DATA1 (_USB_GRXSTSR_DPID_DATA1 << 15) /**< Shifted mode DATA1 for USB_GRXSTSR */ +#define USB_GRXSTSR_DPID_DATA2 (_USB_GRXSTSR_DPID_DATA2 << 15) /**< Shifted mode DATA2 for USB_GRXSTSR */ +#define USB_GRXSTSR_DPID_MDATA (_USB_GRXSTSR_DPID_MDATA << 15) /**< Shifted mode MDATA for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_SHIFT 17 /**< Shift value for USB_PKTSTS */ +#define _USB_GRXSTSR_PKTSTS_MASK 0x1E0000UL /**< Bit mask for USB_PKTSTS */ +#define _USB_GRXSTSR_PKTSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_GOUTNAK 0x00000001UL /**< Mode GOUTNAK for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_PKTRCV 0x00000002UL /**< Mode PKTRCV for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_XFERCOMPL 0x00000003UL /**< Mode XFERCOMPL for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_SETUPCOMPL 0x00000004UL /**< Mode SETUPCOMPL for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_TGLERR 0x00000005UL /**< Mode TGLERR for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_SETUPRCV 0x00000006UL /**< Mode SETUPRCV for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_CHLT 0x00000007UL /**< Mode CHLT for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_DEFAULT (_USB_GRXSTSR_PKTSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_GOUTNAK (_USB_GRXSTSR_PKTSTS_GOUTNAK << 17) /**< Shifted mode GOUTNAK for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_PKTRCV (_USB_GRXSTSR_PKTSTS_PKTRCV << 17) /**< Shifted mode PKTRCV for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_XFERCOMPL (_USB_GRXSTSR_PKTSTS_XFERCOMPL << 17) /**< Shifted mode XFERCOMPL for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_SETUPCOMPL (_USB_GRXSTSR_PKTSTS_SETUPCOMPL << 17) /**< Shifted mode SETUPCOMPL for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_TGLERR (_USB_GRXSTSR_PKTSTS_TGLERR << 17) /**< Shifted mode TGLERR for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_SETUPRCV (_USB_GRXSTSR_PKTSTS_SETUPRCV << 17) /**< Shifted mode SETUPRCV for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_CHLT (_USB_GRXSTSR_PKTSTS_CHLT << 17) /**< Shifted mode CHLT for USB_GRXSTSR */ +#define _USB_GRXSTSR_FN_SHIFT 21 /**< Shift value for USB_FN */ +#define _USB_GRXSTSR_FN_MASK 0x1E00000UL /**< Bit mask for USB_FN */ +#define _USB_GRXSTSR_FN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ +#define USB_GRXSTSR_FN_DEFAULT (_USB_GRXSTSR_FN_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GRXSTSR */ + +/* Bit fields for USB GRXSTSP */ +#define _USB_GRXSTSP_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSP */ +#define _USB_GRXSTSP_MASK 0x01FFFFFFUL /**< Mask for USB_GRXSTSP */ +#define _USB_GRXSTSP_CHNUM_SHIFT 0 /**< Shift value for USB_CHNUM */ +#define _USB_GRXSTSP_CHNUM_MASK 0xFUL /**< Bit mask for USB_CHNUM */ +#define _USB_GRXSTSP_CHNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ +#define USB_GRXSTSP_CHNUM_DEFAULT (_USB_GRXSTSP_CHNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXSTSP */ +#define _USB_GRXSTSP_BCNT_SHIFT 4 /**< Shift value for USB_BCNT */ +#define _USB_GRXSTSP_BCNT_MASK 0x7FF0UL /**< Bit mask for USB_BCNT */ +#define _USB_GRXSTSP_BCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ +#define USB_GRXSTSP_BCNT_DEFAULT (_USB_GRXSTSP_BCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRXSTSP */ +#define _USB_GRXSTSP_DPID_SHIFT 15 /**< Shift value for USB_DPID */ +#define _USB_GRXSTSP_DPID_MASK 0x18000UL /**< Bit mask for USB_DPID */ +#define _USB_GRXSTSP_DPID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ +#define _USB_GRXSTSP_DPID_DATA0 0x00000000UL /**< Mode DATA0 for USB_GRXSTSP */ +#define _USB_GRXSTSP_DPID_DATA1 0x00000001UL /**< Mode DATA1 for USB_GRXSTSP */ +#define _USB_GRXSTSP_DPID_DATA2 0x00000002UL /**< Mode DATA2 for USB_GRXSTSP */ +#define _USB_GRXSTSP_DPID_MDATA 0x00000003UL /**< Mode MDATA for USB_GRXSTSP */ +#define USB_GRXSTSP_DPID_DEFAULT (_USB_GRXSTSP_DPID_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GRXSTSP */ +#define USB_GRXSTSP_DPID_DATA0 (_USB_GRXSTSP_DPID_DATA0 << 15) /**< Shifted mode DATA0 for USB_GRXSTSP */ +#define USB_GRXSTSP_DPID_DATA1 (_USB_GRXSTSP_DPID_DATA1 << 15) /**< Shifted mode DATA1 for USB_GRXSTSP */ +#define USB_GRXSTSP_DPID_DATA2 (_USB_GRXSTSP_DPID_DATA2 << 15) /**< Shifted mode DATA2 for USB_GRXSTSP */ +#define USB_GRXSTSP_DPID_MDATA (_USB_GRXSTSP_DPID_MDATA << 15) /**< Shifted mode MDATA for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_SHIFT 17 /**< Shift value for USB_PKTSTS */ +#define _USB_GRXSTSP_PKTSTS_MASK 0x1E0000UL /**< Bit mask for USB_PKTSTS */ +#define _USB_GRXSTSP_PKTSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_GOUTNAK 0x00000001UL /**< Mode GOUTNAK for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_PKTRCV 0x00000002UL /**< Mode PKTRCV for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_XFERCOMPL 0x00000003UL /**< Mode XFERCOMPL for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_SETUPCOMPL 0x00000004UL /**< Mode SETUPCOMPL for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_TGLERR 0x00000005UL /**< Mode TGLERR for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_SETUPRCV 0x00000006UL /**< Mode SETUPRCV for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_CHLT 0x00000007UL /**< Mode CHLT for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_DEFAULT (_USB_GRXSTSP_PKTSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_GOUTNAK (_USB_GRXSTSP_PKTSTS_GOUTNAK << 17) /**< Shifted mode GOUTNAK for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_PKTRCV (_USB_GRXSTSP_PKTSTS_PKTRCV << 17) /**< Shifted mode PKTRCV for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_XFERCOMPL (_USB_GRXSTSP_PKTSTS_XFERCOMPL << 17) /**< Shifted mode XFERCOMPL for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_SETUPCOMPL (_USB_GRXSTSP_PKTSTS_SETUPCOMPL << 17) /**< Shifted mode SETUPCOMPL for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_TGLERR (_USB_GRXSTSP_PKTSTS_TGLERR << 17) /**< Shifted mode TGLERR for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_SETUPRCV (_USB_GRXSTSP_PKTSTS_SETUPRCV << 17) /**< Shifted mode SETUPRCV for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_CHLT (_USB_GRXSTSP_PKTSTS_CHLT << 17) /**< Shifted mode CHLT for USB_GRXSTSP */ +#define _USB_GRXSTSP_FN_SHIFT 21 /**< Shift value for USB_FN */ +#define _USB_GRXSTSP_FN_MASK 0x1E00000UL /**< Bit mask for USB_FN */ +#define _USB_GRXSTSP_FN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ +#define USB_GRXSTSP_FN_DEFAULT (_USB_GRXSTSP_FN_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GRXSTSP */ + +/* Bit fields for USB GRXFSIZ */ +#define _USB_GRXFSIZ_RESETVALUE 0x00000200UL /**< Default value for USB_GRXFSIZ */ +#define _USB_GRXFSIZ_MASK 0x000003FFUL /**< Mask for USB_GRXFSIZ */ +#define _USB_GRXFSIZ_RXFDEP_SHIFT 0 /**< Shift value for USB_RXFDEP */ +#define _USB_GRXFSIZ_RXFDEP_MASK 0x3FFUL /**< Bit mask for USB_RXFDEP */ +#define _USB_GRXFSIZ_RXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GRXFSIZ */ +#define USB_GRXFSIZ_RXFDEP_DEFAULT (_USB_GRXFSIZ_RXFDEP_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXFSIZ */ + +/* Bit fields for USB GNPTXFSIZ */ +#define _USB_GNPTXFSIZ_RESETVALUE 0x02000200UL /**< Default value for USB_GNPTXFSIZ */ +#define _USB_GNPTXFSIZ_MASK 0xFFFFFFFFUL /**< Mask for USB_GNPTXFSIZ */ +#define _USB_GNPTXFSIZ_NPTXFSTADDR_SHIFT 0 /**< Shift value for USB_NPTXFSTADDR */ +#define _USB_GNPTXFSIZ_NPTXFSTADDR_MASK 0xFFFFUL /**< Bit mask for USB_NPTXFSTADDR */ +#define _USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXFSIZ */ +#define USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT (_USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GNPTXFSIZ */ +#define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_SHIFT 16 /**< Shift value for USB_NPTXFINEPTXF0DEP */ +#define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_MASK 0xFFFF0000UL /**< Bit mask for USB_NPTXFINEPTXF0DEP */ +#define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXFSIZ */ +#define USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT (_USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GNPTXFSIZ */ + +/* Bit fields for USB GNPTXSTS */ +#define _USB_GNPTXSTS_RESETVALUE 0x00080200UL /**< Default value for USB_GNPTXSTS */ +#define _USB_GNPTXSTS_MASK 0x7FFFFFFFUL /**< Mask for USB_GNPTXSTS */ +#define _USB_GNPTXSTS_NPTXFSPCAVAIL_SHIFT 0 /**< Shift value for USB_NPTXFSPCAVAIL */ +#define _USB_GNPTXSTS_NPTXFSPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_NPTXFSPCAVAIL */ +#define _USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXSTS */ +#define USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT (_USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GNPTXSTS */ +#define _USB_GNPTXSTS_NPTXQSPCAVAIL_SHIFT 16 /**< Shift value for USB_NPTXQSPCAVAIL */ +#define _USB_GNPTXSTS_NPTXQSPCAVAIL_MASK 0xFF0000UL /**< Bit mask for USB_NPTXQSPCAVAIL */ +#define _USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_GNPTXSTS */ +#define USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT (_USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GNPTXSTS */ +#define _USB_GNPTXSTS_NPTXQTOP_SHIFT 24 /**< Shift value for USB_NPTXQTOP */ +#define _USB_GNPTXSTS_NPTXQTOP_MASK 0x7F000000UL /**< Bit mask for USB_NPTXQTOP */ +#define _USB_GNPTXSTS_NPTXQTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GNPTXSTS */ +#define USB_GNPTXSTS_NPTXQTOP_DEFAULT (_USB_GNPTXSTS_NPTXQTOP_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GNPTXSTS */ + +/* Bit fields for USB GSNPSID */ +#define _USB_GSNPSID_RESETVALUE 0x4F54330AUL /**< Default value for USB_GSNPSID */ +#define _USB_GSNPSID_MASK 0xFFFFFFFFUL /**< Mask for USB_GSNPSID */ +#define _USB_GSNPSID_SYNOPSYSID_SHIFT 0 /**< Shift value for USB_SYNOPSYSID */ +#define _USB_GSNPSID_SYNOPSYSID_MASK 0xFFFFFFFFUL /**< Bit mask for USB_SYNOPSYSID */ +#define _USB_GSNPSID_SYNOPSYSID_DEFAULT 0x4F54330AUL /**< Mode DEFAULT for USB_GSNPSID */ +#define USB_GSNPSID_SYNOPSYSID_DEFAULT (_USB_GSNPSID_SYNOPSYSID_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GSNPSID */ + +/* Bit fields for USB GDFIFOCFG */ +#define _USB_GDFIFOCFG_RESETVALUE 0x01F20200UL /**< Default value for USB_GDFIFOCFG */ +#define _USB_GDFIFOCFG_MASK 0xFFFFFFFFUL /**< Mask for USB_GDFIFOCFG */ +#define _USB_GDFIFOCFG_GDFIFOCFG_SHIFT 0 /**< Shift value for USB_GDFIFOCFG */ +#define _USB_GDFIFOCFG_GDFIFOCFG_MASK 0xFFFFUL /**< Bit mask for USB_GDFIFOCFG */ +#define _USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GDFIFOCFG */ +#define USB_GDFIFOCFG_GDFIFOCFG_DEFAULT (_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GDFIFOCFG */ +#define _USB_GDFIFOCFG_EPINFOBASEADDR_SHIFT 16 /**< Shift value for USB_EPINFOBASEADDR */ +#define _USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xFFFF0000UL /**< Bit mask for USB_EPINFOBASEADDR */ +#define _USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x000001F2UL /**< Mode DEFAULT for USB_GDFIFOCFG */ +#define USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT (_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GDFIFOCFG */ + +/* Bit fields for USB HPTXFSIZ */ +#define _USB_HPTXFSIZ_RESETVALUE 0x02000400UL /**< Default value for USB_HPTXFSIZ */ +#define _USB_HPTXFSIZ_MASK 0x03FF07FFUL /**< Mask for USB_HPTXFSIZ */ +#define _USB_HPTXFSIZ_PTXFSTADDR_SHIFT 0 /**< Shift value for USB_PTXFSTADDR */ +#define _USB_HPTXFSIZ_PTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_PTXFSTADDR */ +#define _USB_HPTXFSIZ_PTXFSTADDR_DEFAULT 0x00000400UL /**< Mode DEFAULT for USB_HPTXFSIZ */ +#define USB_HPTXFSIZ_PTXFSTADDR_DEFAULT (_USB_HPTXFSIZ_PTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPTXFSIZ */ +#define _USB_HPTXFSIZ_PTXFSIZE_SHIFT 16 /**< Shift value for USB_PTXFSIZE */ +#define _USB_HPTXFSIZ_PTXFSIZE_MASK 0x3FF0000UL /**< Bit mask for USB_PTXFSIZE */ +#define _USB_HPTXFSIZ_PTXFSIZE_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_HPTXFSIZ */ +#define USB_HPTXFSIZ_PTXFSIZE_DEFAULT (_USB_HPTXFSIZ_PTXFSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HPTXFSIZ */ + +/* Bit fields for USB DIEPTXF1 */ +#define _USB_DIEPTXF1_RESETVALUE 0x02000400UL /**< Default value for USB_DIEPTXF1 */ +#define _USB_DIEPTXF1_MASK 0x03FF07FFUL /**< Mask for USB_DIEPTXF1 */ +#define _USB_DIEPTXF1_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x00000400UL /**< Mode DEFAULT for USB_DIEPTXF1 */ +#define USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF1 */ +#define _USB_DIEPTXF1_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF1 */ +#define USB_DIEPTXF1_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF1 */ + +/* Bit fields for USB DIEPTXF2 */ +#define _USB_DIEPTXF2_RESETVALUE 0x02000600UL /**< Default value for USB_DIEPTXF2 */ +#define _USB_DIEPTXF2_MASK 0x03FF07FFUL /**< Mask for USB_DIEPTXF2 */ +#define _USB_DIEPTXF2_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x00000600UL /**< Mode DEFAULT for USB_DIEPTXF2 */ +#define USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF2 */ +#define _USB_DIEPTXF2_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF2 */ +#define USB_DIEPTXF2_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF2 */ + +/* Bit fields for USB DIEPTXF3 */ +#define _USB_DIEPTXF3_RESETVALUE 0x02000800UL /**< Default value for USB_DIEPTXF3 */ +#define _USB_DIEPTXF3_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF3 */ +#define _USB_DIEPTXF3_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x00000800UL /**< Mode DEFAULT for USB_DIEPTXF3 */ +#define USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF3 */ +#define _USB_DIEPTXF3_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF3 */ +#define USB_DIEPTXF3_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF3 */ + +/* Bit fields for USB DIEPTXF4 */ +#define _USB_DIEPTXF4_RESETVALUE 0x02000A00UL /**< Default value for USB_DIEPTXF4 */ +#define _USB_DIEPTXF4_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF4 */ +#define _USB_DIEPTXF4_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x00000A00UL /**< Mode DEFAULT for USB_DIEPTXF4 */ +#define USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF4 */ +#define _USB_DIEPTXF4_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF4 */ +#define USB_DIEPTXF4_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF4 */ + +/* Bit fields for USB DIEPTXF5 */ +#define _USB_DIEPTXF5_RESETVALUE 0x02000C00UL /**< Default value for USB_DIEPTXF5 */ +#define _USB_DIEPTXF5_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF5 */ +#define _USB_DIEPTXF5_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x00000C00UL /**< Mode DEFAULT for USB_DIEPTXF5 */ +#define USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF5 */ +#define _USB_DIEPTXF5_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF5 */ +#define USB_DIEPTXF5_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF5 */ + +/* Bit fields for USB DIEPTXF6 */ +#define _USB_DIEPTXF6_RESETVALUE 0x02000E00UL /**< Default value for USB_DIEPTXF6 */ +#define _USB_DIEPTXF6_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF6 */ +#define _USB_DIEPTXF6_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x00000E00UL /**< Mode DEFAULT for USB_DIEPTXF6 */ +#define USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF6 */ +#define _USB_DIEPTXF6_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF6 */ +#define USB_DIEPTXF6_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF6 */ + +/* Bit fields for USB HCFG */ +#define _USB_HCFG_RESETVALUE 0x00000200UL /**< Default value for USB_HCFG */ +#define _USB_HCFG_MASK 0x8000FF87UL /**< Mask for USB_HCFG */ +#define _USB_HCFG_FSLSPCLKSEL_SHIFT 0 /**< Shift value for USB_FSLSPCLKSEL */ +#define _USB_HCFG_FSLSPCLKSEL_MASK 0x3UL /**< Bit mask for USB_FSLSPCLKSEL */ +#define _USB_HCFG_FSLSPCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */ +#define _USB_HCFG_FSLSPCLKSEL_DIV1 0x00000001UL /**< Mode DIV1 for USB_HCFG */ +#define _USB_HCFG_FSLSPCLKSEL_DIV8 0x00000002UL /**< Mode DIV8 for USB_HCFG */ +#define USB_HCFG_FSLSPCLKSEL_DEFAULT (_USB_HCFG_FSLSPCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HCFG */ +#define USB_HCFG_FSLSPCLKSEL_DIV1 (_USB_HCFG_FSLSPCLKSEL_DIV1 << 0) /**< Shifted mode DIV1 for USB_HCFG */ +#define USB_HCFG_FSLSPCLKSEL_DIV8 (_USB_HCFG_FSLSPCLKSEL_DIV8 << 0) /**< Shifted mode DIV8 for USB_HCFG */ +#define USB_HCFG_FSLSSUPP (0x1UL << 2) /**< FS- and LS-Only Support */ +#define _USB_HCFG_FSLSSUPP_SHIFT 2 /**< Shift value for USB_FSLSSUPP */ +#define _USB_HCFG_FSLSSUPP_MASK 0x4UL /**< Bit mask for USB_FSLSSUPP */ +#define _USB_HCFG_FSLSSUPP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */ +#define _USB_HCFG_FSLSSUPP_HSFSLS 0x00000000UL /**< Mode HSFSLS for USB_HCFG */ +#define _USB_HCFG_FSLSSUPP_FSLS 0x00000001UL /**< Mode FSLS for USB_HCFG */ +#define USB_HCFG_FSLSSUPP_DEFAULT (_USB_HCFG_FSLSSUPP_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HCFG */ +#define USB_HCFG_FSLSSUPP_HSFSLS (_USB_HCFG_FSLSSUPP_HSFSLS << 2) /**< Shifted mode HSFSLS for USB_HCFG */ +#define USB_HCFG_FSLSSUPP_FSLS (_USB_HCFG_FSLSSUPP_FSLS << 2) /**< Shifted mode FSLS for USB_HCFG */ +#define USB_HCFG_ENA32KHZS (0x1UL << 7) /**< Enable 32 kHz Suspend Mode */ +#define _USB_HCFG_ENA32KHZS_SHIFT 7 /**< Shift value for USB_ENA32KHZS */ +#define _USB_HCFG_ENA32KHZS_MASK 0x80UL /**< Bit mask for USB_ENA32KHZS */ +#define _USB_HCFG_ENA32KHZS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */ +#define USB_HCFG_ENA32KHZS_DEFAULT (_USB_HCFG_ENA32KHZS_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HCFG */ +#define _USB_HCFG_RESVALID_SHIFT 8 /**< Shift value for USB_RESVALID */ +#define _USB_HCFG_RESVALID_MASK 0xFF00UL /**< Bit mask for USB_RESVALID */ +#define _USB_HCFG_RESVALID_DEFAULT 0x00000002UL /**< Mode DEFAULT for USB_HCFG */ +#define USB_HCFG_RESVALID_DEFAULT (_USB_HCFG_RESVALID_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HCFG */ +#define USB_HCFG_MODECHTIMEN (0x1UL << 31) /**< Mode Change Time */ +#define _USB_HCFG_MODECHTIMEN_SHIFT 31 /**< Shift value for USB_MODECHTIMEN */ +#define _USB_HCFG_MODECHTIMEN_MASK 0x80000000UL /**< Bit mask for USB_MODECHTIMEN */ +#define _USB_HCFG_MODECHTIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */ +#define USB_HCFG_MODECHTIMEN_DEFAULT (_USB_HCFG_MODECHTIMEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_HCFG */ + +/* Bit fields for USB HFIR */ +#define _USB_HFIR_RESETVALUE 0x0000EA60UL /**< Default value for USB_HFIR */ +#define _USB_HFIR_MASK 0x0001FFFFUL /**< Mask for USB_HFIR */ +#define _USB_HFIR_FRINT_SHIFT 0 /**< Shift value for USB_FRINT */ +#define _USB_HFIR_FRINT_MASK 0xFFFFUL /**< Bit mask for USB_FRINT */ +#define _USB_HFIR_FRINT_DEFAULT 0x0000EA60UL /**< Mode DEFAULT for USB_HFIR */ +#define USB_HFIR_FRINT_DEFAULT (_USB_HFIR_FRINT_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HFIR */ +#define USB_HFIR_HFIRRLDCTRL (0x1UL << 16) /**< Reload Control */ +#define _USB_HFIR_HFIRRLDCTRL_SHIFT 16 /**< Shift value for USB_HFIRRLDCTRL */ +#define _USB_HFIR_HFIRRLDCTRL_MASK 0x10000UL /**< Bit mask for USB_HFIRRLDCTRL */ +#define _USB_HFIR_HFIRRLDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HFIR */ +#define _USB_HFIR_HFIRRLDCTRL_STATIC 0x00000000UL /**< Mode STATIC for USB_HFIR */ +#define _USB_HFIR_HFIRRLDCTRL_DYNAMIC 0x00000001UL /**< Mode DYNAMIC for USB_HFIR */ +#define USB_HFIR_HFIRRLDCTRL_DEFAULT (_USB_HFIR_HFIRRLDCTRL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HFIR */ +#define USB_HFIR_HFIRRLDCTRL_STATIC (_USB_HFIR_HFIRRLDCTRL_STATIC << 16) /**< Shifted mode STATIC for USB_HFIR */ +#define USB_HFIR_HFIRRLDCTRL_DYNAMIC (_USB_HFIR_HFIRRLDCTRL_DYNAMIC << 16) /**< Shifted mode DYNAMIC for USB_HFIR */ + +/* Bit fields for USB HFNUM */ +#define _USB_HFNUM_RESETVALUE 0x00003FFFUL /**< Default value for USB_HFNUM */ +#define _USB_HFNUM_MASK 0xFFFFFFFFUL /**< Mask for USB_HFNUM */ +#define _USB_HFNUM_FRNUM_SHIFT 0 /**< Shift value for USB_FRNUM */ +#define _USB_HFNUM_FRNUM_MASK 0xFFFFUL /**< Bit mask for USB_FRNUM */ +#define _USB_HFNUM_FRNUM_DEFAULT 0x00003FFFUL /**< Mode DEFAULT for USB_HFNUM */ +#define USB_HFNUM_FRNUM_DEFAULT (_USB_HFNUM_FRNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HFNUM */ +#define _USB_HFNUM_FRREM_SHIFT 16 /**< Shift value for USB_FRREM */ +#define _USB_HFNUM_FRREM_MASK 0xFFFF0000UL /**< Bit mask for USB_FRREM */ +#define _USB_HFNUM_FRREM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HFNUM */ +#define USB_HFNUM_FRREM_DEFAULT (_USB_HFNUM_FRREM_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HFNUM */ + +/* Bit fields for USB HPTXSTS */ +#define _USB_HPTXSTS_RESETVALUE 0x00080200UL /**< Default value for USB_HPTXSTS */ +#define _USB_HPTXSTS_MASK 0xFFFFFFFFUL /**< Mask for USB_HPTXSTS */ +#define _USB_HPTXSTS_PTXFSPCAVAIL_SHIFT 0 /**< Shift value for USB_PTXFSPCAVAIL */ +#define _USB_HPTXSTS_PTXFSPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_PTXFSPCAVAIL */ +#define _USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_HPTXSTS */ +#define USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT (_USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPTXSTS */ +#define _USB_HPTXSTS_PTXQSPCAVAIL_SHIFT 16 /**< Shift value for USB_PTXQSPCAVAIL */ +#define _USB_HPTXSTS_PTXQSPCAVAIL_MASK 0xFF0000UL /**< Bit mask for USB_PTXQSPCAVAIL */ +#define _USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_HPTXSTS */ +#define USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT (_USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HPTXSTS */ +#define _USB_HPTXSTS_PTXQTOP_SHIFT 24 /**< Shift value for USB_PTXQTOP */ +#define _USB_HPTXSTS_PTXQTOP_MASK 0xFF000000UL /**< Bit mask for USB_PTXQTOP */ +#define _USB_HPTXSTS_PTXQTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPTXSTS */ +#define USB_HPTXSTS_PTXQTOP_DEFAULT (_USB_HPTXSTS_PTXQTOP_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_HPTXSTS */ + +/* Bit fields for USB HAINT */ +#define _USB_HAINT_RESETVALUE 0x00000000UL /**< Default value for USB_HAINT */ +#define _USB_HAINT_MASK 0x00003FFFUL /**< Mask for USB_HAINT */ +#define _USB_HAINT_HAINT_SHIFT 0 /**< Shift value for USB_HAINT */ +#define _USB_HAINT_HAINT_MASK 0x3FFFUL /**< Bit mask for USB_HAINT */ +#define _USB_HAINT_HAINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HAINT */ +#define USB_HAINT_HAINT_DEFAULT (_USB_HAINT_HAINT_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HAINT */ + +/* Bit fields for USB HAINTMSK */ +#define _USB_HAINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_HAINTMSK */ +#define _USB_HAINTMSK_MASK 0x00003FFFUL /**< Mask for USB_HAINTMSK */ +#define _USB_HAINTMSK_HAINTMSK_SHIFT 0 /**< Shift value for USB_HAINTMSK */ +#define _USB_HAINTMSK_HAINTMSK_MASK 0x3FFFUL /**< Bit mask for USB_HAINTMSK */ +#define _USB_HAINTMSK_HAINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HAINTMSK */ +#define USB_HAINTMSK_HAINTMSK_DEFAULT (_USB_HAINTMSK_HAINTMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HAINTMSK */ + +/* Bit fields for USB HPRT */ +#define _USB_HPRT_RESETVALUE 0x00000000UL /**< Default value for USB_HPRT */ +#define _USB_HPRT_MASK 0x0007FDFFUL /**< Mask for USB_HPRT */ +#define USB_HPRT_PRTCONNSTS (0x1UL << 0) /**< Port Connect Status */ +#define _USB_HPRT_PRTCONNSTS_SHIFT 0 /**< Shift value for USB_PRTCONNSTS */ +#define _USB_HPRT_PRTCONNSTS_MASK 0x1UL /**< Bit mask for USB_PRTCONNSTS */ +#define _USB_HPRT_PRTCONNSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTCONNSTS_DEFAULT (_USB_HPRT_PRTCONNSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTCONNDET (0x1UL << 1) /**< Port Connect Detected */ +#define _USB_HPRT_PRTCONNDET_SHIFT 1 /**< Shift value for USB_PRTCONNDET */ +#define _USB_HPRT_PRTCONNDET_MASK 0x2UL /**< Bit mask for USB_PRTCONNDET */ +#define _USB_HPRT_PRTCONNDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTCONNDET_DEFAULT (_USB_HPRT_PRTCONNDET_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTENA (0x1UL << 2) /**< Port Enable */ +#define _USB_HPRT_PRTENA_SHIFT 2 /**< Shift value for USB_PRTENA */ +#define _USB_HPRT_PRTENA_MASK 0x4UL /**< Bit mask for USB_PRTENA */ +#define _USB_HPRT_PRTENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTENA_DEFAULT (_USB_HPRT_PRTENA_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTENCHNG (0x1UL << 3) /**< Port Enable/Disable Change */ +#define _USB_HPRT_PRTENCHNG_SHIFT 3 /**< Shift value for USB_PRTENCHNG */ +#define _USB_HPRT_PRTENCHNG_MASK 0x8UL /**< Bit mask for USB_PRTENCHNG */ +#define _USB_HPRT_PRTENCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTENCHNG_DEFAULT (_USB_HPRT_PRTENCHNG_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTOVRCURRACT (0x1UL << 4) /**< Port Overcurrent Active */ +#define _USB_HPRT_PRTOVRCURRACT_SHIFT 4 /**< Shift value for USB_PRTOVRCURRACT */ +#define _USB_HPRT_PRTOVRCURRACT_MASK 0x10UL /**< Bit mask for USB_PRTOVRCURRACT */ +#define _USB_HPRT_PRTOVRCURRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTOVRCURRACT_DEFAULT (_USB_HPRT_PRTOVRCURRACT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTOVRCURRCHNG (0x1UL << 5) /**< Port Overcurrent Change */ +#define _USB_HPRT_PRTOVRCURRCHNG_SHIFT 5 /**< Shift value for USB_PRTOVRCURRCHNG */ +#define _USB_HPRT_PRTOVRCURRCHNG_MASK 0x20UL /**< Bit mask for USB_PRTOVRCURRCHNG */ +#define _USB_HPRT_PRTOVRCURRCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTOVRCURRCHNG_DEFAULT (_USB_HPRT_PRTOVRCURRCHNG_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTRES (0x1UL << 6) /**< Port Resume */ +#define _USB_HPRT_PRTRES_SHIFT 6 /**< Shift value for USB_PRTRES */ +#define _USB_HPRT_PRTRES_MASK 0x40UL /**< Bit mask for USB_PRTRES */ +#define _USB_HPRT_PRTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTRES_DEFAULT (_USB_HPRT_PRTRES_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTSUSP (0x1UL << 7) /**< Port Suspend */ +#define _USB_HPRT_PRTSUSP_SHIFT 7 /**< Shift value for USB_PRTSUSP */ +#define _USB_HPRT_PRTSUSP_MASK 0x80UL /**< Bit mask for USB_PRTSUSP */ +#define _USB_HPRT_PRTSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTSUSP_DEFAULT (_USB_HPRT_PRTSUSP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTRST (0x1UL << 8) /**< Port Reset */ +#define _USB_HPRT_PRTRST_SHIFT 8 /**< Shift value for USB_PRTRST */ +#define _USB_HPRT_PRTRST_MASK 0x100UL /**< Bit mask for USB_PRTRST */ +#define _USB_HPRT_PRTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTRST_DEFAULT (_USB_HPRT_PRTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HPRT */ +#define _USB_HPRT_PRTLNSTS_SHIFT 10 /**< Shift value for USB_PRTLNSTS */ +#define _USB_HPRT_PRTLNSTS_MASK 0xC00UL /**< Bit mask for USB_PRTLNSTS */ +#define _USB_HPRT_PRTLNSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTLNSTS_DEFAULT (_USB_HPRT_PRTLNSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTPWR (0x1UL << 12) /**< Port Power */ +#define _USB_HPRT_PRTPWR_SHIFT 12 /**< Shift value for USB_PRTPWR */ +#define _USB_HPRT_PRTPWR_MASK 0x1000UL /**< Bit mask for USB_PRTPWR */ +#define _USB_HPRT_PRTPWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define _USB_HPRT_PRTPWR_OFF 0x00000000UL /**< Mode OFF for USB_HPRT */ +#define _USB_HPRT_PRTPWR_ON 0x00000001UL /**< Mode ON for USB_HPRT */ +#define USB_HPRT_PRTPWR_DEFAULT (_USB_HPRT_PRTPWR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTPWR_OFF (_USB_HPRT_PRTPWR_OFF << 12) /**< Shifted mode OFF for USB_HPRT */ +#define USB_HPRT_PRTPWR_ON (_USB_HPRT_PRTPWR_ON << 12) /**< Shifted mode ON for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_SHIFT 13 /**< Shift value for USB_PRTTSTCTL */ +#define _USB_HPRT_PRTTSTCTL_MASK 0x1E000UL /**< Bit mask for USB_PRTTSTCTL */ +#define _USB_HPRT_PRTTSTCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_DISABLE 0x00000000UL /**< Mode DISABLE for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_J 0x00000001UL /**< Mode J for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_K 0x00000002UL /**< Mode K for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_SE0NAK 0x00000003UL /**< Mode SE0NAK for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_PACKET 0x00000004UL /**< Mode PACKET for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_FORCE 0x00000005UL /**< Mode FORCE for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_DEFAULT (_USB_HPRT_PRTTSTCTL_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_DISABLE (_USB_HPRT_PRTTSTCTL_DISABLE << 13) /**< Shifted mode DISABLE for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_J (_USB_HPRT_PRTTSTCTL_J << 13) /**< Shifted mode J for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_K (_USB_HPRT_PRTTSTCTL_K << 13) /**< Shifted mode K for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_SE0NAK (_USB_HPRT_PRTTSTCTL_SE0NAK << 13) /**< Shifted mode SE0NAK for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_PACKET (_USB_HPRT_PRTTSTCTL_PACKET << 13) /**< Shifted mode PACKET for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_FORCE (_USB_HPRT_PRTTSTCTL_FORCE << 13) /**< Shifted mode FORCE for USB_HPRT */ +#define _USB_HPRT_PRTSPD_SHIFT 17 /**< Shift value for USB_PRTSPD */ +#define _USB_HPRT_PRTSPD_MASK 0x60000UL /**< Bit mask for USB_PRTSPD */ +#define _USB_HPRT_PRTSPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */ +#define _USB_HPRT_PRTSPD_FS 0x00000001UL /**< Mode FS for USB_HPRT */ +#define _USB_HPRT_PRTSPD_LS 0x00000002UL /**< Mode LS for USB_HPRT */ +#define USB_HPRT_PRTSPD_DEFAULT (_USB_HPRT_PRTSPD_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTSPD_FS (_USB_HPRT_PRTSPD_FS << 17) /**< Shifted mode FS for USB_HPRT */ +#define USB_HPRT_PRTSPD_LS (_USB_HPRT_PRTSPD_LS << 17) /**< Shifted mode LS for USB_HPRT */ + +/* Bit fields for USB HC_CHAR */ +#define _USB_HC_CHAR_RESETVALUE 0x00000000UL /**< Default value for USB_HC_CHAR */ +#define _USB_HC_CHAR_MASK 0xFFFEFFFFUL /**< Mask for USB_HC_CHAR */ +#define _USB_HC_CHAR_MPS_SHIFT 0 /**< Shift value for USB_MPS */ +#define _USB_HC_CHAR_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */ +#define _USB_HC_CHAR_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_MPS_DEFAULT (_USB_HC_CHAR_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPNUM_SHIFT 11 /**< Shift value for USB_EPNUM */ +#define _USB_HC_CHAR_EPNUM_MASK 0x7800UL /**< Bit mask for USB_EPNUM */ +#define _USB_HC_CHAR_EPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPNUM_DEFAULT (_USB_HC_CHAR_EPNUM_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPDIR (0x1UL << 15) /**< Endpoint Direction */ +#define _USB_HC_CHAR_EPDIR_SHIFT 15 /**< Shift value for USB_EPDIR */ +#define _USB_HC_CHAR_EPDIR_MASK 0x8000UL /**< Bit mask for USB_EPDIR */ +#define _USB_HC_CHAR_EPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPDIR_OUT 0x00000000UL /**< Mode OUT for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPDIR_IN 0x00000001UL /**< Mode IN for USB_HC_CHAR */ +#define USB_HC_CHAR_EPDIR_DEFAULT (_USB_HC_CHAR_EPDIR_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPDIR_OUT (_USB_HC_CHAR_EPDIR_OUT << 15) /**< Shifted mode OUT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPDIR_IN (_USB_HC_CHAR_EPDIR_IN << 15) /**< Shifted mode IN for USB_HC_CHAR */ +#define USB_HC_CHAR_LSPDDEV (0x1UL << 17) /**< Low-Speed Device */ +#define _USB_HC_CHAR_LSPDDEV_SHIFT 17 /**< Shift value for USB_LSPDDEV */ +#define _USB_HC_CHAR_LSPDDEV_MASK 0x20000UL /**< Bit mask for USB_LSPDDEV */ +#define _USB_HC_CHAR_LSPDDEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_LSPDDEV_DEFAULT (_USB_HC_CHAR_LSPDDEV_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ +#define _USB_HC_CHAR_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ +#define _USB_HC_CHAR_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPTYPE_DEFAULT (_USB_HC_CHAR_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPTYPE_CONTROL (_USB_HC_CHAR_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_HC_CHAR */ +#define USB_HC_CHAR_EPTYPE_ISO (_USB_HC_CHAR_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_HC_CHAR */ +#define USB_HC_CHAR_EPTYPE_BULK (_USB_HC_CHAR_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_HC_CHAR */ +#define USB_HC_CHAR_EPTYPE_INT (_USB_HC_CHAR_EPTYPE_INT << 18) /**< Shifted mode INT for USB_HC_CHAR */ +#define _USB_HC_CHAR_MC_SHIFT 20 /**< Shift value for USB_MC */ +#define _USB_HC_CHAR_MC_MASK 0x300000UL /**< Bit mask for USB_MC */ +#define _USB_HC_CHAR_MC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_MC_DEFAULT (_USB_HC_CHAR_MC_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_HC_CHAR */ +#define _USB_HC_CHAR_DEVADDR_SHIFT 22 /**< Shift value for USB_DEVADDR */ +#define _USB_HC_CHAR_DEVADDR_MASK 0x1FC00000UL /**< Bit mask for USB_DEVADDR */ +#define _USB_HC_CHAR_DEVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_DEVADDR_DEFAULT (_USB_HC_CHAR_DEVADDR_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_ODDFRM (0x1UL << 29) /**< Odd Frame */ +#define _USB_HC_CHAR_ODDFRM_SHIFT 29 /**< Shift value for USB_ODDFRM */ +#define _USB_HC_CHAR_ODDFRM_MASK 0x20000000UL /**< Bit mask for USB_ODDFRM */ +#define _USB_HC_CHAR_ODDFRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_ODDFRM_DEFAULT (_USB_HC_CHAR_ODDFRM_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_CHDIS (0x1UL << 30) /**< Channel Disable */ +#define _USB_HC_CHAR_CHDIS_SHIFT 30 /**< Shift value for USB_CHDIS */ +#define _USB_HC_CHAR_CHDIS_MASK 0x40000000UL /**< Bit mask for USB_CHDIS */ +#define _USB_HC_CHAR_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_CHDIS_DEFAULT (_USB_HC_CHAR_CHDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_CHENA (0x1UL << 31) /**< Channel Enable */ +#define _USB_HC_CHAR_CHENA_SHIFT 31 /**< Shift value for USB_CHENA */ +#define _USB_HC_CHAR_CHENA_MASK 0x80000000UL /**< Bit mask for USB_CHENA */ +#define _USB_HC_CHAR_CHENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_CHENA_DEFAULT (_USB_HC_CHAR_CHENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_HC_CHAR */ + +/* Bit fields for USB HC_SPLT */ +#define _USB_HC_SPLT_RESETVALUE 0x00000000UL /**< Default value for USB_HC_SPLT */ +#define _USB_HC_SPLT_MASK 0x8001FFFFUL /**< Mask for USB_HC_SPLT */ +#define _USB_HC_SPLT_PRTADDR_SHIFT 0 /**< Shift value for USB_PRTADDR */ +#define _USB_HC_SPLT_PRTADDR_MASK 0x7FUL /**< Bit mask for USB_PRTADDR */ +#define _USB_HC_SPLT_PRTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_SPLT */ +#define USB_HC_SPLT_PRTADDR_DEFAULT (_USB_HC_SPLT_PRTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_SPLT */ +#define _USB_HC_SPLT_HUBADDR_SHIFT 7 /**< Shift value for USB_HUBADDR */ +#define _USB_HC_SPLT_HUBADDR_MASK 0x3F80UL /**< Bit mask for USB_HUBADDR */ +#define _USB_HC_SPLT_HUBADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_SPLT */ +#define USB_HC_SPLT_HUBADDR_DEFAULT (_USB_HC_SPLT_HUBADDR_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HC_SPLT */ +#define _USB_HC_SPLT_XACTPOS_SHIFT 14 /**< Shift value for USB_XACTPOS */ +#define _USB_HC_SPLT_XACTPOS_MASK 0xC000UL /**< Bit mask for USB_XACTPOS */ +#define _USB_HC_SPLT_XACTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_SPLT */ +#define USB_HC_SPLT_XACTPOS_DEFAULT (_USB_HC_SPLT_XACTPOS_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_HC_SPLT */ +#define USB_HC_SPLT_COMPSPLT (0x1UL << 16) /**< Do Complete Split */ +#define _USB_HC_SPLT_COMPSPLT_SHIFT 16 /**< Shift value for USB_COMPSPLT */ +#define _USB_HC_SPLT_COMPSPLT_MASK 0x10000UL /**< Bit mask for USB_COMPSPLT */ +#define _USB_HC_SPLT_COMPSPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_SPLT */ +#define USB_HC_SPLT_COMPSPLT_DEFAULT (_USB_HC_SPLT_COMPSPLT_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HC_SPLT */ +#define USB_HC_SPLT_SPLTENA (0x1UL << 31) /**< Split Enable */ +#define _USB_HC_SPLT_SPLTENA_SHIFT 31 /**< Shift value for USB_SPLTENA */ +#define _USB_HC_SPLT_SPLTENA_MASK 0x80000000UL /**< Bit mask for USB_SPLTENA */ +#define _USB_HC_SPLT_SPLTENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_SPLT */ +#define USB_HC_SPLT_SPLTENA_DEFAULT (_USB_HC_SPLT_SPLTENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_HC_SPLT */ + +/* Bit fields for USB HC_INT */ +#define _USB_HC_INT_RESETVALUE 0x00000000UL /**< Default value for USB_HC_INT */ +#define _USB_HC_INT_MASK 0x000007BFUL /**< Mask for USB_HC_INT */ +#define USB_HC_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed */ +#define _USB_HC_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ +#define _USB_HC_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ +#define _USB_HC_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_XFERCOMPL_DEFAULT (_USB_HC_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_CHHLTD (0x1UL << 1) /**< Channel Halted */ +#define _USB_HC_INT_CHHLTD_SHIFT 1 /**< Shift value for USB_CHHLTD */ +#define _USB_HC_INT_CHHLTD_MASK 0x2UL /**< Bit mask for USB_CHHLTD */ +#define _USB_HC_INT_CHHLTD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_CHHLTD_DEFAULT (_USB_HC_INT_CHHLTD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_AHBERR (0x1UL << 2) /**< AHB Error */ +#define _USB_HC_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ +#define _USB_HC_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ +#define _USB_HC_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_AHBERR_DEFAULT (_USB_HC_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_STALL (0x1UL << 3) /**< STALL Response Received Interrupt */ +#define _USB_HC_INT_STALL_SHIFT 3 /**< Shift value for USB_STALL */ +#define _USB_HC_INT_STALL_MASK 0x8UL /**< Bit mask for USB_STALL */ +#define _USB_HC_INT_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_STALL_DEFAULT (_USB_HC_INT_STALL_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_NAK (0x1UL << 4) /**< NAK Response Received Interrupt */ +#define _USB_HC_INT_NAK_SHIFT 4 /**< Shift value for USB_NAK */ +#define _USB_HC_INT_NAK_MASK 0x10UL /**< Bit mask for USB_NAK */ +#define _USB_HC_INT_NAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_NAK_DEFAULT (_USB_HC_INT_NAK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_ACK (0x1UL << 5) /**< ACK Response Received/Transmitted Interrupt */ +#define _USB_HC_INT_ACK_SHIFT 5 /**< Shift value for USB_ACK */ +#define _USB_HC_INT_ACK_MASK 0x20UL /**< Bit mask for USB_ACK */ +#define _USB_HC_INT_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_ACK_DEFAULT (_USB_HC_INT_ACK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_XACTERR (0x1UL << 7) /**< Transaction Error */ +#define _USB_HC_INT_XACTERR_SHIFT 7 /**< Shift value for USB_XACTERR */ +#define _USB_HC_INT_XACTERR_MASK 0x80UL /**< Bit mask for USB_XACTERR */ +#define _USB_HC_INT_XACTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_XACTERR_DEFAULT (_USB_HC_INT_XACTERR_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_BBLERR (0x1UL << 8) /**< Babble Error */ +#define _USB_HC_INT_BBLERR_SHIFT 8 /**< Shift value for USB_BBLERR */ +#define _USB_HC_INT_BBLERR_MASK 0x100UL /**< Bit mask for USB_BBLERR */ +#define _USB_HC_INT_BBLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_BBLERR_DEFAULT (_USB_HC_INT_BBLERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_FRMOVRUN (0x1UL << 9) /**< Frame Overrun */ +#define _USB_HC_INT_FRMOVRUN_SHIFT 9 /**< Shift value for USB_FRMOVRUN */ +#define _USB_HC_INT_FRMOVRUN_MASK 0x200UL /**< Bit mask for USB_FRMOVRUN */ +#define _USB_HC_INT_FRMOVRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_FRMOVRUN_DEFAULT (_USB_HC_INT_FRMOVRUN_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_DATATGLERR (0x1UL << 10) /**< Data Toggle Error */ +#define _USB_HC_INT_DATATGLERR_SHIFT 10 /**< Shift value for USB_DATATGLERR */ +#define _USB_HC_INT_DATATGLERR_MASK 0x400UL /**< Bit mask for USB_DATATGLERR */ +#define _USB_HC_INT_DATATGLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_DATATGLERR_DEFAULT (_USB_HC_INT_DATATGLERR_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HC_INT */ + +/* Bit fields for USB HC_INTMSK */ +#define _USB_HC_INTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_HC_INTMSK */ +#define _USB_HC_INTMSK_MASK 0x000007BFUL /**< Mask for USB_HC_INTMSK */ +#define USB_HC_INTMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Mask */ +#define _USB_HC_INTMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */ +#define _USB_HC_INTMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */ +#define _USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT (_USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_CHHLTDMSK (0x1UL << 1) /**< Channel Halted Mask */ +#define _USB_HC_INTMSK_CHHLTDMSK_SHIFT 1 /**< Shift value for USB_CHHLTDMSK */ +#define _USB_HC_INTMSK_CHHLTDMSK_MASK 0x2UL /**< Bit mask for USB_CHHLTDMSK */ +#define _USB_HC_INTMSK_CHHLTDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_CHHLTDMSK_DEFAULT (_USB_HC_INTMSK_CHHLTDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error Mask */ +#define _USB_HC_INTMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */ +#define _USB_HC_INTMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */ +#define _USB_HC_INTMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_AHBERRMSK_DEFAULT (_USB_HC_INTMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_STALLMSK (0x1UL << 3) /**< STALL Response Received Interrupt Mask */ +#define _USB_HC_INTMSK_STALLMSK_SHIFT 3 /**< Shift value for USB_STALLMSK */ +#define _USB_HC_INTMSK_STALLMSK_MASK 0x8UL /**< Bit mask for USB_STALLMSK */ +#define _USB_HC_INTMSK_STALLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_STALLMSK_DEFAULT (_USB_HC_INTMSK_STALLMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_NAKMSK (0x1UL << 4) /**< NAK Response Received Interrupt Mask */ +#define _USB_HC_INTMSK_NAKMSK_SHIFT 4 /**< Shift value for USB_NAKMSK */ +#define _USB_HC_INTMSK_NAKMSK_MASK 0x10UL /**< Bit mask for USB_NAKMSK */ +#define _USB_HC_INTMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_NAKMSK_DEFAULT (_USB_HC_INTMSK_NAKMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_ACKMSK (0x1UL << 5) /**< ACK Response Received/Transmitted Interrupt Mask */ +#define _USB_HC_INTMSK_ACKMSK_SHIFT 5 /**< Shift value for USB_ACKMSK */ +#define _USB_HC_INTMSK_ACKMSK_MASK 0x20UL /**< Bit mask for USB_ACKMSK */ +#define _USB_HC_INTMSK_ACKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_ACKMSK_DEFAULT (_USB_HC_INTMSK_ACKMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_XACTERRMSK (0x1UL << 7) /**< Transaction Error Mask */ +#define _USB_HC_INTMSK_XACTERRMSK_SHIFT 7 /**< Shift value for USB_XACTERRMSK */ +#define _USB_HC_INTMSK_XACTERRMSK_MASK 0x80UL /**< Bit mask for USB_XACTERRMSK */ +#define _USB_HC_INTMSK_XACTERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_XACTERRMSK_DEFAULT (_USB_HC_INTMSK_XACTERRMSK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_BBLERRMSK (0x1UL << 8) /**< Babble Error Mask */ +#define _USB_HC_INTMSK_BBLERRMSK_SHIFT 8 /**< Shift value for USB_BBLERRMSK */ +#define _USB_HC_INTMSK_BBLERRMSK_MASK 0x100UL /**< Bit mask for USB_BBLERRMSK */ +#define _USB_HC_INTMSK_BBLERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_BBLERRMSK_DEFAULT (_USB_HC_INTMSK_BBLERRMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_FRMOVRUNMSK (0x1UL << 9) /**< Frame Overrun Mask */ +#define _USB_HC_INTMSK_FRMOVRUNMSK_SHIFT 9 /**< Shift value for USB_FRMOVRUNMSK */ +#define _USB_HC_INTMSK_FRMOVRUNMSK_MASK 0x200UL /**< Bit mask for USB_FRMOVRUNMSK */ +#define _USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT (_USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_DATATGLERRMSK (0x1UL << 10) /**< Data Toggle Error Mask */ +#define _USB_HC_INTMSK_DATATGLERRMSK_SHIFT 10 /**< Shift value for USB_DATATGLERRMSK */ +#define _USB_HC_INTMSK_DATATGLERRMSK_MASK 0x400UL /**< Bit mask for USB_DATATGLERRMSK */ +#define _USB_HC_INTMSK_DATATGLERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_DATATGLERRMSK_DEFAULT (_USB_HC_INTMSK_DATATGLERRMSK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HC_INTMSK */ + +/* Bit fields for USB HC_TSIZ */ +#define _USB_HC_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ +#define _USB_HC_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */ +#define _USB_HC_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */ +#define USB_HC_TSIZ_XFERSIZE_DEFAULT (_USB_HC_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ +#define _USB_HC_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */ +#define _USB_HC_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PKTCNT_DEFAULT (_USB_HC_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PID_SHIFT 29 /**< Shift value for USB_PID */ +#define _USB_HC_TSIZ_PID_MASK 0x60000000UL /**< Bit mask for USB_PID */ +#define _USB_HC_TSIZ_PID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PID_DATA0 0x00000000UL /**< Mode DATA0 for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PID_DATA2 0x00000001UL /**< Mode DATA2 for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PID_DATA1 0x00000002UL /**< Mode DATA1 for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PID_MDATA 0x00000003UL /**< Mode MDATA for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PID_DEFAULT (_USB_HC_TSIZ_PID_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PID_DATA0 (_USB_HC_TSIZ_PID_DATA0 << 29) /**< Shifted mode DATA0 for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PID_DATA2 (_USB_HC_TSIZ_PID_DATA2 << 29) /**< Shifted mode DATA2 for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PID_DATA1 (_USB_HC_TSIZ_PID_DATA1 << 29) /**< Shifted mode DATA1 for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PID_MDATA (_USB_HC_TSIZ_PID_MDATA << 29) /**< Shifted mode MDATA for USB_HC_TSIZ */ + +/* Bit fields for USB HC_DMAADDR */ +#define _USB_HC_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_HC_DMAADDR */ +#define _USB_HC_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_HC_DMAADDR */ +#define _USB_HC_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ +#define _USB_HC_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ +#define _USB_HC_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_DMAADDR */ +#define USB_HC_DMAADDR_DMAADDR_DEFAULT (_USB_HC_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_DMAADDR */ + +/* Bit fields for USB DCFG */ +#define _USB_DCFG_RESETVALUE 0x08000000UL /**< Default value for USB_DCFG */ +#define _USB_DCFG_MASK 0xFC00FFFFUL /**< Mask for USB_DCFG */ +#define _USB_DCFG_DEVSPD_SHIFT 0 /**< Shift value for USB_DEVSPD */ +#define _USB_DCFG_DEVSPD_MASK 0x3UL /**< Bit mask for USB_DEVSPD */ +#define _USB_DCFG_DEVSPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ +#define _USB_DCFG_DEVSPD_LS 0x00000002UL /**< Mode LS for USB_DCFG */ +#define _USB_DCFG_DEVSPD_FS 0x00000003UL /**< Mode FS for USB_DCFG */ +#define USB_DCFG_DEVSPD_DEFAULT (_USB_DCFG_DEVSPD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DCFG */ +#define USB_DCFG_DEVSPD_LS (_USB_DCFG_DEVSPD_LS << 0) /**< Shifted mode LS for USB_DCFG */ +#define USB_DCFG_DEVSPD_FS (_USB_DCFG_DEVSPD_FS << 0) /**< Shifted mode FS for USB_DCFG */ +#define USB_DCFG_NZSTSOUTHSHK (0x1UL << 2) /**< Non-Zero-Length Status OUT Handshake */ +#define _USB_DCFG_NZSTSOUTHSHK_SHIFT 2 /**< Shift value for USB_NZSTSOUTHSHK */ +#define _USB_DCFG_NZSTSOUTHSHK_MASK 0x4UL /**< Bit mask for USB_NZSTSOUTHSHK */ +#define _USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ +#define USB_DCFG_NZSTSOUTHSHK_DEFAULT (_USB_DCFG_NZSTSOUTHSHK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DCFG */ +#define USB_DCFG_ENA32KHZSUSP (0x1UL << 3) /**< Enable 32 kHz Suspend Mode */ +#define _USB_DCFG_ENA32KHZSUSP_SHIFT 3 /**< Shift value for USB_ENA32KHZSUSP */ +#define _USB_DCFG_ENA32KHZSUSP_MASK 0x8UL /**< Bit mask for USB_ENA32KHZSUSP */ +#define _USB_DCFG_ENA32KHZSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ +#define USB_DCFG_ENA32KHZSUSP_DEFAULT (_USB_DCFG_ENA32KHZSUSP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DCFG */ +#define _USB_DCFG_DEVADDR_SHIFT 4 /**< Shift value for USB_DEVADDR */ +#define _USB_DCFG_DEVADDR_MASK 0x7F0UL /**< Bit mask for USB_DEVADDR */ +#define _USB_DCFG_DEVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ +#define USB_DCFG_DEVADDR_DEFAULT (_USB_DCFG_DEVADDR_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DCFG */ +#define _USB_DCFG_PERFRINT_SHIFT 11 /**< Shift value for USB_PERFRINT */ +#define _USB_DCFG_PERFRINT_MASK 0x1800UL /**< Bit mask for USB_PERFRINT */ +#define _USB_DCFG_PERFRINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ +#define _USB_DCFG_PERFRINT_80PCNT 0x00000000UL /**< Mode 80PCNT for USB_DCFG */ +#define _USB_DCFG_PERFRINT_85PCNT 0x00000001UL /**< Mode 85PCNT for USB_DCFG */ +#define _USB_DCFG_PERFRINT_90PCNT 0x00000002UL /**< Mode 90PCNT for USB_DCFG */ +#define _USB_DCFG_PERFRINT_95PCNT 0x00000003UL /**< Mode 95PCNT for USB_DCFG */ +#define USB_DCFG_PERFRINT_DEFAULT (_USB_DCFG_PERFRINT_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DCFG */ +#define USB_DCFG_PERFRINT_80PCNT (_USB_DCFG_PERFRINT_80PCNT << 11) /**< Shifted mode 80PCNT for USB_DCFG */ +#define USB_DCFG_PERFRINT_85PCNT (_USB_DCFG_PERFRINT_85PCNT << 11) /**< Shifted mode 85PCNT for USB_DCFG */ +#define USB_DCFG_PERFRINT_90PCNT (_USB_DCFG_PERFRINT_90PCNT << 11) /**< Shifted mode 90PCNT for USB_DCFG */ +#define USB_DCFG_PERFRINT_95PCNT (_USB_DCFG_PERFRINT_95PCNT << 11) /**< Shifted mode 95PCNT for USB_DCFG */ +#define USB_DCFG_ENDEVOUTNAK (0x1UL << 13) /**< Enable Device OUT NAK */ +#define _USB_DCFG_ENDEVOUTNAK_SHIFT 13 /**< Shift value for USB_ENDEVOUTNAK */ +#define _USB_DCFG_ENDEVOUTNAK_MASK 0x2000UL /**< Bit mask for USB_ENDEVOUTNAK */ +#define _USB_DCFG_ENDEVOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ +#define USB_DCFG_ENDEVOUTNAK_DEFAULT (_USB_DCFG_ENDEVOUTNAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DCFG */ +#define USB_DCFG_XCVRDLY (0x1UL << 14) /**< */ +#define _USB_DCFG_XCVRDLY_SHIFT 14 /**< Shift value for USB_XCVRDLY */ +#define _USB_DCFG_XCVRDLY_MASK 0x4000UL /**< Bit mask for USB_XCVRDLY */ +#define _USB_DCFG_XCVRDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ +#define USB_DCFG_XCVRDLY_DEFAULT (_USB_DCFG_XCVRDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_DCFG */ +#define USB_DCFG_ERRATICINTMSK (0x1UL << 15) /**< */ +#define _USB_DCFG_ERRATICINTMSK_SHIFT 15 /**< Shift value for USB_ERRATICINTMSK */ +#define _USB_DCFG_ERRATICINTMSK_MASK 0x8000UL /**< Bit mask for USB_ERRATICINTMSK */ +#define _USB_DCFG_ERRATICINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ +#define USB_DCFG_ERRATICINTMSK_DEFAULT (_USB_DCFG_ERRATICINTMSK_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DCFG */ +#define _USB_DCFG_RESVALID_SHIFT 26 /**< Shift value for USB_RESVALID */ +#define _USB_DCFG_RESVALID_MASK 0xFC000000UL /**< Bit mask for USB_RESVALID */ +#define _USB_DCFG_RESVALID_DEFAULT 0x00000002UL /**< Mode DEFAULT for USB_DCFG */ +#define USB_DCFG_RESVALID_DEFAULT (_USB_DCFG_RESVALID_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DCFG */ + +/* Bit fields for USB DCTL */ +#define _USB_DCTL_RESETVALUE 0x00000002UL /**< Default value for USB_DCTL */ +#define _USB_DCTL_MASK 0x00018FFFUL /**< Mask for USB_DCTL */ +#define USB_DCTL_RMTWKUPSIG (0x1UL << 0) /**< Remote Wakeup Signaling */ +#define _USB_DCTL_RMTWKUPSIG_SHIFT 0 /**< Shift value for USB_RMTWKUPSIG */ +#define _USB_DCTL_RMTWKUPSIG_MASK 0x1UL /**< Bit mask for USB_RMTWKUPSIG */ +#define _USB_DCTL_RMTWKUPSIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_RMTWKUPSIG_DEFAULT (_USB_DCTL_RMTWKUPSIG_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_SFTDISCON (0x1UL << 1) /**< Soft Disconnect */ +#define _USB_DCTL_SFTDISCON_SHIFT 1 /**< Shift value for USB_SFTDISCON */ +#define _USB_DCTL_SFTDISCON_MASK 0x2UL /**< Bit mask for USB_SFTDISCON */ +#define _USB_DCTL_SFTDISCON_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_SFTDISCON_DEFAULT (_USB_DCTL_SFTDISCON_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_GNPINNAKSTS (0x1UL << 2) /**< Global Non-periodic IN NAK Status */ +#define _USB_DCTL_GNPINNAKSTS_SHIFT 2 /**< Shift value for USB_GNPINNAKSTS */ +#define _USB_DCTL_GNPINNAKSTS_MASK 0x4UL /**< Bit mask for USB_GNPINNAKSTS */ +#define _USB_DCTL_GNPINNAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_GNPINNAKSTS_DEFAULT (_USB_DCTL_GNPINNAKSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_GOUTNAKSTS (0x1UL << 3) /**< Global OUT NAK Status */ +#define _USB_DCTL_GOUTNAKSTS_SHIFT 3 /**< Shift value for USB_GOUTNAKSTS */ +#define _USB_DCTL_GOUTNAKSTS_MASK 0x8UL /**< Bit mask for USB_GOUTNAKSTS */ +#define _USB_DCTL_GOUTNAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_GOUTNAKSTS_DEFAULT (_USB_DCTL_GOUTNAKSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DCTL */ +#define _USB_DCTL_TSTCTL_SHIFT 4 /**< Shift value for USB_TSTCTL */ +#define _USB_DCTL_TSTCTL_MASK 0x70UL /**< Bit mask for USB_TSTCTL */ +#define _USB_DCTL_TSTCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ +#define _USB_DCTL_TSTCTL_DISABLE 0x00000000UL /**< Mode DISABLE for USB_DCTL */ +#define _USB_DCTL_TSTCTL_J 0x00000001UL /**< Mode J for USB_DCTL */ +#define _USB_DCTL_TSTCTL_K 0x00000002UL /**< Mode K for USB_DCTL */ +#define _USB_DCTL_TSTCTL_SE0NAK 0x00000003UL /**< Mode SE0NAK for USB_DCTL */ +#define _USB_DCTL_TSTCTL_PACKET 0x00000004UL /**< Mode PACKET for USB_DCTL */ +#define _USB_DCTL_TSTCTL_FORCE 0x00000005UL /**< Mode FORCE for USB_DCTL */ +#define USB_DCTL_TSTCTL_DEFAULT (_USB_DCTL_TSTCTL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_TSTCTL_DISABLE (_USB_DCTL_TSTCTL_DISABLE << 4) /**< Shifted mode DISABLE for USB_DCTL */ +#define USB_DCTL_TSTCTL_J (_USB_DCTL_TSTCTL_J << 4) /**< Shifted mode J for USB_DCTL */ +#define USB_DCTL_TSTCTL_K (_USB_DCTL_TSTCTL_K << 4) /**< Shifted mode K for USB_DCTL */ +#define USB_DCTL_TSTCTL_SE0NAK (_USB_DCTL_TSTCTL_SE0NAK << 4) /**< Shifted mode SE0NAK for USB_DCTL */ +#define USB_DCTL_TSTCTL_PACKET (_USB_DCTL_TSTCTL_PACKET << 4) /**< Shifted mode PACKET for USB_DCTL */ +#define USB_DCTL_TSTCTL_FORCE (_USB_DCTL_TSTCTL_FORCE << 4) /**< Shifted mode FORCE for USB_DCTL */ +#define USB_DCTL_SGNPINNAK (0x1UL << 7) /**< Set Global Non-periodic IN NAK */ +#define _USB_DCTL_SGNPINNAK_SHIFT 7 /**< Shift value for USB_SGNPINNAK */ +#define _USB_DCTL_SGNPINNAK_MASK 0x80UL /**< Bit mask for USB_SGNPINNAK */ +#define _USB_DCTL_SGNPINNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_SGNPINNAK_DEFAULT (_USB_DCTL_SGNPINNAK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_CGNPINNAK (0x1UL << 8) /**< Clear Global Non-periodic IN NAK */ +#define _USB_DCTL_CGNPINNAK_SHIFT 8 /**< Shift value for USB_CGNPINNAK */ +#define _USB_DCTL_CGNPINNAK_MASK 0x100UL /**< Bit mask for USB_CGNPINNAK */ +#define _USB_DCTL_CGNPINNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_CGNPINNAK_DEFAULT (_USB_DCTL_CGNPINNAK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_SGOUTNAK (0x1UL << 9) /**< Set Global OUT NAK */ +#define _USB_DCTL_SGOUTNAK_SHIFT 9 /**< Shift value for USB_SGOUTNAK */ +#define _USB_DCTL_SGOUTNAK_MASK 0x200UL /**< Bit mask for USB_SGOUTNAK */ +#define _USB_DCTL_SGOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_SGOUTNAK_DEFAULT (_USB_DCTL_SGOUTNAK_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_CGOUTNAK (0x1UL << 10) /**< Clear Global OUT NAK */ +#define _USB_DCTL_CGOUTNAK_SHIFT 10 /**< Shift value for USB_CGOUTNAK */ +#define _USB_DCTL_CGOUTNAK_MASK 0x400UL /**< Bit mask for USB_CGOUTNAK */ +#define _USB_DCTL_CGOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_CGOUTNAK_DEFAULT (_USB_DCTL_CGOUTNAK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_PWRONPRGDONE (0x1UL << 11) /**< Power-On Programming Done */ +#define _USB_DCTL_PWRONPRGDONE_SHIFT 11 /**< Shift value for USB_PWRONPRGDONE */ +#define _USB_DCTL_PWRONPRGDONE_MASK 0x800UL /**< Bit mask for USB_PWRONPRGDONE */ +#define _USB_DCTL_PWRONPRGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_PWRONPRGDONE_DEFAULT (_USB_DCTL_PWRONPRGDONE_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_IGNRFRMNUM (0x1UL << 15) /**< Ignore Frame number For Isochronous End points */ +#define _USB_DCTL_IGNRFRMNUM_SHIFT 15 /**< Shift value for USB_IGNRFRMNUM */ +#define _USB_DCTL_IGNRFRMNUM_MASK 0x8000UL /**< Bit mask for USB_IGNRFRMNUM */ +#define _USB_DCTL_IGNRFRMNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_IGNRFRMNUM_DEFAULT (_USB_DCTL_IGNRFRMNUM_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_NAKONBBLE (0x1UL << 16) /**< NAK on Babble Error */ +#define _USB_DCTL_NAKONBBLE_SHIFT 16 /**< Shift value for USB_NAKONBBLE */ +#define _USB_DCTL_NAKONBBLE_MASK 0x10000UL /**< Bit mask for USB_NAKONBBLE */ +#define _USB_DCTL_NAKONBBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_NAKONBBLE_DEFAULT (_USB_DCTL_NAKONBBLE_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DCTL */ + +/* Bit fields for USB DSTS */ +#define _USB_DSTS_RESETVALUE 0x00000002UL /**< Default value for USB_DSTS */ +#define _USB_DSTS_MASK 0x00FFFF0FUL /**< Mask for USB_DSTS */ +#define USB_DSTS_SUSPSTS (0x1UL << 0) /**< Suspend Status */ +#define _USB_DSTS_SUSPSTS_SHIFT 0 /**< Shift value for USB_SUSPSTS */ +#define _USB_DSTS_SUSPSTS_MASK 0x1UL /**< Bit mask for USB_SUSPSTS */ +#define _USB_DSTS_SUSPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ +#define USB_DSTS_SUSPSTS_DEFAULT (_USB_DSTS_SUSPSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DSTS */ +#define _USB_DSTS_ENUMSPD_SHIFT 1 /**< Shift value for USB_ENUMSPD */ +#define _USB_DSTS_ENUMSPD_MASK 0x6UL /**< Bit mask for USB_ENUMSPD */ +#define _USB_DSTS_ENUMSPD_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DSTS */ +#define _USB_DSTS_ENUMSPD_LS 0x00000002UL /**< Mode LS for USB_DSTS */ +#define _USB_DSTS_ENUMSPD_FS 0x00000003UL /**< Mode FS for USB_DSTS */ +#define USB_DSTS_ENUMSPD_DEFAULT (_USB_DSTS_ENUMSPD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DSTS */ +#define USB_DSTS_ENUMSPD_LS (_USB_DSTS_ENUMSPD_LS << 1) /**< Shifted mode LS for USB_DSTS */ +#define USB_DSTS_ENUMSPD_FS (_USB_DSTS_ENUMSPD_FS << 1) /**< Shifted mode FS for USB_DSTS */ +#define USB_DSTS_ERRTICERR (0x1UL << 3) /**< Erratic Error */ +#define _USB_DSTS_ERRTICERR_SHIFT 3 /**< Shift value for USB_ERRTICERR */ +#define _USB_DSTS_ERRTICERR_MASK 0x8UL /**< Bit mask for USB_ERRTICERR */ +#define _USB_DSTS_ERRTICERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ +#define USB_DSTS_ERRTICERR_DEFAULT (_USB_DSTS_ERRTICERR_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DSTS */ +#define _USB_DSTS_SOFFN_SHIFT 8 /**< Shift value for USB_SOFFN */ +#define _USB_DSTS_SOFFN_MASK 0x3FFF00UL /**< Bit mask for USB_SOFFN */ +#define _USB_DSTS_SOFFN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ +#define USB_DSTS_SOFFN_DEFAULT (_USB_DSTS_SOFFN_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DSTS */ +#define _USB_DSTS_DEVLNSTS_SHIFT 22 /**< Shift value for USB_DEVLNSTS */ +#define _USB_DSTS_DEVLNSTS_MASK 0xC00000UL /**< Bit mask for USB_DEVLNSTS */ +#define _USB_DSTS_DEVLNSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ +#define USB_DSTS_DEVLNSTS_DEFAULT (_USB_DSTS_DEVLNSTS_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DSTS */ + +/* Bit fields for USB DIEPMSK */ +#define _USB_DIEPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DIEPMSK */ +#define _USB_DIEPMSK_MASK 0x0000217FUL /**< Mask for USB_DIEPMSK */ +#define USB_DIEPMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Interrupt Mask */ +#define _USB_DIEPMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */ +#define _USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */ +#define _USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_EPDISBLDMSK (0x1UL << 1) /**< Endpoint Disabled Interrupt Mask */ +#define _USB_DIEPMSK_EPDISBLDMSK_SHIFT 1 /**< Shift value for USB_EPDISBLDMSK */ +#define _USB_DIEPMSK_EPDISBLDMSK_MASK 0x2UL /**< Bit mask for USB_EPDISBLDMSK */ +#define _USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_EPDISBLDMSK_DEFAULT (_USB_DIEPMSK_EPDISBLDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error Mask */ +#define _USB_DIEPMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */ +#define _USB_DIEPMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */ +#define _USB_DIEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_AHBERRMSK_DEFAULT (_USB_DIEPMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_TIMEOUTMSK (0x1UL << 3) /**< Timeout Condition Mask */ +#define _USB_DIEPMSK_TIMEOUTMSK_SHIFT 3 /**< Shift value for USB_TIMEOUTMSK */ +#define _USB_DIEPMSK_TIMEOUTMSK_MASK 0x8UL /**< Bit mask for USB_TIMEOUTMSK */ +#define _USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_TIMEOUTMSK_DEFAULT (_USB_DIEPMSK_TIMEOUTMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_INTKNTXFEMPMSK (0x1UL << 4) /**< IN Token Received When TxFIFO Empty Mask */ +#define _USB_DIEPMSK_INTKNTXFEMPMSK_SHIFT 4 /**< Shift value for USB_INTKNTXFEMPMSK */ +#define _USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMPMSK */ +#define _USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT (_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_INTKNEPMISMSK (0x1UL << 5) /**< IN Token received with EP Mismatch Mask */ +#define _USB_DIEPMSK_INTKNEPMISMSK_SHIFT 5 /**< Shift value for USB_INTKNEPMISMSK */ +#define _USB_DIEPMSK_INTKNEPMISMSK_MASK 0x20UL /**< Bit mask for USB_INTKNEPMISMSK */ +#define _USB_DIEPMSK_INTKNEPMISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_INTKNEPMISMSK_DEFAULT (_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_INEPNAKEFFMSK (0x1UL << 6) /**< IN Endpoint NAK Effective Mask */ +#define _USB_DIEPMSK_INEPNAKEFFMSK_SHIFT 6 /**< Shift value for USB_INEPNAKEFFMSK */ +#define _USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFFMSK */ +#define _USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT (_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_TXFIFOUNDRNMSK (0x1UL << 8) /**< Fifo Underrun Mask */ +#define _USB_DIEPMSK_TXFIFOUNDRNMSK_SHIFT 8 /**< Shift value for USB_TXFIFOUNDRNMSK */ +#define _USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100UL /**< Bit mask for USB_TXFIFOUNDRNMSK */ +#define _USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT (_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_NAKMSK (0x1UL << 13) /**< NAK interrupt Mask */ +#define _USB_DIEPMSK_NAKMSK_SHIFT 13 /**< Shift value for USB_NAKMSK */ +#define _USB_DIEPMSK_NAKMSK_MASK 0x2000UL /**< Bit mask for USB_NAKMSK */ +#define _USB_DIEPMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_NAKMSK_DEFAULT (_USB_DIEPMSK_NAKMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEPMSK */ + +/* Bit fields for USB DOEPMSK */ +#define _USB_DOEPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DOEPMSK */ +#define _USB_DOEPMSK_MASK 0x0000317FUL /**< Mask for USB_DOEPMSK */ +#define USB_DOEPMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Interrupt Mask */ +#define _USB_DOEPMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */ +#define _USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */ +#define _USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_EPDISBLDMSK (0x1UL << 1) /**< Endpoint Disabled Interrupt Mask */ +#define _USB_DOEPMSK_EPDISBLDMSK_SHIFT 1 /**< Shift value for USB_EPDISBLDMSK */ +#define _USB_DOEPMSK_EPDISBLDMSK_MASK 0x2UL /**< Bit mask for USB_EPDISBLDMSK */ +#define _USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_EPDISBLDMSK_DEFAULT (_USB_DOEPMSK_EPDISBLDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error */ +#define _USB_DOEPMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */ +#define _USB_DOEPMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */ +#define _USB_DOEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_AHBERRMSK_DEFAULT (_USB_DOEPMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_SETUPMSK (0x1UL << 3) /**< SETUP Phase Done Mask */ +#define _USB_DOEPMSK_SETUPMSK_SHIFT 3 /**< Shift value for USB_SETUPMSK */ +#define _USB_DOEPMSK_SETUPMSK_MASK 0x8UL /**< Bit mask for USB_SETUPMSK */ +#define _USB_DOEPMSK_SETUPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_SETUPMSK_DEFAULT (_USB_DOEPMSK_SETUPMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_OUTTKNEPDISMSK (0x1UL << 4) /**< OUT Token Received when Endpoint Disabled Mask */ +#define _USB_DOEPMSK_OUTTKNEPDISMSK_SHIFT 4 /**< Shift value for USB_OUTTKNEPDISMSK */ +#define _USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDISMSK */ +#define _USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT (_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_STSPHSERCVDMSK (0x1UL << 5) /**< Status Phase Received Mask */ +#define _USB_DOEPMSK_STSPHSERCVDMSK_SHIFT 5 /**< Shift value for USB_STSPHSERCVDMSK */ +#define _USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20UL /**< Bit mask for USB_STSPHSERCVDMSK */ +#define _USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT (_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received Mask */ +#define _USB_DOEPMSK_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */ +#define _USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */ +#define _USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_BACK2BACKSETUP_DEFAULT (_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_OUTPKTERRMSK (0x1UL << 8) /**< OUT Packet Error Mask */ +#define _USB_DOEPMSK_OUTPKTERRMSK_SHIFT 8 /**< Shift value for USB_OUTPKTERRMSK */ +#define _USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100UL /**< Bit mask for USB_OUTPKTERRMSK */ +#define _USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_OUTPKTERRMSK_DEFAULT (_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_BBLEERRMSK (0x1UL << 12) /**< Babble Error interrupt Mask */ +#define _USB_DOEPMSK_BBLEERRMSK_SHIFT 12 /**< Shift value for USB_BBLEERRMSK */ +#define _USB_DOEPMSK_BBLEERRMSK_MASK 0x1000UL /**< Bit mask for USB_BBLEERRMSK */ +#define _USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_BBLEERRMSK_DEFAULT (_USB_DOEPMSK_BBLEERRMSK_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_NAKMSK (0x1UL << 13) /**< NAK interrupt Mask */ +#define _USB_DOEPMSK_NAKMSK_SHIFT 13 /**< Shift value for USB_NAKMSK */ +#define _USB_DOEPMSK_NAKMSK_MASK 0x2000UL /**< Bit mask for USB_NAKMSK */ +#define _USB_DOEPMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_NAKMSK_DEFAULT (_USB_DOEPMSK_NAKMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEPMSK */ + +/* Bit fields for USB DAINT */ +#define _USB_DAINT_RESETVALUE 0x00000000UL /**< Default value for USB_DAINT */ +#define _USB_DAINT_MASK 0x007F007FUL /**< Mask for USB_DAINT */ +#define USB_DAINT_INEPINT0 (0x1UL << 0) /**< IN Endpoint 0 Interrupt Bit */ +#define _USB_DAINT_INEPINT0_SHIFT 0 /**< Shift value for USB_INEPINT0 */ +#define _USB_DAINT_INEPINT0_MASK 0x1UL /**< Bit mask for USB_INEPINT0 */ +#define _USB_DAINT_INEPINT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT0_DEFAULT (_USB_DAINT_INEPINT0_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT1 (0x1UL << 1) /**< IN Endpoint 1 Interrupt Bit */ +#define _USB_DAINT_INEPINT1_SHIFT 1 /**< Shift value for USB_INEPINT1 */ +#define _USB_DAINT_INEPINT1_MASK 0x2UL /**< Bit mask for USB_INEPINT1 */ +#define _USB_DAINT_INEPINT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT1_DEFAULT (_USB_DAINT_INEPINT1_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT2 (0x1UL << 2) /**< IN Endpoint 2 Interrupt Bit */ +#define _USB_DAINT_INEPINT2_SHIFT 2 /**< Shift value for USB_INEPINT2 */ +#define _USB_DAINT_INEPINT2_MASK 0x4UL /**< Bit mask for USB_INEPINT2 */ +#define _USB_DAINT_INEPINT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT2_DEFAULT (_USB_DAINT_INEPINT2_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT3 (0x1UL << 3) /**< IN Endpoint 3 Interrupt Bit */ +#define _USB_DAINT_INEPINT3_SHIFT 3 /**< Shift value for USB_INEPINT3 */ +#define _USB_DAINT_INEPINT3_MASK 0x8UL /**< Bit mask for USB_INEPINT3 */ +#define _USB_DAINT_INEPINT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT3_DEFAULT (_USB_DAINT_INEPINT3_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT4 (0x1UL << 4) /**< IN Endpoint 4 Interrupt Bit */ +#define _USB_DAINT_INEPINT4_SHIFT 4 /**< Shift value for USB_INEPINT4 */ +#define _USB_DAINT_INEPINT4_MASK 0x10UL /**< Bit mask for USB_INEPINT4 */ +#define _USB_DAINT_INEPINT4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT4_DEFAULT (_USB_DAINT_INEPINT4_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT5 (0x1UL << 5) /**< IN Endpoint 5 Interrupt Bit */ +#define _USB_DAINT_INEPINT5_SHIFT 5 /**< Shift value for USB_INEPINT5 */ +#define _USB_DAINT_INEPINT5_MASK 0x20UL /**< Bit mask for USB_INEPINT5 */ +#define _USB_DAINT_INEPINT5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT5_DEFAULT (_USB_DAINT_INEPINT5_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT6 (0x1UL << 6) /**< IN Endpoint 6 Interrupt Bit */ +#define _USB_DAINT_INEPINT6_SHIFT 6 /**< Shift value for USB_INEPINT6 */ +#define _USB_DAINT_INEPINT6_MASK 0x40UL /**< Bit mask for USB_INEPINT6 */ +#define _USB_DAINT_INEPINT6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT6_DEFAULT (_USB_DAINT_INEPINT6_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT0 (0x1UL << 16) /**< OUT Endpoint 0 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT0_SHIFT 16 /**< Shift value for USB_OUTEPINT0 */ +#define _USB_DAINT_OUTEPINT0_MASK 0x10000UL /**< Bit mask for USB_OUTEPINT0 */ +#define _USB_DAINT_OUTEPINT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT0_DEFAULT (_USB_DAINT_OUTEPINT0_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT1 (0x1UL << 17) /**< OUT Endpoint 1 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT1_SHIFT 17 /**< Shift value for USB_OUTEPINT1 */ +#define _USB_DAINT_OUTEPINT1_MASK 0x20000UL /**< Bit mask for USB_OUTEPINT1 */ +#define _USB_DAINT_OUTEPINT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT1_DEFAULT (_USB_DAINT_OUTEPINT1_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT2 (0x1UL << 18) /**< OUT Endpoint 2 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT2_SHIFT 18 /**< Shift value for USB_OUTEPINT2 */ +#define _USB_DAINT_OUTEPINT2_MASK 0x40000UL /**< Bit mask for USB_OUTEPINT2 */ +#define _USB_DAINT_OUTEPINT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT2_DEFAULT (_USB_DAINT_OUTEPINT2_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT3 (0x1UL << 19) /**< OUT Endpoint 3 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT3_SHIFT 19 /**< Shift value for USB_OUTEPINT3 */ +#define _USB_DAINT_OUTEPINT3_MASK 0x80000UL /**< Bit mask for USB_OUTEPINT3 */ +#define _USB_DAINT_OUTEPINT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT3_DEFAULT (_USB_DAINT_OUTEPINT3_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT4 (0x1UL << 20) /**< OUT Endpoint 4 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT4_SHIFT 20 /**< Shift value for USB_OUTEPINT4 */ +#define _USB_DAINT_OUTEPINT4_MASK 0x100000UL /**< Bit mask for USB_OUTEPINT4 */ +#define _USB_DAINT_OUTEPINT4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT4_DEFAULT (_USB_DAINT_OUTEPINT4_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT5 (0x1UL << 21) /**< OUT Endpoint 5 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT5_SHIFT 21 /**< Shift value for USB_OUTEPINT5 */ +#define _USB_DAINT_OUTEPINT5_MASK 0x200000UL /**< Bit mask for USB_OUTEPINT5 */ +#define _USB_DAINT_OUTEPINT5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT5_DEFAULT (_USB_DAINT_OUTEPINT5_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT6 (0x1UL << 22) /**< OUT Endpoint 6 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT6_SHIFT 22 /**< Shift value for USB_OUTEPINT6 */ +#define _USB_DAINT_OUTEPINT6_MASK 0x400000UL /**< Bit mask for USB_OUTEPINT6 */ +#define _USB_DAINT_OUTEPINT6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT6_DEFAULT (_USB_DAINT_OUTEPINT6_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DAINT */ + +/* Bit fields for USB DAINTMSK */ +#define _USB_DAINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DAINTMSK */ +#define _USB_DAINTMSK_MASK 0x007F007FUL /**< Mask for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK0 (0x1UL << 0) /**< IN Endpoint 0 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK0_SHIFT 0 /**< Shift value for USB_INEPMSK0 */ +#define _USB_DAINTMSK_INEPMSK0_MASK 0x1UL /**< Bit mask for USB_INEPMSK0 */ +#define _USB_DAINTMSK_INEPMSK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK0_DEFAULT (_USB_DAINTMSK_INEPMSK0_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK1 (0x1UL << 1) /**< IN Endpoint 1 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK1_SHIFT 1 /**< Shift value for USB_INEPMSK1 */ +#define _USB_DAINTMSK_INEPMSK1_MASK 0x2UL /**< Bit mask for USB_INEPMSK1 */ +#define _USB_DAINTMSK_INEPMSK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK1_DEFAULT (_USB_DAINTMSK_INEPMSK1_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK2 (0x1UL << 2) /**< IN Endpoint 2 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK2_SHIFT 2 /**< Shift value for USB_INEPMSK2 */ +#define _USB_DAINTMSK_INEPMSK2_MASK 0x4UL /**< Bit mask for USB_INEPMSK2 */ +#define _USB_DAINTMSK_INEPMSK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK2_DEFAULT (_USB_DAINTMSK_INEPMSK2_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK3 (0x1UL << 3) /**< IN Endpoint 3 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK3_SHIFT 3 /**< Shift value for USB_INEPMSK3 */ +#define _USB_DAINTMSK_INEPMSK3_MASK 0x8UL /**< Bit mask for USB_INEPMSK3 */ +#define _USB_DAINTMSK_INEPMSK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK3_DEFAULT (_USB_DAINTMSK_INEPMSK3_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK4 (0x1UL << 4) /**< IN Endpoint 4 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK4_SHIFT 4 /**< Shift value for USB_INEPMSK4 */ +#define _USB_DAINTMSK_INEPMSK4_MASK 0x10UL /**< Bit mask for USB_INEPMSK4 */ +#define _USB_DAINTMSK_INEPMSK4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK4_DEFAULT (_USB_DAINTMSK_INEPMSK4_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK5 (0x1UL << 5) /**< IN Endpoint 5 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK5_SHIFT 5 /**< Shift value for USB_INEPMSK5 */ +#define _USB_DAINTMSK_INEPMSK5_MASK 0x20UL /**< Bit mask for USB_INEPMSK5 */ +#define _USB_DAINTMSK_INEPMSK5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK5_DEFAULT (_USB_DAINTMSK_INEPMSK5_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK6 (0x1UL << 6) /**< IN Endpoint 6 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK6_SHIFT 6 /**< Shift value for USB_INEPMSK6 */ +#define _USB_DAINTMSK_INEPMSK6_MASK 0x40UL /**< Bit mask for USB_INEPMSK6 */ +#define _USB_DAINTMSK_INEPMSK6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK6_DEFAULT (_USB_DAINTMSK_INEPMSK6_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK0 (0x1UL << 16) /**< OUT Endpoint 0 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK0_SHIFT 16 /**< Shift value for USB_OUTEPMSK0 */ +#define _USB_DAINTMSK_OUTEPMSK0_MASK 0x10000UL /**< Bit mask for USB_OUTEPMSK0 */ +#define _USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK0_DEFAULT (_USB_DAINTMSK_OUTEPMSK0_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK1 (0x1UL << 17) /**< OUT Endpoint 1 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK1_SHIFT 17 /**< Shift value for USB_OUTEPMSK1 */ +#define _USB_DAINTMSK_OUTEPMSK1_MASK 0x20000UL /**< Bit mask for USB_OUTEPMSK1 */ +#define _USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK1_DEFAULT (_USB_DAINTMSK_OUTEPMSK1_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK2 (0x1UL << 18) /**< OUT Endpoint 2 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK2_SHIFT 18 /**< Shift value for USB_OUTEPMSK2 */ +#define _USB_DAINTMSK_OUTEPMSK2_MASK 0x40000UL /**< Bit mask for USB_OUTEPMSK2 */ +#define _USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK2_DEFAULT (_USB_DAINTMSK_OUTEPMSK2_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK3 (0x1UL << 19) /**< OUT Endpoint 3 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK3_SHIFT 19 /**< Shift value for USB_OUTEPMSK3 */ +#define _USB_DAINTMSK_OUTEPMSK3_MASK 0x80000UL /**< Bit mask for USB_OUTEPMSK3 */ +#define _USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK3_DEFAULT (_USB_DAINTMSK_OUTEPMSK3_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK4 (0x1UL << 20) /**< OUT Endpoint 4 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK4_SHIFT 20 /**< Shift value for USB_OUTEPMSK4 */ +#define _USB_DAINTMSK_OUTEPMSK4_MASK 0x100000UL /**< Bit mask for USB_OUTEPMSK4 */ +#define _USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK4_DEFAULT (_USB_DAINTMSK_OUTEPMSK4_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK5 (0x1UL << 21) /**< OUT Endpoint 5 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK5_SHIFT 21 /**< Shift value for USB_OUTEPMSK5 */ +#define _USB_DAINTMSK_OUTEPMSK5_MASK 0x200000UL /**< Bit mask for USB_OUTEPMSK5 */ +#define _USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK5_DEFAULT (_USB_DAINTMSK_OUTEPMSK5_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK6 (0x1UL << 22) /**< OUT Endpoint 6 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK6_SHIFT 22 /**< Shift value for USB_OUTEPMSK6 */ +#define _USB_DAINTMSK_OUTEPMSK6_MASK 0x400000UL /**< Bit mask for USB_OUTEPMSK6 */ +#define _USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK6_DEFAULT (_USB_DAINTMSK_OUTEPMSK6_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DAINTMSK */ + +/* Bit fields for USB DVBUSDIS */ +#define _USB_DVBUSDIS_RESETVALUE 0x000017D7UL /**< Default value for USB_DVBUSDIS */ +#define _USB_DVBUSDIS_MASK 0x0000FFFFUL /**< Mask for USB_DVBUSDIS */ +#define _USB_DVBUSDIS_DVBUSDIS_SHIFT 0 /**< Shift value for USB_DVBUSDIS */ +#define _USB_DVBUSDIS_DVBUSDIS_MASK 0xFFFFUL /**< Bit mask for USB_DVBUSDIS */ +#define _USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x000017D7UL /**< Mode DEFAULT for USB_DVBUSDIS */ +#define USB_DVBUSDIS_DVBUSDIS_DEFAULT (_USB_DVBUSDIS_DVBUSDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DVBUSDIS */ + +/* Bit fields for USB DVBUSPULSE */ +#define _USB_DVBUSPULSE_RESETVALUE 0x000005B8UL /**< Default value for USB_DVBUSPULSE */ +#define _USB_DVBUSPULSE_MASK 0x00000FFFUL /**< Mask for USB_DVBUSPULSE */ +#define _USB_DVBUSPULSE_DVBUSPULSE_SHIFT 0 /**< Shift value for USB_DVBUSPULSE */ +#define _USB_DVBUSPULSE_DVBUSPULSE_MASK 0xFFFUL /**< Bit mask for USB_DVBUSPULSE */ +#define _USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x000005B8UL /**< Mode DEFAULT for USB_DVBUSPULSE */ +#define USB_DVBUSPULSE_DVBUSPULSE_DEFAULT (_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DVBUSPULSE */ + +/* Bit fields for USB DTHRCTL */ +#define _USB_DTHRCTL_RESETVALUE 0x08100020UL /**< Default value for USB_DTHRCTL */ +#define _USB_DTHRCTL_MASK 0x0BFF1FFFUL /**< Mask for USB_DTHRCTL */ +#define USB_DTHRCTL_NONISOTHREN (0x1UL << 0) /**< Non-ISO IN Endpoints Threshold Enable */ +#define _USB_DTHRCTL_NONISOTHREN_SHIFT 0 /**< Shift value for USB_NONISOTHREN */ +#define _USB_DTHRCTL_NONISOTHREN_MASK 0x1UL /**< Bit mask for USB_NONISOTHREN */ +#define _USB_DTHRCTL_NONISOTHREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DTHRCTL */ +#define USB_DTHRCTL_NONISOTHREN_DEFAULT (_USB_DTHRCTL_NONISOTHREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DTHRCTL */ +#define USB_DTHRCTL_ISOTHREN (0x1UL << 1) /**< ISO IN Endpoints Threshold Enable */ +#define _USB_DTHRCTL_ISOTHREN_SHIFT 1 /**< Shift value for USB_ISOTHREN */ +#define _USB_DTHRCTL_ISOTHREN_MASK 0x2UL /**< Bit mask for USB_ISOTHREN */ +#define _USB_DTHRCTL_ISOTHREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DTHRCTL */ +#define USB_DTHRCTL_ISOTHREN_DEFAULT (_USB_DTHRCTL_ISOTHREN_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DTHRCTL */ +#define _USB_DTHRCTL_TXTHRLEN_SHIFT 2 /**< Shift value for USB_TXTHRLEN */ +#define _USB_DTHRCTL_TXTHRLEN_MASK 0x7FCUL /**< Bit mask for USB_TXTHRLEN */ +#define _USB_DTHRCTL_TXTHRLEN_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_DTHRCTL */ +#define USB_DTHRCTL_TXTHRLEN_DEFAULT (_USB_DTHRCTL_TXTHRLEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DTHRCTL */ +#define _USB_DTHRCTL_AHBTHRRATIO_SHIFT 11 /**< Shift value for USB_AHBTHRRATIO */ +#define _USB_DTHRCTL_AHBTHRRATIO_MASK 0x1800UL /**< Bit mask for USB_AHBTHRRATIO */ +#define _USB_DTHRCTL_AHBTHRRATIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DTHRCTL */ +#define _USB_DTHRCTL_AHBTHRRATIO_DIV1 0x00000000UL /**< Mode DIV1 for USB_DTHRCTL */ +#define _USB_DTHRCTL_AHBTHRRATIO_DIV2 0x00000001UL /**< Mode DIV2 for USB_DTHRCTL */ +#define _USB_DTHRCTL_AHBTHRRATIO_DIV4 0x00000002UL /**< Mode DIV4 for USB_DTHRCTL */ +#define _USB_DTHRCTL_AHBTHRRATIO_DIV8 0x00000003UL /**< Mode DIV8 for USB_DTHRCTL */ +#define USB_DTHRCTL_AHBTHRRATIO_DEFAULT (_USB_DTHRCTL_AHBTHRRATIO_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DTHRCTL */ +#define USB_DTHRCTL_AHBTHRRATIO_DIV1 (_USB_DTHRCTL_AHBTHRRATIO_DIV1 << 11) /**< Shifted mode DIV1 for USB_DTHRCTL */ +#define USB_DTHRCTL_AHBTHRRATIO_DIV2 (_USB_DTHRCTL_AHBTHRRATIO_DIV2 << 11) /**< Shifted mode DIV2 for USB_DTHRCTL */ +#define USB_DTHRCTL_AHBTHRRATIO_DIV4 (_USB_DTHRCTL_AHBTHRRATIO_DIV4 << 11) /**< Shifted mode DIV4 for USB_DTHRCTL */ +#define USB_DTHRCTL_AHBTHRRATIO_DIV8 (_USB_DTHRCTL_AHBTHRRATIO_DIV8 << 11) /**< Shifted mode DIV8 for USB_DTHRCTL */ +#define USB_DTHRCTL_RXTHREN (0x1UL << 16) /**< Receive Threshold Enable */ +#define _USB_DTHRCTL_RXTHREN_SHIFT 16 /**< Shift value for USB_RXTHREN */ +#define _USB_DTHRCTL_RXTHREN_MASK 0x10000UL /**< Bit mask for USB_RXTHREN */ +#define _USB_DTHRCTL_RXTHREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DTHRCTL */ +#define USB_DTHRCTL_RXTHREN_DEFAULT (_USB_DTHRCTL_RXTHREN_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DTHRCTL */ +#define _USB_DTHRCTL_RXTHRLEN_SHIFT 17 /**< Shift value for USB_RXTHRLEN */ +#define _USB_DTHRCTL_RXTHRLEN_MASK 0x3FE0000UL /**< Bit mask for USB_RXTHRLEN */ +#define _USB_DTHRCTL_RXTHRLEN_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_DTHRCTL */ +#define USB_DTHRCTL_RXTHRLEN_DEFAULT (_USB_DTHRCTL_RXTHRLEN_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DTHRCTL */ +#define USB_DTHRCTL_ARBPRKEN (0x1UL << 27) /**< Arbiter Parking Enable */ +#define _USB_DTHRCTL_ARBPRKEN_SHIFT 27 /**< Shift value for USB_ARBPRKEN */ +#define _USB_DTHRCTL_ARBPRKEN_MASK 0x8000000UL /**< Bit mask for USB_ARBPRKEN */ +#define _USB_DTHRCTL_ARBPRKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DTHRCTL */ +#define USB_DTHRCTL_ARBPRKEN_DEFAULT (_USB_DTHRCTL_ARBPRKEN_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DTHRCTL */ + +/* Bit fields for USB DIEPEMPMSK */ +#define _USB_DIEPEMPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DIEPEMPMSK */ +#define _USB_DIEPEMPMSK_MASK 0x0000FFFFUL /**< Mask for USB_DIEPEMPMSK */ +#define _USB_DIEPEMPMSK_INEPTXFEMPMSK_SHIFT 0 /**< Shift value for USB_INEPTXFEMPMSK */ +#define _USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK 0xFFFFUL /**< Bit mask for USB_INEPTXFEMPMSK */ +#define _USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPEMPMSK */ +#define USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT (_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPEMPMSK */ + +/* Bit fields for USB DIEP0CTL */ +#define _USB_DIEP0CTL_RESETVALUE 0x00008000UL /**< Default value for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_MASK 0xCFEE8003UL /**< Mask for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ +#define _USB_DIEP0CTL_MPS_MASK 0x3UL /**< Bit mask for USB_MPS */ +#define _USB_DIEP0CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_MPS_64B 0x00000000UL /**< Mode 64B for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_MPS_32B 0x00000001UL /**< Mode 32B for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_MPS_16B 0x00000002UL /**< Mode 16B for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_MPS_8B 0x00000003UL /**< Mode 8B for USB_DIEP0CTL */ +#define USB_DIEP0CTL_MPS_DEFAULT (_USB_DIEP0CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_MPS_64B (_USB_DIEP0CTL_MPS_64B << 0) /**< Shifted mode 64B for USB_DIEP0CTL */ +#define USB_DIEP0CTL_MPS_32B (_USB_DIEP0CTL_MPS_32B << 0) /**< Shifted mode 32B for USB_DIEP0CTL */ +#define USB_DIEP0CTL_MPS_16B (_USB_DIEP0CTL_MPS_16B << 0) /**< Shifted mode 16B for USB_DIEP0CTL */ +#define USB_DIEP0CTL_MPS_8B (_USB_DIEP0CTL_MPS_8B << 0) /**< Shifted mode 8B for USB_DIEP0CTL */ +#define USB_DIEP0CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ +#define _USB_DIEP0CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ +#define _USB_DIEP0CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ +#define _USB_DIEP0CTL_USBACTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_USBACTEP_DEFAULT (_USB_DIEP0CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ +#define _USB_DIEP0CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ +#define _USB_DIEP0CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ +#define _USB_DIEP0CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_NAKSTS_DEFAULT (_USB_DIEP0CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ +#define _USB_DIEP0CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ +#define _USB_DIEP0CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_EPTYPE_DEFAULT (_USB_DIEP0CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_STALL (0x1UL << 21) /**< Handshake */ +#define _USB_DIEP0CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ +#define _USB_DIEP0CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ +#define _USB_DIEP0CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_STALL_DEFAULT (_USB_DIEP0CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_TXFNUM_SHIFT 22 /**< Shift value for USB_TXFNUM */ +#define _USB_DIEP0CTL_TXFNUM_MASK 0x3C00000UL /**< Bit mask for USB_TXFNUM */ +#define _USB_DIEP0CTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_TXFNUM_DEFAULT (_USB_DIEP0CTL_TXFNUM_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_CNAK (0x1UL << 26) /**< Clear NAK */ +#define _USB_DIEP0CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ +#define _USB_DIEP0CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ +#define _USB_DIEP0CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_CNAK_DEFAULT (_USB_DIEP0CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_SNAK (0x1UL << 27) /**< Set NAK */ +#define _USB_DIEP0CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ +#define _USB_DIEP0CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ +#define _USB_DIEP0CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_SNAK_DEFAULT (_USB_DIEP0CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ +#define _USB_DIEP0CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ +#define _USB_DIEP0CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ +#define _USB_DIEP0CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_EPDIS_DEFAULT (_USB_DIEP0CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ +#define _USB_DIEP0CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ +#define _USB_DIEP0CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ +#define _USB_DIEP0CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_EPENA_DEFAULT (_USB_DIEP0CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ + +/* Bit fields for USB DIEP0INT */ +#define _USB_DIEP0INT_RESETVALUE 0x00000080UL /**< Default value for USB_DIEP0INT */ +#define _USB_DIEP0INT_MASK 0x000039FFUL /**< Mask for USB_DIEP0INT */ +#define USB_DIEP0INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ +#define _USB_DIEP0INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ +#define _USB_DIEP0INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ +#define _USB_DIEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_XFERCOMPL_DEFAULT (_USB_DIEP0INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ +#define _USB_DIEP0INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ +#define _USB_DIEP0INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ +#define _USB_DIEP0INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_EPDISBLD_DEFAULT (_USB_DIEP0INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_AHBERR (0x1UL << 2) /**< AHB Error */ +#define _USB_DIEP0INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ +#define _USB_DIEP0INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ +#define _USB_DIEP0INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_AHBERR_DEFAULT (_USB_DIEP0INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_TIMEOUT (0x1UL << 3) /**< Timeout Condition */ +#define _USB_DIEP0INT_TIMEOUT_SHIFT 3 /**< Shift value for USB_TIMEOUT */ +#define _USB_DIEP0INT_TIMEOUT_MASK 0x8UL /**< Bit mask for USB_TIMEOUT */ +#define _USB_DIEP0INT_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_TIMEOUT_DEFAULT (_USB_DIEP0INT_TIMEOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_INTKNTXFEMP (0x1UL << 4) /**< IN Token Received When TxFIFO is Empty */ +#define _USB_DIEP0INT_INTKNTXFEMP_SHIFT 4 /**< Shift value for USB_INTKNTXFEMP */ +#define _USB_DIEP0INT_INTKNTXFEMP_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMP */ +#define _USB_DIEP0INT_INTKNTXFEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_INTKNTXFEMP_DEFAULT (_USB_DIEP0INT_INTKNTXFEMP_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_INTKNEPMIS (0x1UL << 5) /**< IN Token Received with EP Mismatch */ +#define _USB_DIEP0INT_INTKNEPMIS_SHIFT 5 /**< Shift value for USB_INTKNEPMIS */ +#define _USB_DIEP0INT_INTKNEPMIS_MASK 0x20UL /**< Bit mask for USB_INTKNEPMIS */ +#define _USB_DIEP0INT_INTKNEPMIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_INTKNEPMIS_DEFAULT (_USB_DIEP0INT_INTKNEPMIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_INEPNAKEFF (0x1UL << 6) /**< IN Endpoint NAK Effective */ +#define _USB_DIEP0INT_INEPNAKEFF_SHIFT 6 /**< Shift value for USB_INEPNAKEFF */ +#define _USB_DIEP0INT_INEPNAKEFF_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFF */ +#define _USB_DIEP0INT_INEPNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_INEPNAKEFF_DEFAULT (_USB_DIEP0INT_INEPNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_TXFEMP (0x1UL << 7) /**< Transmit FIFO Empty */ +#define _USB_DIEP0INT_TXFEMP_SHIFT 7 /**< Shift value for USB_TXFEMP */ +#define _USB_DIEP0INT_TXFEMP_MASK 0x80UL /**< Bit mask for USB_TXFEMP */ +#define _USB_DIEP0INT_TXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_TXFEMP_DEFAULT (_USB_DIEP0INT_TXFEMP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_TXFIFOUNDRN (0x1UL << 8) /**< Fifo Underrun */ +#define _USB_DIEP0INT_TXFIFOUNDRN_SHIFT 8 /**< Shift value for USB_TXFIFOUNDRN */ +#define _USB_DIEP0INT_TXFIFOUNDRN_MASK 0x100UL /**< Bit mask for USB_TXFIFOUNDRN */ +#define _USB_DIEP0INT_TXFIFOUNDRN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_TXFIFOUNDRN_DEFAULT (_USB_DIEP0INT_TXFIFOUNDRN_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ +#define _USB_DIEP0INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ +#define _USB_DIEP0INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ +#define _USB_DIEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_PKTDRPSTS_DEFAULT (_USB_DIEP0INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_BBLEERR (0x1UL << 12) /**< Babble Interrupt */ +#define _USB_DIEP0INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ +#define _USB_DIEP0INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ +#define _USB_DIEP0INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_BBLEERR_DEFAULT (_USB_DIEP0INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ +#define _USB_DIEP0INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ +#define _USB_DIEP0INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ +#define _USB_DIEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_NAKINTRPT_DEFAULT (_USB_DIEP0INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEP0INT */ + +/* Bit fields for USB DIEP0TSIZ */ +#define _USB_DIEP0TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP0TSIZ */ +#define _USB_DIEP0TSIZ_MASK 0x0018007FUL /**< Mask for USB_DIEP0TSIZ */ +#define _USB_DIEP0TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ +#define _USB_DIEP0TSIZ_XFERSIZE_MASK 0x7FUL /**< Bit mask for USB_XFERSIZE */ +#define _USB_DIEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0TSIZ */ +#define USB_DIEP0TSIZ_XFERSIZE_DEFAULT (_USB_DIEP0TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0TSIZ */ +#define _USB_DIEP0TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ +#define _USB_DIEP0TSIZ_PKTCNT_MASK 0x180000UL /**< Bit mask for USB_PKTCNT */ +#define _USB_DIEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0TSIZ */ +#define USB_DIEP0TSIZ_PKTCNT_DEFAULT (_USB_DIEP0TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DIEP0TSIZ */ + +/* Bit fields for USB DIEP0DMAADDR */ +#define _USB_DIEP0DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP0DMAADDR */ +#define _USB_DIEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DIEP0DMAADDR */ +#define _USB_DIEP0DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ +#define _USB_DIEP0DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ +#define _USB_DIEP0DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0DMAADDR */ +#define USB_DIEP0DMAADDR_DMAADDR_DEFAULT (_USB_DIEP0DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0DMAADDR */ + +/* Bit fields for USB DIEP0TXFSTS */ +#define _USB_DIEP0TXFSTS_RESETVALUE 0x00000200UL /**< Default value for USB_DIEP0TXFSTS */ +#define _USB_DIEP0TXFSTS_MASK 0x0000FFFFUL /**< Mask for USB_DIEP0TXFSTS */ +#define _USB_DIEP0TXFSTS_SPCAVAIL_SHIFT 0 /**< Shift value for USB_SPCAVAIL */ +#define _USB_DIEP0TXFSTS_SPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_SPCAVAIL */ +#define _USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEP0TXFSTS */ +#define USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0TXFSTS */ + +/* Bit fields for USB DIEP_CTL */ +#define _USB_DIEP_CTL_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_MASK 0xFFEF87FFUL /**< Mask for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ +#define _USB_DIEP_CTL_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */ +#define _USB_DIEP_CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_MPS_DEFAULT (_USB_DIEP_CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ +#define _USB_DIEP_CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ +#define _USB_DIEP_CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ +#define _USB_DIEP_CTL_USBACTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_USBACTEP_DEFAULT (_USB_DIEP_CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_DPIDEOF (0x1UL << 16) /**< Endpoint Data PID / Even or Odd Frame */ +#define _USB_DIEP_CTL_DPIDEOF_SHIFT 16 /**< Shift value for USB_DPIDEOF */ +#define _USB_DIEP_CTL_DPIDEOF_MASK 0x10000UL /**< Bit mask for USB_DPIDEOF */ +#define _USB_DIEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /**< Mode DATA0EVEN for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /**< Mode DATA1ODD for USB_DIEP_CTL */ +#define USB_DIEP_CTL_DPIDEOF_DEFAULT (_USB_DIEP_CTL_DPIDEOF_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_DPIDEOF_DATA0EVEN (_USB_DIEP_CTL_DPIDEOF_DATA0EVEN << 16) /**< Shifted mode DATA0EVEN for USB_DIEP_CTL */ +#define USB_DIEP_CTL_DPIDEOF_DATA1ODD (_USB_DIEP_CTL_DPIDEOF_DATA1ODD << 16) /**< Shifted mode DATA1ODD for USB_DIEP_CTL */ +#define USB_DIEP_CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ +#define _USB_DIEP_CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ +#define _USB_DIEP_CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ +#define _USB_DIEP_CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_NAKSTS_DEFAULT (_USB_DIEP_CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ +#define _USB_DIEP_CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ +#define _USB_DIEP_CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPTYPE_DEFAULT (_USB_DIEP_CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPTYPE_CONTROL (_USB_DIEP_CTL_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPTYPE_ISO (_USB_DIEP_CTL_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPTYPE_BULK (_USB_DIEP_CTL_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPTYPE_INT (_USB_DIEP_CTL_EPTYPE_INT << 18) /**< Shifted mode INT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_STALL (0x1UL << 21) /**< Handshake */ +#define _USB_DIEP_CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ +#define _USB_DIEP_CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ +#define _USB_DIEP_CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_STALL_DEFAULT (_USB_DIEP_CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_TXFNUM_SHIFT 22 /**< Shift value for USB_TXFNUM */ +#define _USB_DIEP_CTL_TXFNUM_MASK 0x3C00000UL /**< Bit mask for USB_TXFNUM */ +#define _USB_DIEP_CTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_TXFNUM_DEFAULT (_USB_DIEP_CTL_TXFNUM_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_CNAK (0x1UL << 26) /**< Clear NAK */ +#define _USB_DIEP_CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ +#define _USB_DIEP_CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ +#define _USB_DIEP_CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_CNAK_DEFAULT (_USB_DIEP_CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SNAK (0x1UL << 27) /**< Set NAK */ +#define _USB_DIEP_CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ +#define _USB_DIEP_CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ +#define _USB_DIEP_CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SNAK_DEFAULT (_USB_DIEP_CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SETD0PIDEF (0x1UL << 28) /**< Set DATA0 PID / Even Frame */ +#define _USB_DIEP_CTL_SETD0PIDEF_SHIFT 28 /**< Shift value for USB_SETD0PIDEF */ +#define _USB_DIEP_CTL_SETD0PIDEF_MASK 0x10000000UL /**< Bit mask for USB_SETD0PIDEF */ +#define _USB_DIEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SETD0PIDEF_DEFAULT (_USB_DIEP_CTL_SETD0PIDEF_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SETD1PIDOF (0x1UL << 29) /**< Set DATA1 PID / Odd Frame */ +#define _USB_DIEP_CTL_SETD1PIDOF_SHIFT 29 /**< Shift value for USB_SETD1PIDOF */ +#define _USB_DIEP_CTL_SETD1PIDOF_MASK 0x20000000UL /**< Bit mask for USB_SETD1PIDOF */ +#define _USB_DIEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SETD1PIDOF_DEFAULT (_USB_DIEP_CTL_SETD1PIDOF_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ +#define _USB_DIEP_CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ +#define _USB_DIEP_CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ +#define _USB_DIEP_CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPDIS_DEFAULT (_USB_DIEP_CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ +#define _USB_DIEP_CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ +#define _USB_DIEP_CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ +#define _USB_DIEP_CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPENA_DEFAULT (_USB_DIEP_CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ + +/* Bit fields for USB DIEP_INT */ +#define _USB_DIEP_INT_RESETVALUE 0x00000080UL /**< Default value for USB_DIEP_INT */ +#define _USB_DIEP_INT_MASK 0x000039FFUL /**< Mask for USB_DIEP_INT */ +#define USB_DIEP_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ +#define _USB_DIEP_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ +#define _USB_DIEP_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ +#define _USB_DIEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_XFERCOMPL_DEFAULT (_USB_DIEP_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ +#define _USB_DIEP_INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ +#define _USB_DIEP_INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ +#define _USB_DIEP_INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_EPDISBLD_DEFAULT (_USB_DIEP_INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_AHBERR (0x1UL << 2) /**< AHB Error */ +#define _USB_DIEP_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ +#define _USB_DIEP_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ +#define _USB_DIEP_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_AHBERR_DEFAULT (_USB_DIEP_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_TIMEOUT (0x1UL << 3) /**< Timeout Condition */ +#define _USB_DIEP_INT_TIMEOUT_SHIFT 3 /**< Shift value for USB_TIMEOUT */ +#define _USB_DIEP_INT_TIMEOUT_MASK 0x8UL /**< Bit mask for USB_TIMEOUT */ +#define _USB_DIEP_INT_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_TIMEOUT_DEFAULT (_USB_DIEP_INT_TIMEOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_INTKNTXFEMP (0x1UL << 4) /**< IN Token Received When TxFIFO is Empty */ +#define _USB_DIEP_INT_INTKNTXFEMP_SHIFT 4 /**< Shift value for USB_INTKNTXFEMP */ +#define _USB_DIEP_INT_INTKNTXFEMP_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMP */ +#define _USB_DIEP_INT_INTKNTXFEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_INTKNTXFEMP_DEFAULT (_USB_DIEP_INT_INTKNTXFEMP_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_INTKNEPMIS (0x1UL << 5) /**< IN Token Received with EP Mismatch */ +#define _USB_DIEP_INT_INTKNEPMIS_SHIFT 5 /**< Shift value for USB_INTKNEPMIS */ +#define _USB_DIEP_INT_INTKNEPMIS_MASK 0x20UL /**< Bit mask for USB_INTKNEPMIS */ +#define _USB_DIEP_INT_INTKNEPMIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_INTKNEPMIS_DEFAULT (_USB_DIEP_INT_INTKNEPMIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_INEPNAKEFF (0x1UL << 6) /**< IN Endpoint NAK Effective */ +#define _USB_DIEP_INT_INEPNAKEFF_SHIFT 6 /**< Shift value for USB_INEPNAKEFF */ +#define _USB_DIEP_INT_INEPNAKEFF_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFF */ +#define _USB_DIEP_INT_INEPNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_INEPNAKEFF_DEFAULT (_USB_DIEP_INT_INEPNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_TXFEMP (0x1UL << 7) /**< Transmit FIFO Empty */ +#define _USB_DIEP_INT_TXFEMP_SHIFT 7 /**< Shift value for USB_TXFEMP */ +#define _USB_DIEP_INT_TXFEMP_MASK 0x80UL /**< Bit mask for USB_TXFEMP */ +#define _USB_DIEP_INT_TXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_TXFEMP_DEFAULT (_USB_DIEP_INT_TXFEMP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_TXFIFOUNDRN (0x1UL << 8) /**< Fifo Underrun */ +#define _USB_DIEP_INT_TXFIFOUNDRN_SHIFT 8 /**< Shift value for USB_TXFIFOUNDRN */ +#define _USB_DIEP_INT_TXFIFOUNDRN_MASK 0x100UL /**< Bit mask for USB_TXFIFOUNDRN */ +#define _USB_DIEP_INT_TXFIFOUNDRN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_TXFIFOUNDRN_DEFAULT (_USB_DIEP_INT_TXFIFOUNDRN_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ +#define _USB_DIEP_INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ +#define _USB_DIEP_INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ +#define _USB_DIEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_PKTDRPSTS_DEFAULT (_USB_DIEP_INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_BBLEERR (0x1UL << 12) /**< Babble Interrupt */ +#define _USB_DIEP_INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ +#define _USB_DIEP_INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ +#define _USB_DIEP_INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_BBLEERR_DEFAULT (_USB_DIEP_INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ +#define _USB_DIEP_INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ +#define _USB_DIEP_INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ +#define _USB_DIEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_NAKINTRPT_DEFAULT (_USB_DIEP_INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEP_INT */ + +/* Bit fields for USB DIEP_TSIZ */ +#define _USB_DIEP_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_TSIZ */ +#define _USB_DIEP_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_DIEP_TSIZ */ +#define _USB_DIEP_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ +#define _USB_DIEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */ +#define _USB_DIEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */ +#define USB_DIEP_TSIZ_XFERSIZE_DEFAULT (_USB_DIEP_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */ +#define _USB_DIEP_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ +#define _USB_DIEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */ +#define _USB_DIEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */ +#define USB_DIEP_TSIZ_PKTCNT_DEFAULT (_USB_DIEP_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */ +#define _USB_DIEP_TSIZ_MC_SHIFT 29 /**< Shift value for USB_MC */ +#define _USB_DIEP_TSIZ_MC_MASK 0x60000000UL /**< Bit mask for USB_MC */ +#define _USB_DIEP_TSIZ_MC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */ +#define USB_DIEP_TSIZ_MC_DEFAULT (_USB_DIEP_TSIZ_MC_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */ + +/* Bit fields for USB DIEP_DMAADDR */ +#define _USB_DIEP_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_DMAADDR */ +#define _USB_DIEP_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DIEP_DMAADDR */ +#define _USB_DIEP_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ +#define _USB_DIEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ +#define _USB_DIEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_DMAADDR */ +#define USB_DIEP_DMAADDR_DMAADDR_DEFAULT (_USB_DIEP_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_DMAADDR */ + +/* Bit fields for USB DIEP_DTXFSTS */ +#define _USB_DIEP_DTXFSTS_RESETVALUE 0x00000200UL /**< Default value for USB_DIEP_DTXFSTS */ +#define _USB_DIEP_DTXFSTS_MASK 0x0000FFFFUL /**< Mask for USB_DIEP_DTXFSTS */ +#define _USB_DIEP_DTXFSTS_SPCAVAIL_SHIFT 0 /**< Shift value for USB_SPCAVAIL */ +#define _USB_DIEP_DTXFSTS_SPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_SPCAVAIL */ +#define _USB_DIEP_DTXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEP_DTXFSTS */ +#define USB_DIEP_DTXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP_DTXFSTS_SPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_DTXFSTS */ + +/* Bit fields for USB DOEP0CTL */ +#define _USB_DOEP0CTL_RESETVALUE 0x00008000UL /**< Default value for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_MASK 0xCC3E8003UL /**< Mask for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ +#define _USB_DOEP0CTL_MPS_MASK 0x3UL /**< Bit mask for USB_MPS */ +#define _USB_DOEP0CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_MPS_64B 0x00000000UL /**< Mode 64B for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_MPS_32B 0x00000001UL /**< Mode 32B for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_MPS_16B 0x00000002UL /**< Mode 16B for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_MPS_8B 0x00000003UL /**< Mode 8B for USB_DOEP0CTL */ +#define USB_DOEP0CTL_MPS_DEFAULT (_USB_DOEP0CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_MPS_64B (_USB_DOEP0CTL_MPS_64B << 0) /**< Shifted mode 64B for USB_DOEP0CTL */ +#define USB_DOEP0CTL_MPS_32B (_USB_DOEP0CTL_MPS_32B << 0) /**< Shifted mode 32B for USB_DOEP0CTL */ +#define USB_DOEP0CTL_MPS_16B (_USB_DOEP0CTL_MPS_16B << 0) /**< Shifted mode 16B for USB_DOEP0CTL */ +#define USB_DOEP0CTL_MPS_8B (_USB_DOEP0CTL_MPS_8B << 0) /**< Shifted mode 8B for USB_DOEP0CTL */ +#define USB_DOEP0CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ +#define _USB_DOEP0CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ +#define _USB_DOEP0CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ +#define _USB_DOEP0CTL_USBACTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_USBACTEP_DEFAULT (_USB_DOEP0CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ +#define _USB_DOEP0CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ +#define _USB_DOEP0CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ +#define _USB_DOEP0CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_NAKSTS_DEFAULT (_USB_DOEP0CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ +#define _USB_DOEP0CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ +#define _USB_DOEP0CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_EPTYPE_DEFAULT (_USB_DOEP0CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_SNP (0x1UL << 20) /**< Snoop Mode */ +#define _USB_DOEP0CTL_SNP_SHIFT 20 /**< Shift value for USB_SNP */ +#define _USB_DOEP0CTL_SNP_MASK 0x100000UL /**< Bit mask for USB_SNP */ +#define _USB_DOEP0CTL_SNP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_SNP_DEFAULT (_USB_DOEP0CTL_SNP_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_STALL (0x1UL << 21) /**< Handshake */ +#define _USB_DOEP0CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ +#define _USB_DOEP0CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ +#define _USB_DOEP0CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_STALL_DEFAULT (_USB_DOEP0CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_CNAK (0x1UL << 26) /**< Clear NAK */ +#define _USB_DOEP0CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ +#define _USB_DOEP0CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ +#define _USB_DOEP0CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_CNAK_DEFAULT (_USB_DOEP0CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_SNAK (0x1UL << 27) /**< Set NAK */ +#define _USB_DOEP0CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ +#define _USB_DOEP0CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ +#define _USB_DOEP0CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_SNAK_DEFAULT (_USB_DOEP0CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ +#define _USB_DOEP0CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ +#define _USB_DOEP0CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ +#define _USB_DOEP0CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_EPDIS_DEFAULT (_USB_DOEP0CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ +#define _USB_DOEP0CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ +#define _USB_DOEP0CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ +#define _USB_DOEP0CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_EPENA_DEFAULT (_USB_DOEP0CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ + +/* Bit fields for USB DOEP0INT */ +#define _USB_DOEP0INT_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0INT */ +#define _USB_DOEP0INT_MASK 0x0000B97FUL /**< Mask for USB_DOEP0INT */ +#define USB_DOEP0INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ +#define _USB_DOEP0INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ +#define _USB_DOEP0INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ +#define _USB_DOEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_XFERCOMPL_DEFAULT (_USB_DOEP0INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ +#define _USB_DOEP0INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ +#define _USB_DOEP0INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ +#define _USB_DOEP0INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_EPDISBLD_DEFAULT (_USB_DOEP0INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_AHBERR (0x1UL << 2) /**< AHB Error */ +#define _USB_DOEP0INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ +#define _USB_DOEP0INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ +#define _USB_DOEP0INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_AHBERR_DEFAULT (_USB_DOEP0INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_SETUP (0x1UL << 3) /**< Setup Phase Done */ +#define _USB_DOEP0INT_SETUP_SHIFT 3 /**< Shift value for USB_SETUP */ +#define _USB_DOEP0INT_SETUP_MASK 0x8UL /**< Bit mask for USB_SETUP */ +#define _USB_DOEP0INT_SETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_SETUP_DEFAULT (_USB_DOEP0INT_SETUP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_OUTTKNEPDIS (0x1UL << 4) /**< OUT Token Received When Endpoint Disabled */ +#define _USB_DOEP0INT_OUTTKNEPDIS_SHIFT 4 /**< Shift value for USB_OUTTKNEPDIS */ +#define _USB_DOEP0INT_OUTTKNEPDIS_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDIS */ +#define _USB_DOEP0INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP0INT_OUTTKNEPDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_STSPHSERCVD (0x1UL << 5) /**< Status Phase Received For Control Write */ +#define _USB_DOEP0INT_STSPHSERCVD_SHIFT 5 /**< Shift value for USB_STSPHSERCVD */ +#define _USB_DOEP0INT_STSPHSERCVD_MASK 0x20UL /**< Bit mask for USB_STSPHSERCVD */ +#define _USB_DOEP0INT_STSPHSERCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_STSPHSERCVD_DEFAULT (_USB_DOEP0INT_STSPHSERCVD_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received */ +#define _USB_DOEP0INT_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */ +#define _USB_DOEP0INT_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */ +#define _USB_DOEP0INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP0INT_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_OUTPKTERR (0x1UL << 8) /**< OUT Packet Error */ +#define _USB_DOEP0INT_OUTPKTERR_SHIFT 8 /**< Shift value for USB_OUTPKTERR */ +#define _USB_DOEP0INT_OUTPKTERR_MASK 0x100UL /**< Bit mask for USB_OUTPKTERR */ +#define _USB_DOEP0INT_OUTPKTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_OUTPKTERR_DEFAULT (_USB_DOEP0INT_OUTPKTERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ +#define _USB_DOEP0INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ +#define _USB_DOEP0INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ +#define _USB_DOEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_PKTDRPSTS_DEFAULT (_USB_DOEP0INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_BBLEERR (0x1UL << 12) /**< NAK Interrupt */ +#define _USB_DOEP0INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ +#define _USB_DOEP0INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ +#define _USB_DOEP0INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_BBLEERR_DEFAULT (_USB_DOEP0INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ +#define _USB_DOEP0INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ +#define _USB_DOEP0INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ +#define _USB_DOEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_NAKINTRPT_DEFAULT (_USB_DOEP0INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_STUPPKTRCVD (0x1UL << 15) /**< */ +#define _USB_DOEP0INT_STUPPKTRCVD_SHIFT 15 /**< Shift value for USB_STUPPKTRCVD */ +#define _USB_DOEP0INT_STUPPKTRCVD_MASK 0x8000UL /**< Bit mask for USB_STUPPKTRCVD */ +#define _USB_DOEP0INT_STUPPKTRCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_STUPPKTRCVD_DEFAULT (_USB_DOEP0INT_STUPPKTRCVD_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP0INT */ + +/* Bit fields for USB DOEP0TSIZ */ +#define _USB_DOEP0TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0TSIZ */ +#define _USB_DOEP0TSIZ_MASK 0x6008007FUL /**< Mask for USB_DOEP0TSIZ */ +#define _USB_DOEP0TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ +#define _USB_DOEP0TSIZ_XFERSIZE_MASK 0x7FUL /**< Bit mask for USB_XFERSIZE */ +#define _USB_DOEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */ +#define USB_DOEP0TSIZ_XFERSIZE_DEFAULT (_USB_DOEP0TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */ +#define USB_DOEP0TSIZ_PKTCNT (0x1UL << 19) /**< Packet Count */ +#define _USB_DOEP0TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ +#define _USB_DOEP0TSIZ_PKTCNT_MASK 0x80000UL /**< Bit mask for USB_PKTCNT */ +#define _USB_DOEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */ +#define USB_DOEP0TSIZ_PKTCNT_DEFAULT (_USB_DOEP0TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */ +#define _USB_DOEP0TSIZ_SUPCNT_SHIFT 29 /**< Shift value for USB_SUPCNT */ +#define _USB_DOEP0TSIZ_SUPCNT_MASK 0x60000000UL /**< Bit mask for USB_SUPCNT */ +#define _USB_DOEP0TSIZ_SUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */ +#define USB_DOEP0TSIZ_SUPCNT_DEFAULT (_USB_DOEP0TSIZ_SUPCNT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */ + +/* Bit fields for USB DOEP0DMAADDR */ +#define _USB_DOEP0DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0DMAADDR */ +#define _USB_DOEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DOEP0DMAADDR */ +#define _USB_DOEP0DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ +#define _USB_DOEP0DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ +#define _USB_DOEP0DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0DMAADDR */ +#define USB_DOEP0DMAADDR_DMAADDR_DEFAULT (_USB_DOEP0DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0DMAADDR */ + +/* Bit fields for USB DOEP_CTL */ +#define _USB_DOEP_CTL_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_MASK 0xFC3F87FFUL /**< Mask for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ +#define _USB_DOEP_CTL_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */ +#define _USB_DOEP_CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_MPS_DEFAULT (_USB_DOEP_CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ +#define _USB_DOEP_CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ +#define _USB_DOEP_CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ +#define _USB_DOEP_CTL_USBACTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_USBACTEP_DEFAULT (_USB_DOEP_CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_DPIDEOF (0x1UL << 16) /**< Endpoint Data PID / Even-odd Frame */ +#define _USB_DOEP_CTL_DPIDEOF_SHIFT 16 /**< Shift value for USB_DPIDEOF */ +#define _USB_DOEP_CTL_DPIDEOF_MASK 0x10000UL /**< Bit mask for USB_DPIDEOF */ +#define _USB_DOEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /**< Mode DATA0EVEN for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /**< Mode DATA1ODD for USB_DOEP_CTL */ +#define USB_DOEP_CTL_DPIDEOF_DEFAULT (_USB_DOEP_CTL_DPIDEOF_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_DPIDEOF_DATA0EVEN (_USB_DOEP_CTL_DPIDEOF_DATA0EVEN << 16) /**< Shifted mode DATA0EVEN for USB_DOEP_CTL */ +#define USB_DOEP_CTL_DPIDEOF_DATA1ODD (_USB_DOEP_CTL_DPIDEOF_DATA1ODD << 16) /**< Shifted mode DATA1ODD for USB_DOEP_CTL */ +#define USB_DOEP_CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ +#define _USB_DOEP_CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ +#define _USB_DOEP_CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ +#define _USB_DOEP_CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_NAKSTS_DEFAULT (_USB_DOEP_CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ +#define _USB_DOEP_CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ +#define _USB_DOEP_CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPTYPE_DEFAULT (_USB_DOEP_CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPTYPE_CONTROL (_USB_DOEP_CTL_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPTYPE_ISO (_USB_DOEP_CTL_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPTYPE_BULK (_USB_DOEP_CTL_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPTYPE_INT (_USB_DOEP_CTL_EPTYPE_INT << 18) /**< Shifted mode INT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SNP (0x1UL << 20) /**< Snoop Mode */ +#define _USB_DOEP_CTL_SNP_SHIFT 20 /**< Shift value for USB_SNP */ +#define _USB_DOEP_CTL_SNP_MASK 0x100000UL /**< Bit mask for USB_SNP */ +#define _USB_DOEP_CTL_SNP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SNP_DEFAULT (_USB_DOEP_CTL_SNP_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_STALL (0x1UL << 21) /**< STALL Handshake */ +#define _USB_DOEP_CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ +#define _USB_DOEP_CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ +#define _USB_DOEP_CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_STALL_DEFAULT (_USB_DOEP_CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_CNAK (0x1UL << 26) /**< Clear NAK */ +#define _USB_DOEP_CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ +#define _USB_DOEP_CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ +#define _USB_DOEP_CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_CNAK_DEFAULT (_USB_DOEP_CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SNAK (0x1UL << 27) /**< Set NAK */ +#define _USB_DOEP_CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ +#define _USB_DOEP_CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ +#define _USB_DOEP_CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SNAK_DEFAULT (_USB_DOEP_CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SETD0PIDEF (0x1UL << 28) /**< Set DATA0 PID / Even Frame */ +#define _USB_DOEP_CTL_SETD0PIDEF_SHIFT 28 /**< Shift value for USB_SETD0PIDEF */ +#define _USB_DOEP_CTL_SETD0PIDEF_MASK 0x10000000UL /**< Bit mask for USB_SETD0PIDEF */ +#define _USB_DOEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SETD0PIDEF_DEFAULT (_USB_DOEP_CTL_SETD0PIDEF_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SETD1PIDOF (0x1UL << 29) /**< Set DATA1 PID / Odd Frame */ +#define _USB_DOEP_CTL_SETD1PIDOF_SHIFT 29 /**< Shift value for USB_SETD1PIDOF */ +#define _USB_DOEP_CTL_SETD1PIDOF_MASK 0x20000000UL /**< Bit mask for USB_SETD1PIDOF */ +#define _USB_DOEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SETD1PIDOF_DEFAULT (_USB_DOEP_CTL_SETD1PIDOF_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ +#define _USB_DOEP_CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ +#define _USB_DOEP_CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ +#define _USB_DOEP_CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPDIS_DEFAULT (_USB_DOEP_CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ +#define _USB_DOEP_CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ +#define _USB_DOEP_CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ +#define _USB_DOEP_CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPENA_DEFAULT (_USB_DOEP_CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ + +/* Bit fields for USB DOEP_INT */ +#define _USB_DOEP_INT_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_INT */ +#define _USB_DOEP_INT_MASK 0x0000B97FUL /**< Mask for USB_DOEP_INT */ +#define USB_DOEP_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ +#define _USB_DOEP_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ +#define _USB_DOEP_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ +#define _USB_DOEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_XFERCOMPL_DEFAULT (_USB_DOEP_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ +#define _USB_DOEP_INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ +#define _USB_DOEP_INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ +#define _USB_DOEP_INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_EPDISBLD_DEFAULT (_USB_DOEP_INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_AHBERR (0x1UL << 2) /**< AHB Error */ +#define _USB_DOEP_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ +#define _USB_DOEP_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ +#define _USB_DOEP_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_AHBERR_DEFAULT (_USB_DOEP_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_SETUP (0x1UL << 3) /**< Setup Phase Done */ +#define _USB_DOEP_INT_SETUP_SHIFT 3 /**< Shift value for USB_SETUP */ +#define _USB_DOEP_INT_SETUP_MASK 0x8UL /**< Bit mask for USB_SETUP */ +#define _USB_DOEP_INT_SETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_SETUP_DEFAULT (_USB_DOEP_INT_SETUP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_OUTTKNEPDIS (0x1UL << 4) /**< OUT Token Received When Endpoint Disabled */ +#define _USB_DOEP_INT_OUTTKNEPDIS_SHIFT 4 /**< Shift value for USB_OUTTKNEPDIS */ +#define _USB_DOEP_INT_OUTTKNEPDIS_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDIS */ +#define _USB_DOEP_INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP_INT_OUTTKNEPDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_STSPHSERCVD (0x1UL << 5) /**< Status Phase Received For Control Write */ +#define _USB_DOEP_INT_STSPHSERCVD_SHIFT 5 /**< Shift value for USB_STSPHSERCVD */ +#define _USB_DOEP_INT_STSPHSERCVD_MASK 0x20UL /**< Bit mask for USB_STSPHSERCVD */ +#define _USB_DOEP_INT_STSPHSERCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_STSPHSERCVD_DEFAULT (_USB_DOEP_INT_STSPHSERCVD_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received */ +#define _USB_DOEP_INT_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */ +#define _USB_DOEP_INT_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */ +#define _USB_DOEP_INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP_INT_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_OUTPKTERR (0x1UL << 8) /**< OUT Packet Error */ +#define _USB_DOEP_INT_OUTPKTERR_SHIFT 8 /**< Shift value for USB_OUTPKTERR */ +#define _USB_DOEP_INT_OUTPKTERR_MASK 0x100UL /**< Bit mask for USB_OUTPKTERR */ +#define _USB_DOEP_INT_OUTPKTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_OUTPKTERR_DEFAULT (_USB_DOEP_INT_OUTPKTERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ +#define _USB_DOEP_INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ +#define _USB_DOEP_INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ +#define _USB_DOEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_PKTDRPSTS_DEFAULT (_USB_DOEP_INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_BBLEERR (0x1UL << 12) /**< Babble Error */ +#define _USB_DOEP_INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ +#define _USB_DOEP_INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ +#define _USB_DOEP_INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_BBLEERR_DEFAULT (_USB_DOEP_INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ +#define _USB_DOEP_INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ +#define _USB_DOEP_INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ +#define _USB_DOEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_NAKINTRPT_DEFAULT (_USB_DOEP_INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_STUPPKTRCVD (0x1UL << 15) /**< */ +#define _USB_DOEP_INT_STUPPKTRCVD_SHIFT 15 /**< Shift value for USB_STUPPKTRCVD */ +#define _USB_DOEP_INT_STUPPKTRCVD_MASK 0x8000UL /**< Bit mask for USB_STUPPKTRCVD */ +#define _USB_DOEP_INT_STUPPKTRCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_STUPPKTRCVD_DEFAULT (_USB_DOEP_INT_STUPPKTRCVD_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP_INT */ + +/* Bit fields for USB DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ +#define _USB_DOEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */ +#define _USB_DOEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_XFERSIZE_DEFAULT (_USB_DOEP_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ +#define _USB_DOEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */ +#define _USB_DOEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_PKTCNT_DEFAULT (_USB_DOEP_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_SHIFT 29 /**< Shift value for USB_RXDPIDSUPCNT */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MASK 0x60000000UL /**< Bit mask for USB_RXDPIDSUPCNT */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 0x00000000UL /**< Mode DATA0 for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 0x00000001UL /**< Mode DATA2 for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 0x00000002UL /**< Mode DATA1 for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA 0x00000003UL /**< Mode MDATA for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 << 29) /**< Shifted mode DATA0 for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 << 29) /**< Shifted mode DATA2 for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 << 29) /**< Shifted mode DATA1 for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA (_USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA << 29) /**< Shifted mode MDATA for USB_DOEP_TSIZ */ + +/* Bit fields for USB DOEP_DMAADDR */ +#define _USB_DOEP_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_DMAADDR */ +#define _USB_DOEP_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DOEP_DMAADDR */ +#define _USB_DOEP_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ +#define _USB_DOEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ +#define _USB_DOEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_DMAADDR */ +#define USB_DOEP_DMAADDR_DMAADDR_DEFAULT (_USB_DOEP_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_DMAADDR */ + +/* Bit fields for USB PCGCCTL */ +#define _USB_PCGCCTL_RESETVALUE 0x00000000UL /**< Default value for USB_PCGCCTL */ +#define _USB_PCGCCTL_MASK 0x0000014FUL /**< Mask for USB_PCGCCTL */ +#define USB_PCGCCTL_STOPPCLK (0x1UL << 0) /**< Stop PHY clock */ +#define _USB_PCGCCTL_STOPPCLK_SHIFT 0 /**< Shift value for USB_STOPPCLK */ +#define _USB_PCGCCTL_STOPPCLK_MASK 0x1UL /**< Bit mask for USB_STOPPCLK */ +#define _USB_PCGCCTL_STOPPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_STOPPCLK_DEFAULT (_USB_PCGCCTL_STOPPCLK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_GATEHCLK (0x1UL << 1) /**< Gate HCLK */ +#define _USB_PCGCCTL_GATEHCLK_SHIFT 1 /**< Shift value for USB_GATEHCLK */ +#define _USB_PCGCCTL_GATEHCLK_MASK 0x2UL /**< Bit mask for USB_GATEHCLK */ +#define _USB_PCGCCTL_GATEHCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_GATEHCLK_DEFAULT (_USB_PCGCCTL_GATEHCLK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_PWRCLMP (0x1UL << 2) /**< Power Clamp */ +#define _USB_PCGCCTL_PWRCLMP_SHIFT 2 /**< Shift value for USB_PWRCLMP */ +#define _USB_PCGCCTL_PWRCLMP_MASK 0x4UL /**< Bit mask for USB_PWRCLMP */ +#define _USB_PCGCCTL_PWRCLMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_PWRCLMP_DEFAULT (_USB_PCGCCTL_PWRCLMP_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_RSTPDWNMODULE (0x1UL << 3) /**< Reset Power-Down Modules */ +#define _USB_PCGCCTL_RSTPDWNMODULE_SHIFT 3 /**< Shift value for USB_RSTPDWNMODULE */ +#define _USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8UL /**< Bit mask for USB_RSTPDWNMODULE */ +#define _USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_RSTPDWNMODULE_DEFAULT (_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_PHYSLEEP (0x1UL << 6) /**< PHY In Sleep */ +#define _USB_PCGCCTL_PHYSLEEP_SHIFT 6 /**< Shift value for USB_PHYSLEEP */ +#define _USB_PCGCCTL_PHYSLEEP_MASK 0x40UL /**< Bit mask for USB_PHYSLEEP */ +#define _USB_PCGCCTL_PHYSLEEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_PHYSLEEP_DEFAULT (_USB_PCGCCTL_PHYSLEEP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_RESETAFTERSUSP (0x1UL << 8) /**< Reset after suspend */ +#define _USB_PCGCCTL_RESETAFTERSUSP_SHIFT 8 /**< Shift value for USB_RESETAFTERSUSP */ +#define _USB_PCGCCTL_RESETAFTERSUSP_MASK 0x100UL /**< Bit mask for USB_RESETAFTERSUSP */ +#define _USB_PCGCCTL_RESETAFTERSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_RESETAFTERSUSP_DEFAULT (_USB_PCGCCTL_RESETAFTERSUSP_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_PCGCCTL */ + +/* Bit fields for USB FIFO0D */ +#define _USB_FIFO0D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO0D */ +#define _USB_FIFO0D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO0D */ +#define _USB_FIFO0D_FIFO0D_SHIFT 0 /**< Shift value for USB_FIFO0D */ +#define _USB_FIFO0D_FIFO0D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO0D */ +#define _USB_FIFO0D_FIFO0D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO0D */ +#define USB_FIFO0D_FIFO0D_DEFAULT (_USB_FIFO0D_FIFO0D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO0D */ + +/* Bit fields for USB FIFO1D */ +#define _USB_FIFO1D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO1D */ +#define _USB_FIFO1D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO1D */ +#define _USB_FIFO1D_FIFO1D_SHIFT 0 /**< Shift value for USB_FIFO1D */ +#define _USB_FIFO1D_FIFO1D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO1D */ +#define _USB_FIFO1D_FIFO1D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO1D */ +#define USB_FIFO1D_FIFO1D_DEFAULT (_USB_FIFO1D_FIFO1D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO1D */ + +/* Bit fields for USB FIFO2D */ +#define _USB_FIFO2D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO2D */ +#define _USB_FIFO2D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO2D */ +#define _USB_FIFO2D_FIFO2D_SHIFT 0 /**< Shift value for USB_FIFO2D */ +#define _USB_FIFO2D_FIFO2D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO2D */ +#define _USB_FIFO2D_FIFO2D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO2D */ +#define USB_FIFO2D_FIFO2D_DEFAULT (_USB_FIFO2D_FIFO2D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO2D */ + +/* Bit fields for USB FIFO3D */ +#define _USB_FIFO3D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO3D */ +#define _USB_FIFO3D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO3D */ +#define _USB_FIFO3D_FIFO3D_SHIFT 0 /**< Shift value for USB_FIFO3D */ +#define _USB_FIFO3D_FIFO3D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO3D */ +#define _USB_FIFO3D_FIFO3D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO3D */ +#define USB_FIFO3D_FIFO3D_DEFAULT (_USB_FIFO3D_FIFO3D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO3D */ + +/* Bit fields for USB FIFO4D */ +#define _USB_FIFO4D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO4D */ +#define _USB_FIFO4D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO4D */ +#define _USB_FIFO4D_FIFO4D_SHIFT 0 /**< Shift value for USB_FIFO4D */ +#define _USB_FIFO4D_FIFO4D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO4D */ +#define _USB_FIFO4D_FIFO4D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO4D */ +#define USB_FIFO4D_FIFO4D_DEFAULT (_USB_FIFO4D_FIFO4D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO4D */ + +/* Bit fields for USB FIFO5D */ +#define _USB_FIFO5D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO5D */ +#define _USB_FIFO5D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO5D */ +#define _USB_FIFO5D_FIFO5D_SHIFT 0 /**< Shift value for USB_FIFO5D */ +#define _USB_FIFO5D_FIFO5D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO5D */ +#define _USB_FIFO5D_FIFO5D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO5D */ +#define USB_FIFO5D_FIFO5D_DEFAULT (_USB_FIFO5D_FIFO5D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO5D */ + +/* Bit fields for USB FIFO6D */ +#define _USB_FIFO6D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO6D */ +#define _USB_FIFO6D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO6D */ +#define _USB_FIFO6D_FIFO6D_SHIFT 0 /**< Shift value for USB_FIFO6D */ +#define _USB_FIFO6D_FIFO6D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO6D */ +#define _USB_FIFO6D_FIFO6D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO6D */ +#define USB_FIFO6D_FIFO6D_DEFAULT (_USB_FIFO6D_FIFO6D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO6D */ + +/* Bit fields for USB FIFO7D */ +#define _USB_FIFO7D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO7D */ +#define _USB_FIFO7D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO7D */ +#define _USB_FIFO7D_FIFO7D_SHIFT 0 /**< Shift value for USB_FIFO7D */ +#define _USB_FIFO7D_FIFO7D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO7D */ +#define _USB_FIFO7D_FIFO7D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO7D */ +#define USB_FIFO7D_FIFO7D_DEFAULT (_USB_FIFO7D_FIFO7D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO7D */ + +/* Bit fields for USB FIFO8D */ +#define _USB_FIFO8D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO8D */ +#define _USB_FIFO8D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO8D */ +#define _USB_FIFO8D_FIFO8D_SHIFT 0 /**< Shift value for USB_FIFO8D */ +#define _USB_FIFO8D_FIFO8D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO8D */ +#define _USB_FIFO8D_FIFO8D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO8D */ +#define USB_FIFO8D_FIFO8D_DEFAULT (_USB_FIFO8D_FIFO8D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO8D */ + +/* Bit fields for USB FIFO9D */ +#define _USB_FIFO9D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO9D */ +#define _USB_FIFO9D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO9D */ +#define _USB_FIFO9D_FIFO9D_SHIFT 0 /**< Shift value for USB_FIFO9D */ +#define _USB_FIFO9D_FIFO9D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO9D */ +#define _USB_FIFO9D_FIFO9D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO9D */ +#define USB_FIFO9D_FIFO9D_DEFAULT (_USB_FIFO9D_FIFO9D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO9D */ + +/* Bit fields for USB FIFO10D */ +#define _USB_FIFO10D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO10D */ +#define _USB_FIFO10D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO10D */ +#define _USB_FIFO10D_FIFO10D_SHIFT 0 /**< Shift value for USB_FIFO10D */ +#define _USB_FIFO10D_FIFO10D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO10D */ +#define _USB_FIFO10D_FIFO10D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO10D */ +#define USB_FIFO10D_FIFO10D_DEFAULT (_USB_FIFO10D_FIFO10D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO10D */ + +/* Bit fields for USB FIFO11D */ +#define _USB_FIFO11D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO11D */ +#define _USB_FIFO11D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO11D */ +#define _USB_FIFO11D_FIFO11D_SHIFT 0 /**< Shift value for USB_FIFO11D */ +#define _USB_FIFO11D_FIFO11D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO11D */ +#define _USB_FIFO11D_FIFO11D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO11D */ +#define USB_FIFO11D_FIFO11D_DEFAULT (_USB_FIFO11D_FIFO11D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO11D */ + +/* Bit fields for USB FIFO12D */ +#define _USB_FIFO12D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO12D */ +#define _USB_FIFO12D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO12D */ +#define _USB_FIFO12D_FIFO12D_SHIFT 0 /**< Shift value for USB_FIFO12D */ +#define _USB_FIFO12D_FIFO12D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO12D */ +#define _USB_FIFO12D_FIFO12D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO12D */ +#define USB_FIFO12D_FIFO12D_DEFAULT (_USB_FIFO12D_FIFO12D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO12D */ + +/* Bit fields for USB FIFO13D */ +#define _USB_FIFO13D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO13D */ +#define _USB_FIFO13D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO13D */ +#define _USB_FIFO13D_FIFO13D_SHIFT 0 /**< Shift value for USB_FIFO13D */ +#define _USB_FIFO13D_FIFO13D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO13D */ +#define _USB_FIFO13D_FIFO13D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO13D */ +#define USB_FIFO13D_FIFO13D_DEFAULT (_USB_FIFO13D_FIFO13D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO13D */ + +/* Bit fields for USB FIFORAM */ +#define _USB_FIFORAM_RESETVALUE 0x00000000UL /**< Default value for USB_FIFORAM */ +#define _USB_FIFORAM_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFORAM */ +#define _USB_FIFORAM_FIFORAM_SHIFT 0 /**< Shift value for USB_FIFORAM */ +#define _USB_FIFORAM_FIFORAM_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFORAM */ +#define _USB_FIFORAM_FIFORAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFORAM */ +#define USB_FIFORAM_FIFORAM_DEFAULT (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */ + +/** @} */ +/** @} End of group EFM32GG11B_USB */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_diep.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_diep.h new file mode 100644 index 0000000000000..2da1580565a69 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_diep.h @@ -0,0 +1,65 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_USB_DIEP register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief USB_DIEP USB DIEP Register + * @ingroup EFM32GG11B_USB + ******************************************************************************/ +typedef struct { + __IOM uint32_t CTL; /**< Device Control IN Endpoint x+1 Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t INT; /**< Device IN Endpoint x+1 Interrupt Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t TSIZ; /**< Device IN Endpoint x+1 Transfer Size Register */ + __IOM uint32_t DMAADDR; /**< Device IN Endpoint x+1 DMA Address Register */ + __IM uint32_t DTXFSTS; /**< Device IN Endpoint Transmit FIFO Status Register 1 */ + uint32_t RESERVED2[1U]; /**< Reserved future */ +} USB_DIEP_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_doep.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_doep.h new file mode 100644 index 0000000000000..650e28b1ad078 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_doep.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_USB_DOEP register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief USB_DOEP USB DOEP Register + * @ingroup EFM32GG11B_USB + ******************************************************************************/ +typedef struct { + __IOM uint32_t CTL; /**< Device Control OUT Endpoint x+1 Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use **/ + __IOM uint32_t INT; /**< Device OUT Endpoint x+1 Interrupt Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use **/ + __IOM uint32_t TSIZ; /**< Device OUT Endpoint x+1 Transfer Size Register */ + __IOM uint32_t DMAADDR; /**< Device OUT Endpoint x+1 DMA Address Register */ + uint32_t RESERVED2[2U]; /**< Reserved future */ +} USB_DOEP_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_hc.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_hc.h new file mode 100644 index 0000000000000..a4c252bcc45af --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_usb_hc.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_USB_HC register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief USB_HC USB HC Register + * @ingroup EFM32GG11B_USB + ******************************************************************************/ +typedef struct { + __IOM uint32_t CHAR; /**< Host Channel x Characteristics Register */ + __IOM uint32_t SPLT; /**< Host Channel x Split Control Register */ + __IOM uint32_t INT; /**< Host Channel x Interrupt Register */ + __IOM uint32_t INTMSK; /**< Host Channel x Interrupt Mask Register */ + __IOM uint32_t TSIZ; /**< Host Channel x Transfer Size Register */ + __IOM uint32_t DMAADDR; /**< Host Channel x DMA Address Register */ + uint32_t RESERVED0[2U]; /**< Reserved future */ +} USB_HC_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_vdac.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_vdac.h new file mode 100644 index 0000000000000..f7cf43a1a9dda --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_vdac.h @@ -0,0 +1,1717 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_VDAC register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_VDAC VDAC + * @{ + * @brief EFM32GG11B_VDAC Register Declaration + ******************************************************************************/ +/** VDAC Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */ + __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */ + __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */ + __IOM uint32_t COMBDATA; /**< Combined Data Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + + uint32_t RESERVED0[27U]; /**< Reserved registers */ + VDAC_OPA_TypeDef OPA[4U]; /**< OPA Registers */ +} VDAC_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_VDAC + * @{ + * @defgroup EFM32GG11B_VDAC_BitFields VDAC Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for VDAC CTRL */ +#define _VDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CTRL */ +#define _VDAC_CTRL_MASK 0x937F0771UL /**< Mask for VDAC_CTRL */ +#define VDAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */ +#define _VDAC_CTRL_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ +#define _VDAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ +#define _VDAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_DIFF_DEFAULT (_VDAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_SINEMODE (0x1UL << 4) /**< Sine Mode */ +#define _VDAC_CTRL_SINEMODE_SHIFT 4 /**< Shift value for VDAC_SINEMODE */ +#define _VDAC_CTRL_SINEMODE_MASK 0x10UL /**< Bit mask for VDAC_SINEMODE */ +#define _VDAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_SINEMODE_DEFAULT (_VDAC_CTRL_SINEMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_OUTENPRS (0x1UL << 5) /**< PRS Controlled Output Enable */ +#define _VDAC_CTRL_OUTENPRS_SHIFT 5 /**< Shift value for VDAC_OUTENPRS */ +#define _VDAC_CTRL_OUTENPRS_MASK 0x20UL /**< Bit mask for VDAC_OUTENPRS */ +#define _VDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_OUTENPRS_DEFAULT (_VDAC_CTRL_OUTENPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_CH0PRESCRST (0x1UL << 6) /**< Channel 0 Start Reset Prescaler */ +#define _VDAC_CTRL_CH0PRESCRST_SHIFT 6 /**< Shift value for VDAC_CH0PRESCRST */ +#define _VDAC_CTRL_CH0PRESCRST_MASK 0x40UL /**< Bit mask for VDAC_CH0PRESCRST */ +#define _VDAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_CH0PRESCRST_DEFAULT (_VDAC_CTRL_CH0PRESCRST_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for VDAC_REFSEL */ +#define _VDAC_CTRL_REFSEL_MASK 0x700UL /**< Bit mask for VDAC_REFSEL */ +#define _VDAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_1V25LN 0x00000000UL /**< Mode 1V25LN for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_2V5LN 0x00000001UL /**< Mode 2V5LN for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_1V25 0x00000002UL /**< Mode 1V25 for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_2V5 0x00000003UL /**< Mode 2V5 for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_VDD 0x00000004UL /**< Mode VDD for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_EXT 0x00000006UL /**< Mode EXT for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_DEFAULT (_VDAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_1V25LN (_VDAC_CTRL_REFSEL_1V25LN << 8) /**< Shifted mode 1V25LN for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_2V5LN (_VDAC_CTRL_REFSEL_2V5LN << 8) /**< Shifted mode 2V5LN for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_1V25 (_VDAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_2V5 (_VDAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_VDD (_VDAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_EXT (_VDAC_CTRL_REFSEL_EXT << 8) /**< Shifted mode EXT for VDAC_CTRL */ +#define _VDAC_CTRL_PRESC_SHIFT 16 /**< Shift value for VDAC_PRESC */ +#define _VDAC_CTRL_PRESC_MASK 0x7F0000UL /**< Bit mask for VDAC_PRESC */ +#define _VDAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for VDAC_CTRL */ +#define VDAC_CTRL_PRESC_DEFAULT (_VDAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_PRESC_NODIVISION (_VDAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_SHIFT 24 /**< Shift value for VDAC_REFRESHPERIOD */ +#define _VDAC_CTRL_REFRESHPERIOD_MASK 0x3000000UL /**< Bit mask for VDAC_REFRESHPERIOD */ +#define _VDAC_CTRL_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_8CYCLES 0x00000000UL /**< Mode 8CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_16CYCLES 0x00000001UL /**< Mode 16CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_32CYCLES 0x00000002UL /**< Mode 32CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_64CYCLES 0x00000003UL /**< Mode 64CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_DEFAULT (_VDAC_CTRL_REFRESHPERIOD_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_8CYCLES (_VDAC_CTRL_REFRESHPERIOD_8CYCLES << 24) /**< Shifted mode 8CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_16CYCLES (_VDAC_CTRL_REFRESHPERIOD_16CYCLES << 24) /**< Shifted mode 16CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_32CYCLES (_VDAC_CTRL_REFRESHPERIOD_32CYCLES << 24) /**< Shifted mode 32CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_64CYCLES (_VDAC_CTRL_REFRESHPERIOD_64CYCLES << 24) /**< Shifted mode 64CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE (0x1UL << 28) /**< Warm-up Mode */ +#define _VDAC_CTRL_WARMUPMODE_SHIFT 28 /**< Shift value for VDAC_WARMUPMODE */ +#define _VDAC_CTRL_WARMUPMODE_MASK 0x10000000UL /**< Bit mask for VDAC_WARMUPMODE */ +#define _VDAC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CTRL */ +#define _VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_DEFAULT (_VDAC_CTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_NORMAL (_VDAC_CTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY (_VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY << 28) /**< Shifted mode KEEPINSTANDBY for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE (0x1UL << 31) /**< Clock Mode */ +#define _VDAC_CTRL_DACCLKMODE_SHIFT 31 /**< Shift value for VDAC_DACCLKMODE */ +#define _VDAC_CTRL_DACCLKMODE_MASK 0x80000000UL /**< Bit mask for VDAC_DACCLKMODE */ +#define _VDAC_CTRL_DACCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_DACCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for VDAC_CTRL */ +#define _VDAC_CTRL_DACCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_DEFAULT (_VDAC_CTRL_DACCLKMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_SYNC (_VDAC_CTRL_DACCLKMODE_SYNC << 31) /**< Shifted mode SYNC for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_ASYNC (_VDAC_CTRL_DACCLKMODE_ASYNC << 31) /**< Shifted mode ASYNC for VDAC_CTRL */ + +/* Bit fields for VDAC STATUS */ +#define _VDAC_STATUS_RESETVALUE 0x0000000CUL /**< Default value for VDAC_STATUS */ +#define _VDAC_STATUS_MASK 0xFFFF003FUL /**< Mask for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ +#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ +#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0BL (0x1UL << 2) /**< Channel 0 Buffer Level */ +#define _VDAC_STATUS_CH0BL_SHIFT 2 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_STATUS_CH0BL_MASK 0x4UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_STATUS_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0BL_DEFAULT (_VDAC_STATUS_CH0BL_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1BL (0x1UL << 3) /**< Channel 1 Buffer Level */ +#define _VDAC_STATUS_CH1BL_SHIFT 3 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_STATUS_CH1BL_MASK 0x8UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_STATUS_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1BL_DEFAULT (_VDAC_STATUS_CH1BL_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warm */ +#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warm */ +#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA3APORTCONFLICT (0x1UL << 19) /**< OPA3 Bus Conflict Output */ +#define _VDAC_STATUS_OPA3APORTCONFLICT_SHIFT 19 /**< Shift value for VDAC_OPA3APORTCONFLICT */ +#define _VDAC_STATUS_OPA3APORTCONFLICT_MASK 0x80000UL /**< Bit mask for VDAC_OPA3APORTCONFLICT */ +#define _VDAC_STATUS_OPA3APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA3APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA3APORTCONFLICT_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0ENS (0x1UL << 20) /**< OPA0 Enabled Status */ +#define _VDAC_STATUS_OPA0ENS_SHIFT 20 /**< Shift value for VDAC_OPA0ENS */ +#define _VDAC_STATUS_OPA0ENS_MASK 0x100000UL /**< Bit mask for VDAC_OPA0ENS */ +#define _VDAC_STATUS_OPA0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0ENS_DEFAULT (_VDAC_STATUS_OPA0ENS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1ENS (0x1UL << 21) /**< OPA1 Enabled Status */ +#define _VDAC_STATUS_OPA1ENS_SHIFT 21 /**< Shift value for VDAC_OPA1ENS */ +#define _VDAC_STATUS_OPA1ENS_MASK 0x200000UL /**< Bit mask for VDAC_OPA1ENS */ +#define _VDAC_STATUS_OPA1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1ENS_DEFAULT (_VDAC_STATUS_OPA1ENS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2ENS (0x1UL << 22) /**< OPA2 Enabled Status */ +#define _VDAC_STATUS_OPA2ENS_SHIFT 22 /**< Shift value for VDAC_OPA2ENS */ +#define _VDAC_STATUS_OPA2ENS_MASK 0x400000UL /**< Bit mask for VDAC_OPA2ENS */ +#define _VDAC_STATUS_OPA2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2ENS_DEFAULT (_VDAC_STATUS_OPA2ENS_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA3ENS (0x1UL << 23) /**< OPA3 Enabled Status */ +#define _VDAC_STATUS_OPA3ENS_SHIFT 23 /**< Shift value for VDAC_OPA3ENS */ +#define _VDAC_STATUS_OPA3ENS_MASK 0x800000UL /**< Bit mask for VDAC_OPA3ENS */ +#define _VDAC_STATUS_OPA3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA3ENS_DEFAULT (_VDAC_STATUS_OPA3ENS_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0WARM (0x1UL << 24) /**< OPA0 Warm Status */ +#define _VDAC_STATUS_OPA0WARM_SHIFT 24 /**< Shift value for VDAC_OPA0WARM */ +#define _VDAC_STATUS_OPA0WARM_MASK 0x1000000UL /**< Bit mask for VDAC_OPA0WARM */ +#define _VDAC_STATUS_OPA0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0WARM_DEFAULT (_VDAC_STATUS_OPA0WARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1WARM (0x1UL << 25) /**< OPA1 Warm Status */ +#define _VDAC_STATUS_OPA1WARM_SHIFT 25 /**< Shift value for VDAC_OPA1WARM */ +#define _VDAC_STATUS_OPA1WARM_MASK 0x2000000UL /**< Bit mask for VDAC_OPA1WARM */ +#define _VDAC_STATUS_OPA1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1WARM_DEFAULT (_VDAC_STATUS_OPA1WARM_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2WARM (0x1UL << 26) /**< OPA2 Warm Status */ +#define _VDAC_STATUS_OPA2WARM_SHIFT 26 /**< Shift value for VDAC_OPA2WARM */ +#define _VDAC_STATUS_OPA2WARM_MASK 0x4000000UL /**< Bit mask for VDAC_OPA2WARM */ +#define _VDAC_STATUS_OPA2WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2WARM_DEFAULT (_VDAC_STATUS_OPA2WARM_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA3WARM (0x1UL << 27) /**< OPA3 Warm Status */ +#define _VDAC_STATUS_OPA3WARM_SHIFT 27 /**< Shift value for VDAC_OPA3WARM */ +#define _VDAC_STATUS_OPA3WARM_MASK 0x8000000UL /**< Bit mask for VDAC_OPA3WARM */ +#define _VDAC_STATUS_OPA3WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA3WARM_DEFAULT (_VDAC_STATUS_OPA3WARM_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Status */ +#define _VDAC_STATUS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_STATUS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_STATUS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0OUTVALID_DEFAULT (_VDAC_STATUS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Status */ +#define _VDAC_STATUS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_STATUS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_STATUS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1OUTVALID_DEFAULT (_VDAC_STATUS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2OUTVALID (0x1UL << 30) /**< OPA2 Output Valid Status */ +#define _VDAC_STATUS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_STATUS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_STATUS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2OUTVALID_DEFAULT (_VDAC_STATUS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA3OUTVALID (0x1UL << 31) /**< OPA3 Output Valid Status */ +#define _VDAC_STATUS_OPA3OUTVALID_SHIFT 31 /**< Shift value for VDAC_OPA3OUTVALID */ +#define _VDAC_STATUS_OPA3OUTVALID_MASK 0x80000000UL /**< Bit mask for VDAC_OPA3OUTVALID */ +#define _VDAC_STATUS_OPA3OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA3OUTVALID_DEFAULT (_VDAC_STATUS_OPA3OUTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */ + +/* Bit fields for VDAC CH0CTRL */ +#define _VDAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_MASK 0x0001F171UL /**< Mask for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ +#define _VDAC_CH0CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH0CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH0CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_DEFAULT (_VDAC_CH0CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_CONTINUOUS (_VDAC_CH0CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH0CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH0CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH0CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_DEFAULT (_VDAC_CH0CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SW (_VDAC_CH0CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_PRS (_VDAC_CH0CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_REFRESH (_VDAC_CH0CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SWPRS (_VDAC_CH0CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SWREFRESH (_VDAC_CH0CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_LESENSE (_VDAC_CH0CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSASYNC (0x1UL << 8) /**< Channel 0 PRS Asynchronous Enable */ +#define _VDAC_CH0CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ +#define _VDAC_CH0CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ +#define _VDAC_CH0CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSASYNC_DEFAULT (_VDAC_CH0CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ +#define _VDAC_CH0CTRL_PRSSEL_MASK 0x1F000UL /**< Bit mask for VDAC_PRSSEL */ +#define _VDAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_DEFAULT (_VDAC_CH0CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH0 (_VDAC_CH0CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH1 (_VDAC_CH0CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH2 (_VDAC_CH0CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH3 (_VDAC_CH0CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH4 (_VDAC_CH0CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH5 (_VDAC_CH0CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH6 (_VDAC_CH0CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH7 (_VDAC_CH0CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH8 (_VDAC_CH0CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH9 (_VDAC_CH0CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH10 (_VDAC_CH0CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH11 (_VDAC_CH0CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH12 (_VDAC_CH0CTRL_PRSSEL_PRSCH12 << 12) /**< Shifted mode PRSCH12 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH13 (_VDAC_CH0CTRL_PRSSEL_PRSCH13 << 12) /**< Shifted mode PRSCH13 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH14 (_VDAC_CH0CTRL_PRSSEL_PRSCH14 << 12) /**< Shifted mode PRSCH14 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH15 (_VDAC_CH0CTRL_PRSSEL_PRSCH15 << 12) /**< Shifted mode PRSCH15 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH16 (_VDAC_CH0CTRL_PRSSEL_PRSCH16 << 12) /**< Shifted mode PRSCH16 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH17 (_VDAC_CH0CTRL_PRSSEL_PRSCH17 << 12) /**< Shifted mode PRSCH17 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH18 (_VDAC_CH0CTRL_PRSSEL_PRSCH18 << 12) /**< Shifted mode PRSCH18 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH19 (_VDAC_CH0CTRL_PRSSEL_PRSCH19 << 12) /**< Shifted mode PRSCH19 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH20 (_VDAC_CH0CTRL_PRSSEL_PRSCH20 << 12) /**< Shifted mode PRSCH20 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH21 (_VDAC_CH0CTRL_PRSSEL_PRSCH21 << 12) /**< Shifted mode PRSCH21 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH22 (_VDAC_CH0CTRL_PRSSEL_PRSCH22 << 12) /**< Shifted mode PRSCH22 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH23 (_VDAC_CH0CTRL_PRSSEL_PRSCH23 << 12) /**< Shifted mode PRSCH23 for VDAC_CH0CTRL */ + +/* Bit fields for VDAC CH1CTRL */ +#define _VDAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_MASK 0x0001F171UL /**< Mask for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ +#define _VDAC_CH1CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH1CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH1CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_DEFAULT (_VDAC_CH1CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_CONTINUOUS (_VDAC_CH1CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH1CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH1CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH1CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_DEFAULT (_VDAC_CH1CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SW (_VDAC_CH1CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_PRS (_VDAC_CH1CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_REFRESH (_VDAC_CH1CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SWPRS (_VDAC_CH1CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SWREFRESH (_VDAC_CH1CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_LESENSE (_VDAC_CH1CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSASYNC (0x1UL << 8) /**< Channel 1 PRS Asynchronous Enable */ +#define _VDAC_CH1CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ +#define _VDAC_CH1CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ +#define _VDAC_CH1CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSASYNC_DEFAULT (_VDAC_CH1CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ +#define _VDAC_CH1CTRL_PRSSEL_MASK 0x1F000UL /**< Bit mask for VDAC_PRSSEL */ +#define _VDAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_DEFAULT (_VDAC_CH1CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH0 (_VDAC_CH1CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH1 (_VDAC_CH1CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH2 (_VDAC_CH1CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH3 (_VDAC_CH1CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH4 (_VDAC_CH1CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH5 (_VDAC_CH1CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH6 (_VDAC_CH1CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH7 (_VDAC_CH1CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH8 (_VDAC_CH1CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH9 (_VDAC_CH1CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH10 (_VDAC_CH1CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH11 (_VDAC_CH1CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH12 (_VDAC_CH1CTRL_PRSSEL_PRSCH12 << 12) /**< Shifted mode PRSCH12 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH13 (_VDAC_CH1CTRL_PRSSEL_PRSCH13 << 12) /**< Shifted mode PRSCH13 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH14 (_VDAC_CH1CTRL_PRSSEL_PRSCH14 << 12) /**< Shifted mode PRSCH14 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH15 (_VDAC_CH1CTRL_PRSSEL_PRSCH15 << 12) /**< Shifted mode PRSCH15 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH16 (_VDAC_CH1CTRL_PRSSEL_PRSCH16 << 12) /**< Shifted mode PRSCH16 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH17 (_VDAC_CH1CTRL_PRSSEL_PRSCH17 << 12) /**< Shifted mode PRSCH17 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH18 (_VDAC_CH1CTRL_PRSSEL_PRSCH18 << 12) /**< Shifted mode PRSCH18 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH19 (_VDAC_CH1CTRL_PRSSEL_PRSCH19 << 12) /**< Shifted mode PRSCH19 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH20 (_VDAC_CH1CTRL_PRSSEL_PRSCH20 << 12) /**< Shifted mode PRSCH20 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH21 (_VDAC_CH1CTRL_PRSSEL_PRSCH21 << 12) /**< Shifted mode PRSCH21 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH22 (_VDAC_CH1CTRL_PRSSEL_PRSCH22 << 12) /**< Shifted mode PRSCH22 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH23 (_VDAC_CH1CTRL_PRSSEL_PRSCH23 << 12) /**< Shifted mode PRSCH23 for VDAC_CH1CTRL */ + +/* Bit fields for VDAC CMD */ +#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ +#define _VDAC_CMD_MASK 0x00FF000FUL /**< Mask for VDAC_CMD */ +#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ +#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ +#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN (0x1UL << 2) /**< DAC Channel 1 Enable */ +#define _VDAC_CMD_CH1EN_SHIFT 2 /**< Shift value for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_MASK 0x4UL /**< Bit mask for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS (0x1UL << 3) /**< DAC Channel 1 Disable */ +#define _VDAC_CMD_CH1DIS_SHIFT 3 /**< Shift value for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_MASK 0x8UL /**< Bit mask for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0EN (0x1UL << 16) /**< OPA0 Enable */ +#define _VDAC_CMD_OPA0EN_SHIFT 16 /**< Shift value for VDAC_OPA0EN */ +#define _VDAC_CMD_OPA0EN_MASK 0x10000UL /**< Bit mask for VDAC_OPA0EN */ +#define _VDAC_CMD_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0EN_DEFAULT (_VDAC_CMD_OPA0EN_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0DIS (0x1UL << 17) /**< OPA0 Disable */ +#define _VDAC_CMD_OPA0DIS_SHIFT 17 /**< Shift value for VDAC_OPA0DIS */ +#define _VDAC_CMD_OPA0DIS_MASK 0x20000UL /**< Bit mask for VDAC_OPA0DIS */ +#define _VDAC_CMD_OPA0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0DIS_DEFAULT (_VDAC_CMD_OPA0DIS_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1EN (0x1UL << 18) /**< OPA1 Enable */ +#define _VDAC_CMD_OPA1EN_SHIFT 18 /**< Shift value for VDAC_OPA1EN */ +#define _VDAC_CMD_OPA1EN_MASK 0x40000UL /**< Bit mask for VDAC_OPA1EN */ +#define _VDAC_CMD_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1EN_DEFAULT (_VDAC_CMD_OPA1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1DIS (0x1UL << 19) /**< OPA1 Disable */ +#define _VDAC_CMD_OPA1DIS_SHIFT 19 /**< Shift value for VDAC_OPA1DIS */ +#define _VDAC_CMD_OPA1DIS_MASK 0x80000UL /**< Bit mask for VDAC_OPA1DIS */ +#define _VDAC_CMD_OPA1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1DIS_DEFAULT (_VDAC_CMD_OPA1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2EN (0x1UL << 20) /**< OPA2 Enable */ +#define _VDAC_CMD_OPA2EN_SHIFT 20 /**< Shift value for VDAC_OPA2EN */ +#define _VDAC_CMD_OPA2EN_MASK 0x100000UL /**< Bit mask for VDAC_OPA2EN */ +#define _VDAC_CMD_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2EN_DEFAULT (_VDAC_CMD_OPA2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2DIS (0x1UL << 21) /**< OPA2 Disable */ +#define _VDAC_CMD_OPA2DIS_SHIFT 21 /**< Shift value for VDAC_OPA2DIS */ +#define _VDAC_CMD_OPA2DIS_MASK 0x200000UL /**< Bit mask for VDAC_OPA2DIS */ +#define _VDAC_CMD_OPA2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2DIS_DEFAULT (_VDAC_CMD_OPA2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA3EN (0x1UL << 22) /**< OPA3 Enable */ +#define _VDAC_CMD_OPA3EN_SHIFT 22 /**< Shift value for VDAC_OPA3EN */ +#define _VDAC_CMD_OPA3EN_MASK 0x400000UL /**< Bit mask for VDAC_OPA3EN */ +#define _VDAC_CMD_OPA3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA3EN_DEFAULT (_VDAC_CMD_OPA3EN_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA3DIS (0x1UL << 23) /**< OPA3 Disable */ +#define _VDAC_CMD_OPA3DIS_SHIFT 23 /**< Shift value for VDAC_OPA3DIS */ +#define _VDAC_CMD_OPA3DIS_MASK 0x800000UL /**< Bit mask for VDAC_OPA3DIS */ +#define _VDAC_CMD_OPA3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA3DIS_DEFAULT (_VDAC_CMD_OPA3DIS_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_CMD */ + +/* Bit fields for VDAC IF */ +#define _VDAC_IF_RESETVALUE 0x000000C0UL /**< Default value for VDAC_IF */ +#define _VDAC_IF_MASK 0xF0FF80FFUL /**< Mask for VDAC_IF */ +#define VDAC_IF_CH0CD (0x1UL << 0) /**< Channel 0 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD (0x1UL << 1) /**< Channel 1 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF (0x1UL << 2) /**< Channel 0 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF (0x1UL << 3) /**< Channel 1 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0BL (0x1UL << 6) /**< Channel 0 Buffer Level Interrupt Flag */ +#define _VDAC_IF_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_IF_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_IF_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0BL_DEFAULT (_VDAC_IF_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1BL (0x1UL << 7) /**< Channel 1 Buffer Level Interrupt Flag */ +#define _VDAC_IF_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_IF_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_IF_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1BL_DEFAULT (_VDAC_IF_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_EM23ERR (0x1UL << 15) /**< EM2/3 Entry Error Flag */ +#define _VDAC_IF_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IF_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_EM23ERR_DEFAULT (_VDAC_IF_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IF_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IF_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0APORTCONFLICT_DEFAULT (_VDAC_IF_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IF_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IF_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1APORTCONFLICT_DEFAULT (_VDAC_IF_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IF_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IF_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2APORTCONFLICT_DEFAULT (_VDAC_IF_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA3APORTCONFLICT (0x1UL << 19) /**< OPA3 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA3APORTCONFLICT_SHIFT 19 /**< Shift value for VDAC_OPA3APORTCONFLICT */ +#define _VDAC_IF_OPA3APORTCONFLICT_MASK 0x80000UL /**< Bit mask for VDAC_OPA3APORTCONFLICT */ +#define _VDAC_IF_OPA3APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA3APORTCONFLICT_DEFAULT (_VDAC_IF_OPA3APORTCONFLICT_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IF_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IF_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IF_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IF_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IF_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IF_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA3PRSTIMEDERR (0x1UL << 23) /**< OPA3 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA3PRSTIMEDERR_SHIFT 23 /**< Shift value for VDAC_OPA3PRSTIMEDERR */ +#define _VDAC_IF_OPA3PRSTIMEDERR_MASK 0x800000UL /**< Bit mask for VDAC_OPA3PRSTIMEDERR */ +#define _VDAC_IF_OPA3PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA3PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA3PRSTIMEDERR_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IF_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IF_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0OUTVALID_DEFAULT (_VDAC_IF_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IF_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IF_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1OUTVALID_DEFAULT (_VDAC_IF_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2OUTVALID (0x1UL << 30) /**< OPA3 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IF_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IF_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2OUTVALID_DEFAULT (_VDAC_IF_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA3OUTVALID (0x1UL << 31) /**< OPA3 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA3OUTVALID_SHIFT 31 /**< Shift value for VDAC_OPA3OUTVALID */ +#define _VDAC_IF_OPA3OUTVALID_MASK 0x80000000UL /**< Bit mask for VDAC_OPA3OUTVALID */ +#define _VDAC_IF_OPA3OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA3OUTVALID_DEFAULT (_VDAC_IF_OPA3OUTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_IF */ + +/* Bit fields for VDAC IFS */ +#define _VDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFS */ +#define _VDAC_IFS_MASK 0xF0FF803FUL /**< Mask for VDAC_IFS */ +#define VDAC_IFS_CH0CD (0x1UL << 0) /**< Set CH0CD Interrupt Flag */ +#define _VDAC_IFS_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IFS_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IFS_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0CD_DEFAULT (_VDAC_IFS_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1CD (0x1UL << 1) /**< Set CH1CD Interrupt Flag */ +#define _VDAC_IFS_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IFS_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IFS_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1CD_DEFAULT (_VDAC_IFS_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0OF (0x1UL << 2) /**< Set CH0OF Interrupt Flag */ +#define _VDAC_IFS_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IFS_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IFS_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0OF_DEFAULT (_VDAC_IFS_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1OF (0x1UL << 3) /**< Set CH1OF Interrupt Flag */ +#define _VDAC_IFS_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IFS_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IFS_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1OF_DEFAULT (_VDAC_IFS_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0UF (0x1UL << 4) /**< Set CH0UF Interrupt Flag */ +#define _VDAC_IFS_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0UF_DEFAULT (_VDAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1UF (0x1UL << 5) /**< Set CH1UF Interrupt Flag */ +#define _VDAC_IFS_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1UF_DEFAULT (_VDAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_EM23ERR (0x1UL << 15) /**< Set EM23ERR Interrupt Flag */ +#define _VDAC_IFS_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IFS_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_EM23ERR_DEFAULT (_VDAC_IFS_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0APORTCONFLICT (0x1UL << 16) /**< Set OPA0APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1APORTCONFLICT (0x1UL << 17) /**< Set OPA1APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2APORTCONFLICT (0x1UL << 18) /**< Set OPA2APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA3APORTCONFLICT (0x1UL << 19) /**< Set OPA3APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA3APORTCONFLICT_SHIFT 19 /**< Shift value for VDAC_OPA3APORTCONFLICT */ +#define _VDAC_IFS_OPA3APORTCONFLICT_MASK 0x80000UL /**< Bit mask for VDAC_OPA3APORTCONFLICT */ +#define _VDAC_IFS_OPA3APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA3APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA3APORTCONFLICT_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0PRSTIMEDERR (0x1UL << 20) /**< Set OPA0PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1PRSTIMEDERR (0x1UL << 21) /**< Set OPA1PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2PRSTIMEDERR (0x1UL << 22) /**< Set OPA2PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA3PRSTIMEDERR (0x1UL << 23) /**< Set OPA3PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA3PRSTIMEDERR_SHIFT 23 /**< Shift value for VDAC_OPA3PRSTIMEDERR */ +#define _VDAC_IFS_OPA3PRSTIMEDERR_MASK 0x800000UL /**< Bit mask for VDAC_OPA3PRSTIMEDERR */ +#define _VDAC_IFS_OPA3PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA3PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA3PRSTIMEDERR_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0OUTVALID (0x1UL << 28) /**< Set OPA0OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IFS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IFS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0OUTVALID_DEFAULT (_VDAC_IFS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1OUTVALID (0x1UL << 29) /**< Set OPA1OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IFS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IFS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1OUTVALID_DEFAULT (_VDAC_IFS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2OUTVALID (0x1UL << 30) /**< Set OPA2OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IFS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IFS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2OUTVALID_DEFAULT (_VDAC_IFS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA3OUTVALID (0x1UL << 31) /**< Set OPA3OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA3OUTVALID_SHIFT 31 /**< Shift value for VDAC_OPA3OUTVALID */ +#define _VDAC_IFS_OPA3OUTVALID_MASK 0x80000000UL /**< Bit mask for VDAC_OPA3OUTVALID */ +#define _VDAC_IFS_OPA3OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA3OUTVALID_DEFAULT (_VDAC_IFS_OPA3OUTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_IFS */ + +/* Bit fields for VDAC IFC */ +#define _VDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFC */ +#define _VDAC_IFC_MASK 0xF0FF803FUL /**< Mask for VDAC_IFC */ +#define VDAC_IFC_CH0CD (0x1UL << 0) /**< Clear CH0CD Interrupt Flag */ +#define _VDAC_IFC_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IFC_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IFC_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0CD_DEFAULT (_VDAC_IFC_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1CD (0x1UL << 1) /**< Clear CH1CD Interrupt Flag */ +#define _VDAC_IFC_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IFC_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IFC_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1CD_DEFAULT (_VDAC_IFC_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0OF (0x1UL << 2) /**< Clear CH0OF Interrupt Flag */ +#define _VDAC_IFC_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IFC_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IFC_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0OF_DEFAULT (_VDAC_IFC_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1OF (0x1UL << 3) /**< Clear CH1OF Interrupt Flag */ +#define _VDAC_IFC_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IFC_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IFC_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1OF_DEFAULT (_VDAC_IFC_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0UF (0x1UL << 4) /**< Clear CH0UF Interrupt Flag */ +#define _VDAC_IFC_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0UF_DEFAULT (_VDAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1UF (0x1UL << 5) /**< Clear CH1UF Interrupt Flag */ +#define _VDAC_IFC_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1UF_DEFAULT (_VDAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_EM23ERR (0x1UL << 15) /**< Clear EM23ERR Interrupt Flag */ +#define _VDAC_IFC_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IFC_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_EM23ERR_DEFAULT (_VDAC_IFC_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0APORTCONFLICT (0x1UL << 16) /**< Clear OPA0APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFC_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFC_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1APORTCONFLICT (0x1UL << 17) /**< Clear OPA1APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFC_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFC_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2APORTCONFLICT (0x1UL << 18) /**< Clear OPA2APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFC_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFC_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA3APORTCONFLICT (0x1UL << 19) /**< Clear OPA3APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA3APORTCONFLICT_SHIFT 19 /**< Shift value for VDAC_OPA3APORTCONFLICT */ +#define _VDAC_IFC_OPA3APORTCONFLICT_MASK 0x80000UL /**< Bit mask for VDAC_OPA3APORTCONFLICT */ +#define _VDAC_IFC_OPA3APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA3APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA3APORTCONFLICT_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0PRSTIMEDERR (0x1UL << 20) /**< Clear OPA0PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1PRSTIMEDERR (0x1UL << 21) /**< Clear OPA1PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2PRSTIMEDERR (0x1UL << 22) /**< Clear OPA2PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA3PRSTIMEDERR (0x1UL << 23) /**< Clear OPA3PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA3PRSTIMEDERR_SHIFT 23 /**< Shift value for VDAC_OPA3PRSTIMEDERR */ +#define _VDAC_IFC_OPA3PRSTIMEDERR_MASK 0x800000UL /**< Bit mask for VDAC_OPA3PRSTIMEDERR */ +#define _VDAC_IFC_OPA3PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA3PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA3PRSTIMEDERR_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0OUTVALID (0x1UL << 28) /**< Clear OPA0OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IFC_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IFC_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0OUTVALID_DEFAULT (_VDAC_IFC_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1OUTVALID (0x1UL << 29) /**< Clear OPA1OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IFC_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IFC_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1OUTVALID_DEFAULT (_VDAC_IFC_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2OUTVALID (0x1UL << 30) /**< Clear OPA2OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IFC_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IFC_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2OUTVALID_DEFAULT (_VDAC_IFC_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA3OUTVALID (0x1UL << 31) /**< Clear OPA3OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA3OUTVALID_SHIFT 31 /**< Shift value for VDAC_OPA3OUTVALID */ +#define _VDAC_IFC_OPA3OUTVALID_MASK 0x80000000UL /**< Bit mask for VDAC_OPA3OUTVALID */ +#define _VDAC_IFC_OPA3OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA3OUTVALID_DEFAULT (_VDAC_IFC_OPA3OUTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_IFC */ + +/* Bit fields for VDAC IEN */ +#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ +#define _VDAC_IEN_MASK 0xF0FF80FFUL /**< Mask for VDAC_IEN */ +#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0CD Interrupt Enable */ +#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1CD Interrupt Enable */ +#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF (0x1UL << 2) /**< CH0OF Interrupt Enable */ +#define _VDAC_IEN_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF (0x1UL << 3) /**< CH1OF Interrupt Enable */ +#define _VDAC_IEN_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF (0x1UL << 4) /**< CH0UF Interrupt Enable */ +#define _VDAC_IEN_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF (0x1UL << 5) /**< CH1UF Interrupt Enable */ +#define _VDAC_IEN_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0BL (0x1UL << 6) /**< CH0BL Interrupt Enable */ +#define _VDAC_IEN_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_IEN_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_IEN_CH0BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0BL_DEFAULT (_VDAC_IEN_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1BL (0x1UL << 7) /**< CH1BL Interrupt Enable */ +#define _VDAC_IEN_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_IEN_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_IEN_CH1BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1BL_DEFAULT (_VDAC_IEN_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_EM23ERR (0x1UL << 15) /**< EM23ERR Interrupt Enable */ +#define _VDAC_IEN_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IEN_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_EM23ERR_DEFAULT (_VDAC_IEN_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IEN_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IEN_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IEN_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IEN_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IEN_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IEN_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA3APORTCONFLICT (0x1UL << 19) /**< OPA3APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA3APORTCONFLICT_SHIFT 19 /**< Shift value for VDAC_OPA3APORTCONFLICT */ +#define _VDAC_IEN_OPA3APORTCONFLICT_MASK 0x80000UL /**< Bit mask for VDAC_OPA3APORTCONFLICT */ +#define _VDAC_IEN_OPA3APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA3APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA3APORTCONFLICT_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA3PRSTIMEDERR (0x1UL << 23) /**< OPA3PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA3PRSTIMEDERR_SHIFT 23 /**< Shift value for VDAC_OPA3PRSTIMEDERR */ +#define _VDAC_IEN_OPA3PRSTIMEDERR_MASK 0x800000UL /**< Bit mask for VDAC_OPA3PRSTIMEDERR */ +#define _VDAC_IEN_OPA3PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA3PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA3PRSTIMEDERR_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0OUTVALID (0x1UL << 28) /**< OPA0OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IEN_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IEN_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0OUTVALID_DEFAULT (_VDAC_IEN_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1OUTVALID (0x1UL << 29) /**< OPA1OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IEN_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IEN_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1OUTVALID_DEFAULT (_VDAC_IEN_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2OUTVALID (0x1UL << 30) /**< OPA2OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IEN_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IEN_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2OUTVALID_DEFAULT (_VDAC_IEN_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA3OUTVALID (0x1UL << 31) /**< OPA3OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA3OUTVALID_SHIFT 31 /**< Shift value for VDAC_OPA3OUTVALID */ +#define _VDAC_IEN_OPA3OUTVALID_MASK 0x80000000UL /**< Bit mask for VDAC_OPA3OUTVALID */ +#define _VDAC_IEN_OPA3OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA3OUTVALID_DEFAULT (_VDAC_IEN_OPA3OUTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_IEN */ + +/* Bit fields for VDAC CH0DATA */ +#define _VDAC_CH0DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH0DATA */ +#define _VDAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH0DATA */ +#define _VDAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH0DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH0DATA */ +#define VDAC_CH0DATA_DATA_DEFAULT (_VDAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0DATA */ + +/* Bit fields for VDAC CH1DATA */ +#define _VDAC_CH1DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH1DATA */ +#define _VDAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH1DATA */ +#define _VDAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH1DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH1DATA */ +#define VDAC_CH1DATA_DATA_DEFAULT (_VDAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1DATA */ + +/* Bit fields for VDAC COMBDATA */ +#define _VDAC_COMBDATA_RESETVALUE 0x08000800UL /**< Default value for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for VDAC_CH0DATA */ +#define _VDAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for VDAC_CH0DATA */ +#define _VDAC_COMBDATA_CH0DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ +#define VDAC_COMBDATA_CH0DATA_DEFAULT (_VDAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for VDAC_CH1DATA */ +#define _VDAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for VDAC_CH1DATA */ +#define _VDAC_COMBDATA_CH1DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ +#define VDAC_COMBDATA_CH1DATA_DEFAULT (_VDAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ + +/* Bit fields for VDAC CAL */ +#define _VDAC_CAL_RESETVALUE 0x00082004UL /**< Default value for VDAC_CAL */ +#define _VDAC_CAL_MASK 0x000F3F07UL /**< Mask for VDAC_CAL */ +#define _VDAC_CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for VDAC_OFFSETTRIM */ +#define _VDAC_CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for VDAC_OFFSETTRIM */ +#define _VDAC_CAL_OFFSETTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_OFFSETTRIM_DEFAULT (_VDAC_CAL_OFFSETTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CAL */ +#define _VDAC_CAL_GAINERRTRIM_SHIFT 8 /**< Shift value for VDAC_GAINERRTRIM */ +#define _VDAC_CAL_GAINERRTRIM_MASK 0x3F00UL /**< Bit mask for VDAC_GAINERRTRIM */ +#define _VDAC_CAL_GAINERRTRIM_DEFAULT 0x00000020UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_GAINERRTRIM_DEFAULT (_VDAC_CAL_GAINERRTRIM_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CAL */ +#define _VDAC_CAL_GAINERRTRIMCH1_SHIFT 16 /**< Shift value for VDAC_GAINERRTRIMCH1 */ +#define _VDAC_CAL_GAINERRTRIMCH1_MASK 0xF0000UL /**< Bit mask for VDAC_GAINERRTRIMCH1 */ +#define _VDAC_CAL_GAINERRTRIMCH1_DEFAULT 0x00000008UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_GAINERRTRIMCH1_DEFAULT (_VDAC_CAL_GAINERRTRIMCH1_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CAL */ + +/* Bit fields for VDAC OPA_APORTREQ */ +#define _VDAC_OPA_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTREQ */ +#define _VDAC_OPA_APORTREQ_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XREQ */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XREQ */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YREQ */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YREQ */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XREQ */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XREQ */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YREQ */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YREQ */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XREQ */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XREQ */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YREQ */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YREQ */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XREQ */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XREQ */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YREQ */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YREQ */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ + +/* Bit fields for VDAC OPA_APORTCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ + +/* Bit fields for VDAC OPA_CTRL */ +#define _VDAC_OPA_CTRL_RESETVALUE 0x0000000EUL /**< Default value for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_MASK 0x00317F1FUL /**< Mask for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for VDAC_OPADRIVESTRENGTH */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_MASK 0x3UL /**< Bit mask for VDAC_OPADRIVESTRENGTH */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT (_VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_INCBW (0x1UL << 2) /**< OPAx Unity Gain Bandwidth Scale */ +#define _VDAC_OPA_CTRL_INCBW_SHIFT 2 /**< Shift value for VDAC_OPAINCBW */ +#define _VDAC_OPA_CTRL_INCBW_MASK 0x4UL /**< Bit mask for VDAC_OPAINCBW */ +#define _VDAC_OPA_CTRL_INCBW_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_INCBW_DEFAULT (_VDAC_OPA_CTRL_INCBW_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_HCMDIS (0x1UL << 3) /**< High Common Mode Disable */ +#define _VDAC_OPA_CTRL_HCMDIS_SHIFT 3 /**< Shift value for VDAC_OPAHCMDIS */ +#define _VDAC_OPA_CTRL_HCMDIS_MASK 0x8UL /**< Bit mask for VDAC_OPAHCMDIS */ +#define _VDAC_OPA_CTRL_HCMDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_HCMDIS_DEFAULT (_VDAC_OPA_CTRL_HCMDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE (0x1UL << 4) /**< Scale OPAx Output Driving Strength */ +#define _VDAC_OPA_CTRL_OUTSCALE_SHIFT 4 /**< Shift value for VDAC_OPAOUTSCALE */ +#define _VDAC_OPA_CTRL_OUTSCALE_MASK 0x10UL /**< Bit mask for VDAC_OPAOUTSCALE */ +#define _VDAC_OPA_CTRL_OUTSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_OUTSCALE_FULL 0x00000000UL /**< Mode FULL for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_OUTSCALE_HALF 0x00000001UL /**< Mode HALF for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_DEFAULT (_VDAC_OPA_CTRL_OUTSCALE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_FULL (_VDAC_OPA_CTRL_OUTSCALE_FULL << 4) /**< Shifted mode FULL for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_HALF (_VDAC_OPA_CTRL_OUTSCALE_HALF << 4) /**< Shifted mode HALF for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSEN (0x1UL << 8) /**< OPAx PRS Trigger Enable */ +#define _VDAC_OPA_CTRL_PRSEN_SHIFT 8 /**< Shift value for VDAC_OPAPRSEN */ +#define _VDAC_OPA_CTRL_PRSEN_MASK 0x100UL /**< Bit mask for VDAC_OPAPRSEN */ +#define _VDAC_OPA_CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSEN_DEFAULT (_VDAC_OPA_CTRL_PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE (0x1UL << 9) /**< OPAx PRS Trigger Mode */ +#define _VDAC_OPA_CTRL_PRSMODE_SHIFT 9 /**< Shift value for VDAC_OPAPRSMODE */ +#define _VDAC_OPA_CTRL_PRSMODE_MASK 0x200UL /**< Bit mask for VDAC_OPAPRSMODE */ +#define _VDAC_OPA_CTRL_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_DEFAULT (_VDAC_OPA_CTRL_PRSMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_PULSED (_VDAC_OPA_CTRL_PRSMODE_PULSED << 9) /**< Shifted mode PULSED for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_TIMED (_VDAC_OPA_CTRL_PRSMODE_TIMED << 9) /**< Shifted mode TIMED for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_SHIFT 10 /**< Shift value for VDAC_OPAPRSSEL */ +#define _VDAC_OPA_CTRL_PRSSEL_MASK 0x7C00UL /**< Bit mask for VDAC_OPAPRSSEL */ +#define _VDAC_OPA_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_DEFAULT (_VDAC_OPA_CTRL_PRSSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH0 (_VDAC_OPA_CTRL_PRSSEL_PRSCH0 << 10) /**< Shifted mode PRSCH0 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH1 (_VDAC_OPA_CTRL_PRSSEL_PRSCH1 << 10) /**< Shifted mode PRSCH1 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH2 (_VDAC_OPA_CTRL_PRSSEL_PRSCH2 << 10) /**< Shifted mode PRSCH2 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH3 (_VDAC_OPA_CTRL_PRSSEL_PRSCH3 << 10) /**< Shifted mode PRSCH3 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH4 (_VDAC_OPA_CTRL_PRSSEL_PRSCH4 << 10) /**< Shifted mode PRSCH4 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH5 (_VDAC_OPA_CTRL_PRSSEL_PRSCH5 << 10) /**< Shifted mode PRSCH5 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH6 (_VDAC_OPA_CTRL_PRSSEL_PRSCH6 << 10) /**< Shifted mode PRSCH6 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH7 (_VDAC_OPA_CTRL_PRSSEL_PRSCH7 << 10) /**< Shifted mode PRSCH7 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH8 (_VDAC_OPA_CTRL_PRSSEL_PRSCH8 << 10) /**< Shifted mode PRSCH8 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH9 (_VDAC_OPA_CTRL_PRSSEL_PRSCH9 << 10) /**< Shifted mode PRSCH9 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH10 (_VDAC_OPA_CTRL_PRSSEL_PRSCH10 << 10) /**< Shifted mode PRSCH10 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH11 (_VDAC_OPA_CTRL_PRSSEL_PRSCH11 << 10) /**< Shifted mode PRSCH11 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH12 (_VDAC_OPA_CTRL_PRSSEL_PRSCH12 << 10) /**< Shifted mode PRSCH12 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH13 (_VDAC_OPA_CTRL_PRSSEL_PRSCH13 << 10) /**< Shifted mode PRSCH13 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH14 (_VDAC_OPA_CTRL_PRSSEL_PRSCH14 << 10) /**< Shifted mode PRSCH14 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH15 (_VDAC_OPA_CTRL_PRSSEL_PRSCH15 << 10) /**< Shifted mode PRSCH15 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH16 (_VDAC_OPA_CTRL_PRSSEL_PRSCH16 << 10) /**< Shifted mode PRSCH16 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH17 (_VDAC_OPA_CTRL_PRSSEL_PRSCH17 << 10) /**< Shifted mode PRSCH17 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH18 (_VDAC_OPA_CTRL_PRSSEL_PRSCH18 << 10) /**< Shifted mode PRSCH18 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH19 (_VDAC_OPA_CTRL_PRSSEL_PRSCH19 << 10) /**< Shifted mode PRSCH19 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH20 (_VDAC_OPA_CTRL_PRSSEL_PRSCH20 << 10) /**< Shifted mode PRSCH20 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH21 (_VDAC_OPA_CTRL_PRSSEL_PRSCH21 << 10) /**< Shifted mode PRSCH21 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH22 (_VDAC_OPA_CTRL_PRSSEL_PRSCH22 << 10) /**< Shifted mode PRSCH22 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH23 (_VDAC_OPA_CTRL_PRSSEL_PRSCH23 << 10) /**< Shifted mode PRSCH23 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE (0x1UL << 16) /**< OPAx PRS Output Select */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_SHIFT 16 /**< Shift value for VDAC_OPAPRSOUTMODE */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_MASK 0x10000UL /**< Bit mask for VDAC_OPAPRSOUTMODE */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_WARM 0x00000000UL /**< Mode WARM for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID 0x00000001UL /**< Mode OUTVALID for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT (_VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_WARM (_VDAC_OPA_CTRL_PRSOUTMODE_WARM << 16) /**< Shifted mode WARM for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID (_VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID << 16) /**< Shifted mode OUTVALID for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTXMASTERDIS (0x1UL << 20) /**< APORT Bus Master Disable */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_SHIFT 20 /**< Shift value for VDAC_OPAAPORTXMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_MASK 0x100000UL /**< Bit mask for VDAC_OPAAPORTXMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTYMASTERDIS (0x1UL << 21) /**< APORT Bus Master Disable */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_SHIFT 21 /**< Shift value for VDAC_OPAAPORTYMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_MASK 0x200000UL /**< Bit mask for VDAC_OPAAPORTYMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ + +/* Bit fields for VDAC OPA_TIMER */ +#define _VDAC_OPA_TIMER_RESETVALUE 0x00010700UL /**< Default value for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_MASK 0x03FF7F3FUL /**< Mask for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_STARTUPDLY_SHIFT 0 /**< Shift value for VDAC_OPASTARTUPDLY */ +#define _VDAC_OPA_TIMER_STARTUPDLY_MASK 0x3FUL /**< Bit mask for VDAC_OPASTARTUPDLY */ +#define _VDAC_OPA_TIMER_STARTUPDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_STARTUPDLY_DEFAULT (_VDAC_OPA_TIMER_STARTUPDLY_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_WARMUPTIME_SHIFT 8 /**< Shift value for VDAC_OPAWARMUPTIME */ +#define _VDAC_OPA_TIMER_WARMUPTIME_MASK 0x7F00UL /**< Bit mask for VDAC_OPAWARMUPTIME */ +#define _VDAC_OPA_TIMER_WARMUPTIME_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_WARMUPTIME_DEFAULT (_VDAC_OPA_TIMER_WARMUPTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_SETTLETIME_SHIFT 16 /**< Shift value for VDAC_OPASETTLETIME */ +#define _VDAC_OPA_TIMER_SETTLETIME_MASK 0x3FF0000UL /**< Bit mask for VDAC_OPASETTLETIME */ +#define _VDAC_OPA_TIMER_SETTLETIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_SETTLETIME_DEFAULT (_VDAC_OPA_TIMER_SETTLETIME_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ + +/* Bit fields for VDAC OPA_MUX */ +#define _VDAC_OPA_MUX_RESETVALUE 0x0016F2F1UL /**< Default value for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_MASK 0x0717FFFFUL /**< Mask for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_SHIFT 0 /**< Shift value for VDAC_OPAPOSSEL */ +#define _VDAC_OPA_MUX_POSSEL_MASK 0xFFUL /**< Bit mask for VDAC_OPAPOSSEL */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH2 0x00000021UL /**< Mode APORT1XCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH4 0x00000022UL /**< Mode APORT1XCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH6 0x00000023UL /**< Mode APORT1XCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH8 0x00000024UL /**< Mode APORT1XCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH10 0x00000025UL /**< Mode APORT1XCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH12 0x00000026UL /**< Mode APORT1XCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH14 0x00000027UL /**< Mode APORT1XCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH16 0x00000028UL /**< Mode APORT1XCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH18 0x00000029UL /**< Mode APORT1XCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH20 0x0000002AUL /**< Mode APORT1XCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH22 0x0000002BUL /**< Mode APORT1XCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH24 0x0000002CUL /**< Mode APORT1XCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH26 0x0000002DUL /**< Mode APORT1XCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH28 0x0000002EUL /**< Mode APORT1XCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH30 0x0000002FUL /**< Mode APORT1XCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH1 0x00000040UL /**< Mode APORT2XCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH3 0x00000041UL /**< Mode APORT2XCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH5 0x00000042UL /**< Mode APORT2XCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH7 0x00000043UL /**< Mode APORT2XCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH9 0x00000044UL /**< Mode APORT2XCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH11 0x00000045UL /**< Mode APORT2XCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH13 0x00000046UL /**< Mode APORT2XCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH15 0x00000047UL /**< Mode APORT2XCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH17 0x00000048UL /**< Mode APORT2XCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH19 0x00000049UL /**< Mode APORT2XCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH21 0x0000004AUL /**< Mode APORT2XCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH23 0x0000004BUL /**< Mode APORT2XCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH25 0x0000004CUL /**< Mode APORT2XCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH27 0x0000004DUL /**< Mode APORT2XCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH29 0x0000004EUL /**< Mode APORT2XCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH31 0x0000004FUL /**< Mode APORT2XCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH2 0x00000061UL /**< Mode APORT3XCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH4 0x00000062UL /**< Mode APORT3XCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH6 0x00000063UL /**< Mode APORT3XCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH8 0x00000064UL /**< Mode APORT3XCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH10 0x00000065UL /**< Mode APORT3XCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH12 0x00000066UL /**< Mode APORT3XCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH14 0x00000067UL /**< Mode APORT3XCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH16 0x00000068UL /**< Mode APORT3XCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH18 0x00000069UL /**< Mode APORT3XCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH20 0x0000006AUL /**< Mode APORT3XCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH22 0x0000006BUL /**< Mode APORT3XCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH24 0x0000006CUL /**< Mode APORT3XCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH26 0x0000006DUL /**< Mode APORT3XCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH28 0x0000006EUL /**< Mode APORT3XCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH30 0x0000006FUL /**< Mode APORT3XCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH1 0x00000080UL /**< Mode APORT4XCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH3 0x00000081UL /**< Mode APORT4XCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH5 0x00000082UL /**< Mode APORT4XCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH7 0x00000083UL /**< Mode APORT4XCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH9 0x00000084UL /**< Mode APORT4XCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH11 0x00000085UL /**< Mode APORT4XCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH13 0x00000086UL /**< Mode APORT4XCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH15 0x00000087UL /**< Mode APORT4XCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH17 0x00000088UL /**< Mode APORT4XCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH19 0x00000089UL /**< Mode APORT4XCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH21 0x0000008AUL /**< Mode APORT4XCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH23 0x0000008BUL /**< Mode APORT4XCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH25 0x0000008CUL /**< Mode APORT4XCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH27 0x0000008DUL /**< Mode APORT4XCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH29 0x0000008EUL /**< Mode APORT4XCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH31 0x0000008FUL /**< Mode APORT4XCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DEFAULT 0x000000F1UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DAC 0x000000F1UL /**< Mode DAC for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_POSPAD 0x000000F2UL /**< Mode POSPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_OPANEXT 0x000000F3UL /**< Mode OPANEXT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_OPATAP 0x000000F4UL /**< Mode OPATAP for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH0 (_VDAC_OPA_MUX_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH2 (_VDAC_OPA_MUX_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH4 (_VDAC_OPA_MUX_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH6 (_VDAC_OPA_MUX_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH8 (_VDAC_OPA_MUX_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH10 (_VDAC_OPA_MUX_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH12 (_VDAC_OPA_MUX_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH14 (_VDAC_OPA_MUX_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH16 (_VDAC_OPA_MUX_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH18 (_VDAC_OPA_MUX_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH20 (_VDAC_OPA_MUX_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH22 (_VDAC_OPA_MUX_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH24 (_VDAC_OPA_MUX_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH26 (_VDAC_OPA_MUX_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH28 (_VDAC_OPA_MUX_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH30 (_VDAC_OPA_MUX_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH1 (_VDAC_OPA_MUX_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH3 (_VDAC_OPA_MUX_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH5 (_VDAC_OPA_MUX_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH7 (_VDAC_OPA_MUX_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH9 (_VDAC_OPA_MUX_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH11 (_VDAC_OPA_MUX_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH13 (_VDAC_OPA_MUX_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH15 (_VDAC_OPA_MUX_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH17 (_VDAC_OPA_MUX_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH19 (_VDAC_OPA_MUX_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH21 (_VDAC_OPA_MUX_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH23 (_VDAC_OPA_MUX_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH25 (_VDAC_OPA_MUX_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH27 (_VDAC_OPA_MUX_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH29 (_VDAC_OPA_MUX_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH31 (_VDAC_OPA_MUX_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH0 (_VDAC_OPA_MUX_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH2 (_VDAC_OPA_MUX_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH4 (_VDAC_OPA_MUX_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH6 (_VDAC_OPA_MUX_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH8 (_VDAC_OPA_MUX_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH10 (_VDAC_OPA_MUX_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH12 (_VDAC_OPA_MUX_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH14 (_VDAC_OPA_MUX_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH16 (_VDAC_OPA_MUX_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH18 (_VDAC_OPA_MUX_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH20 (_VDAC_OPA_MUX_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH22 (_VDAC_OPA_MUX_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH24 (_VDAC_OPA_MUX_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH26 (_VDAC_OPA_MUX_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH28 (_VDAC_OPA_MUX_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH30 (_VDAC_OPA_MUX_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH1 (_VDAC_OPA_MUX_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH3 (_VDAC_OPA_MUX_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH5 (_VDAC_OPA_MUX_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH7 (_VDAC_OPA_MUX_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH9 (_VDAC_OPA_MUX_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH11 (_VDAC_OPA_MUX_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH13 (_VDAC_OPA_MUX_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH15 (_VDAC_OPA_MUX_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH17 (_VDAC_OPA_MUX_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH19 (_VDAC_OPA_MUX_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH21 (_VDAC_OPA_MUX_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH23 (_VDAC_OPA_MUX_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH25 (_VDAC_OPA_MUX_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH27 (_VDAC_OPA_MUX_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH29 (_VDAC_OPA_MUX_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH31 (_VDAC_OPA_MUX_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DISABLE (_VDAC_OPA_MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DEFAULT (_VDAC_OPA_MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DAC (_VDAC_OPA_MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_POSPAD (_VDAC_OPA_MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_OPANEXT (_VDAC_OPA_MUX_POSSEL_OPANEXT << 0) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_OPATAP (_VDAC_OPA_MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_SHIFT 8 /**< Shift value for VDAC_OPANEGSEL */ +#define _VDAC_OPA_MUX_NEGSEL_MASK 0xFF00UL /**< Bit mask for VDAC_OPANEGSEL */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_UG 0x000000F1UL /**< Mode UG for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_DEFAULT 0x000000F2UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_OPATAP 0x000000F2UL /**< Mode OPATAP for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_NEGPAD 0x000000F3UL /**< Mode NEGPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_DISABLE (_VDAC_OPA_MUX_NEGSEL_DISABLE << 8) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_UG (_VDAC_OPA_MUX_NEGSEL_UG << 8) /**< Shifted mode UG for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_DEFAULT (_VDAC_OPA_MUX_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_OPATAP (_VDAC_OPA_MUX_NEGSEL_OPATAP << 8) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_NEGPAD (_VDAC_OPA_MUX_NEGSEL_NEGPAD << 8) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_SHIFT 16 /**< Shift value for VDAC_OPARESINMUX */ +#define _VDAC_OPA_MUX_RESINMUX_MASK 0x70000UL /**< Bit mask for VDAC_OPARESINMUX */ +#define _VDAC_OPA_MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_OPANEXT 0x00000001UL /**< Mode OPANEXT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_COMPAD 0x00000004UL /**< Mode COMPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_CENTER 0x00000005UL /**< Mode CENTER for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_DEFAULT 0x00000006UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_VSS 0x00000006UL /**< Mode VSS for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_DISABLE (_VDAC_OPA_MUX_RESINMUX_DISABLE << 16) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_OPANEXT (_VDAC_OPA_MUX_RESINMUX_OPANEXT << 16) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_NEGPAD (_VDAC_OPA_MUX_RESINMUX_NEGPAD << 16) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_POSPAD (_VDAC_OPA_MUX_RESINMUX_POSPAD << 16) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_COMPAD (_VDAC_OPA_MUX_RESINMUX_COMPAD << 16) /**< Shifted mode COMPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_CENTER (_VDAC_OPA_MUX_RESINMUX_CENTER << 16) /**< Shifted mode CENTER for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_DEFAULT (_VDAC_OPA_MUX_RESINMUX_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_VSS (_VDAC_OPA_MUX_RESINMUX_VSS << 16) /**< Shifted mode VSS for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_GAIN3X (0x1UL << 20) /**< OPAx Dedicated 3x Gain Resistor Ladder */ +#define _VDAC_OPA_MUX_GAIN3X_SHIFT 20 /**< Shift value for VDAC_OPAGAIN3X */ +#define _VDAC_OPA_MUX_GAIN3X_MASK 0x100000UL /**< Bit mask for VDAC_OPAGAIN3X */ +#define _VDAC_OPA_MUX_GAIN3X_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_GAIN3X_DEFAULT (_VDAC_OPA_MUX_GAIN3X_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_SHIFT 24 /**< Shift value for VDAC_OPARESSEL */ +#define _VDAC_OPA_MUX_RESSEL_MASK 0x7000000UL /**< Bit mask for VDAC_OPARESSEL */ +#define _VDAC_OPA_MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_DEFAULT (_VDAC_OPA_MUX_RESSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES0 (_VDAC_OPA_MUX_RESSEL_RES0 << 24) /**< Shifted mode RES0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES1 (_VDAC_OPA_MUX_RESSEL_RES1 << 24) /**< Shifted mode RES1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES2 (_VDAC_OPA_MUX_RESSEL_RES2 << 24) /**< Shifted mode RES2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES3 (_VDAC_OPA_MUX_RESSEL_RES3 << 24) /**< Shifted mode RES3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES4 (_VDAC_OPA_MUX_RESSEL_RES4 << 24) /**< Shifted mode RES4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES5 (_VDAC_OPA_MUX_RESSEL_RES5 << 24) /**< Shifted mode RES5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES6 (_VDAC_OPA_MUX_RESSEL_RES6 << 24) /**< Shifted mode RES6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES7 (_VDAC_OPA_MUX_RESSEL_RES7 << 24) /**< Shifted mode RES7 for VDAC_OPA_MUX */ + +/* Bit fields for VDAC OPA_OUT */ +#define _VDAC_OPA_OUT_RESETVALUE 0x00000001UL /**< Default value for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_MASK 0x00FF01FFUL /**< Mask for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_MAINOUTEN (0x1UL << 0) /**< OPAx Main Output Enable */ +#define _VDAC_OPA_OUT_MAINOUTEN_SHIFT 0 /**< Shift value for VDAC_OPAMAINOUTEN */ +#define _VDAC_OPA_OUT_MAINOUTEN_MASK 0x1UL /**< Bit mask for VDAC_OPAMAINOUTEN */ +#define _VDAC_OPA_OUT_MAINOUTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_MAINOUTEN_DEFAULT (_VDAC_OPA_OUT_MAINOUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTEN (0x1UL << 1) /**< OPAx Alternative Output Enable */ +#define _VDAC_OPA_OUT_ALTOUTEN_SHIFT 1 /**< Shift value for VDAC_OPAALTOUTEN */ +#define _VDAC_OPA_OUT_ALTOUTEN_MASK 0x2UL /**< Bit mask for VDAC_OPAALTOUTEN */ +#define _VDAC_OPA_OUT_ALTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTEN (0x1UL << 2) /**< OPAx Aport Output Enable */ +#define _VDAC_OPA_OUT_APORTOUTEN_SHIFT 2 /**< Shift value for VDAC_OPAAPORTOUTEN */ +#define _VDAC_OPA_OUT_APORTOUTEN_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORTOUTEN */ +#define _VDAC_OPA_OUT_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTEN_DEFAULT (_VDAC_OPA_OUT_APORTOUTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_SHORT (0x1UL << 3) /**< OPAx Main and Alternative Output Short */ +#define _VDAC_OPA_OUT_SHORT_SHIFT 3 /**< Shift value for VDAC_OPASHORT */ +#define _VDAC_OPA_OUT_SHORT_MASK 0x8UL /**< Bit mask for VDAC_OPASHORT */ +#define _VDAC_OPA_OUT_SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_SHORT_DEFAULT (_VDAC_OPA_OUT_SHORT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_SHIFT 4 /**< Shift value for VDAC_OPAALTOUTPADEN */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_MASK 0x1F0UL /**< Bit mask for VDAC_OPAALTOUTPADEN */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT0 0x00000001UL /**< Mode OUT0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT1 0x00000002UL /**< Mode OUT1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT2 0x00000004UL /**< Mode OUT2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT3 0x00000008UL /**< Mode OUT3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT4 0x00000010UL /**< Mode OUT4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT0 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT0 << 4) /**< Shifted mode OUT0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT1 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT1 << 4) /**< Shifted mode OUT1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT2 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT2 << 4) /**< Shifted mode OUT2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT3 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT3 << 4) /**< Shifted mode OUT3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT4 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT4 << 4) /**< Shifted mode OUT4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_SHIFT 16 /**< Shift value for VDAC_OPAAPORTOUTSEL */ +#define _VDAC_OPA_OUT_APORTOUTSEL_MASK 0xFF0000UL /**< Bit mask for VDAC_OPAAPORTOUTSEL */ +#define _VDAC_OPA_OUT_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_DEFAULT (_VDAC_OPA_OUT_APORTOUTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for VDAC_OPA_OUT */ + +/* Bit fields for VDAC OPA_CAL */ +#define _VDAC_OPA_CAL_RESETVALUE 0x000080E7UL /**< Default value for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_MASK 0x7DF6EDEFUL /**< Mask for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM1_SHIFT 0 /**< Shift value for VDAC_OPACM1 */ +#define _VDAC_OPA_CAL_CM1_MASK 0xFUL /**< Bit mask for VDAC_OPACM1 */ +#define _VDAC_OPA_CAL_CM1_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM1_DEFAULT (_VDAC_OPA_CAL_CM1_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM2_SHIFT 5 /**< Shift value for VDAC_OPACM2 */ +#define _VDAC_OPA_CAL_CM2_MASK 0x1E0UL /**< Bit mask for VDAC_OPACM2 */ +#define _VDAC_OPA_CAL_CM2_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM2_DEFAULT (_VDAC_OPA_CAL_CM2_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM3_SHIFT 10 /**< Shift value for VDAC_OPACM3 */ +#define _VDAC_OPA_CAL_CM3_MASK 0xC00UL /**< Bit mask for VDAC_OPACM3 */ +#define _VDAC_OPA_CAL_CM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM3_DEFAULT (_VDAC_OPA_CAL_CM3_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_GM_SHIFT 13 /**< Shift value for VDAC_OPAGM */ +#define _VDAC_OPA_CAL_GM_MASK 0xE000UL /**< Bit mask for VDAC_OPAGM */ +#define _VDAC_OPA_CAL_GM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_GM_DEFAULT (_VDAC_OPA_CAL_GM_DEFAULT << 13) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_GM3_SHIFT 17 /**< Shift value for VDAC_OPAGM3 */ +#define _VDAC_OPA_CAL_GM3_MASK 0x60000UL /**< Bit mask for VDAC_OPAGM3 */ +#define _VDAC_OPA_CAL_GM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_GM3_DEFAULT (_VDAC_OPA_CAL_GM3_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_OFFSETP_SHIFT 20 /**< Shift value for VDAC_OPAOFFSETP */ +#define _VDAC_OPA_CAL_OFFSETP_MASK 0x1F00000UL /**< Bit mask for VDAC_OPAOFFSETP */ +#define _VDAC_OPA_CAL_OFFSETP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_OFFSETP_DEFAULT (_VDAC_OPA_CAL_OFFSETP_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_OFFSETN_SHIFT 26 /**< Shift value for VDAC_OPAOFFSETN */ +#define _VDAC_OPA_CAL_OFFSETN_MASK 0x7C000000UL /**< Bit mask for VDAC_OPAOFFSETN */ +#define _VDAC_OPA_CAL_OFFSETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_OFFSETN_DEFAULT (_VDAC_OPA_CAL_OFFSETN_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ + +/** @} */ +/** @} End of group EFM32GG11B_VDAC */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_vdac_opa.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_vdac_opa.h new file mode 100644 index 0000000000000..0176bf283f86f --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_vdac_opa.h @@ -0,0 +1,65 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_VDAC_OPA register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief VDAC_OPA VDAC OPA Register + * @ingroup EFM32GG11B_VDAC + ******************************************************************************/ +typedef struct { + __IM uint32_t APORTREQ; /**< Operational Amplifier APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< Operational Amplifier APORT Conflict Status Register */ + __IOM uint32_t CTRL; /**< Operational Amplifier Control Register */ + __IOM uint32_t TIMER; /**< Operational Amplifier Timer Control Register */ + __IOM uint32_t MUX; /**< Operational Amplifier Mux Configuration Register */ + __IOM uint32_t OUT; /**< Operational Amplifier Output Configuration Register */ + __IOM uint32_t CAL; /**< Operational Amplifier Calibration Register */ + uint32_t RESERVED0[1U]; /**< Reserved future */ +} VDAC_OPA_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_wdog.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_wdog.h new file mode 100644 index 0000000000000..9ec1fbe5da44b --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_wdog.h @@ -0,0 +1,375 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_WDOG register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @defgroup EFM32GG11B_WDOG WDOG + * @{ + * @brief EFM32GG11B_WDOG Register Declaration + ******************************************************************************/ +/** WDOG Register Declaration */ +typedef struct { + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + WDOG_PCH_TypeDef PCH[2U]; /**< PCH */ + + uint32_t RESERVED0[2U]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Watchdog Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} WDOG_TypeDef; /** @} */ + +/***************************************************************************//** + * @addtogroup EFM32GG11B_WDOG + * @{ + * @defgroup EFM32GG11B_WDOG_BitFields WDOG Bit Fields + * @{ + ******************************************************************************/ + +/* Bit fields for WDOG CTRL */ +#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */ +#define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */ +#define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */ +#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */ +#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */ +#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration Lock */ +#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */ +#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */ +#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_HFCORECLK 0x00000003UL /**< Mode HFCORECLK for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_HFCORECLK (_WDOG_CTRL_CLKSEL_HFCORECLK << 12) /**< Shifted mode HFCORECLK for WDOG_CTRL */ +#define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */ +#define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */ +#define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */ +#define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */ +#define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/* Bit fields for WDOG PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_MASK 0x0000011FUL /**< Mask for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0x1FUL /**< Bit mask for WDOG_PRSSEL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH12 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH13 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH14 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH15 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH16 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH17 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH18 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH19 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH20 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH21 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH22 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH23 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS Missing Event Will Trigger a Watchdog Reset */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IFS */ +#define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */ +#define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */ +#define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */ +#define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */ +#define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */ +#define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */ +#define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */ +#define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */ + +/* Bit fields for WDOG IFC */ +#define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */ +#define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */ +#define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */ +#define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */ +#define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */ +#define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */ +#define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */ +#define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/** @} */ +/** @} End of group EFM32GG11B_WDOG */ +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_wdog_pch.h b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_wdog_pch.h new file mode 100644 index 0000000000000..8acb2bad6d3b2 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_wdog_pch.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief EFM32GG11B_WDOG_PCH register and bit field definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @brief WDOG_PCH WDOG PCH Register + * @ingroup EFM32GG11B_WDOG + ******************************************************************************/ +typedef struct { + __IOM uint32_t PRSCTRL; /**< PRS Control Register */ +} WDOG_PCH_TypeDef; + +/** @} End of group Parts */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/em_device.h b/cpu/efm32/families/efm32gg11b/include/vendor/em_device.h new file mode 100644 index 0000000000000..3db832ac1fe19 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/em_device.h @@ -0,0 +1,236 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + * @endverbatim + * + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H + +#if defined(EFM32GG11B110F2048GM64) +#include "efm32gg11b110f2048gm64.h" + +#elif defined(EFM32GG11B110F2048GQ64) +#include "efm32gg11b110f2048gq64.h" + +#elif defined(EFM32GG11B110F2048IM64) +#include "efm32gg11b110f2048im64.h" + +#elif defined(EFM32GG11B110F2048IQ64) +#include "efm32gg11b110f2048iq64.h" + +#elif defined(EFM32GG11B120F2048GM64) +#include "efm32gg11b120f2048gm64.h" + +#elif defined(EFM32GG11B120F2048GQ64) +#include "efm32gg11b120f2048gq64.h" + +#elif defined(EFM32GG11B120F2048IM64) +#include "efm32gg11b120f2048im64.h" + +#elif defined(EFM32GG11B120F2048IQ64) +#include "efm32gg11b120f2048iq64.h" + +#elif defined(EFM32GG11B310F2048GL112) +#include "efm32gg11b310f2048gl112.h" + +#elif defined(EFM32GG11B310F2048GQ100) +#include "efm32gg11b310f2048gq100.h" + +#elif defined(EFM32GG11B320F2048GL112) +#include "efm32gg11b320f2048gl112.h" + +#elif defined(EFM32GG11B320F2048GQ100) +#include "efm32gg11b320f2048gq100.h" + +#elif defined(EFM32GG11B420F2048GL112) +#include "efm32gg11b420f2048gl112.h" + +#elif defined(EFM32GG11B420F2048GL120) +#include "efm32gg11b420f2048gl120.h" + +#elif defined(EFM32GG11B420F2048GM64) +#include "efm32gg11b420f2048gm64.h" + +#elif defined(EFM32GG11B420F2048GQ100) +#include "efm32gg11b420f2048gq100.h" + +#elif defined(EFM32GG11B420F2048GQ64) +#include "efm32gg11b420f2048gq64.h" + +#elif defined(EFM32GG11B420F2048IL112) +#include "efm32gg11b420f2048il112.h" + +#elif defined(EFM32GG11B420F2048IL120) +#include "efm32gg11b420f2048il120.h" + +#elif defined(EFM32GG11B420F2048IM64) +#include "efm32gg11b420f2048im64.h" + +#elif defined(EFM32GG11B420F2048IQ100) +#include "efm32gg11b420f2048iq100.h" + +#elif defined(EFM32GG11B420F2048IQ64) +#include "efm32gg11b420f2048iq64.h" + +#elif defined(EFM32GG11B510F2048GL120) +#include "efm32gg11b510f2048gl120.h" + +#elif defined(EFM32GG11B510F2048GM64) +#include "efm32gg11b510f2048gm64.h" + +#elif defined(EFM32GG11B510F2048GQ100) +#include "efm32gg11b510f2048gq100.h" + +#elif defined(EFM32GG11B510F2048GQ64) +#include "efm32gg11b510f2048gq64.h" + +#elif defined(EFM32GG11B510F2048IL120) +#include "efm32gg11b510f2048il120.h" + +#elif defined(EFM32GG11B510F2048IM64) +#include "efm32gg11b510f2048im64.h" + +#elif defined(EFM32GG11B510F2048IQ100) +#include "efm32gg11b510f2048iq100.h" + +#elif defined(EFM32GG11B510F2048IQ64) +#include "efm32gg11b510f2048iq64.h" + +#elif defined(EFM32GG11B520F2048GL120) +#include "efm32gg11b520f2048gl120.h" + +#elif defined(EFM32GG11B520F2048GM64) +#include "efm32gg11b520f2048gm64.h" + +#elif defined(EFM32GG11B520F2048GQ100) +#include "efm32gg11b520f2048gq100.h" + +#elif defined(EFM32GG11B520F2048GQ64) +#include "efm32gg11b520f2048gq64.h" + +#elif defined(EFM32GG11B520F2048IL120) +#include "efm32gg11b520f2048il120.h" + +#elif defined(EFM32GG11B520F2048IM64) +#include "efm32gg11b520f2048im64.h" + +#elif defined(EFM32GG11B520F2048IQ100) +#include "efm32gg11b520f2048iq100.h" + +#elif defined(EFM32GG11B520F2048IQ64) +#include "efm32gg11b520f2048iq64.h" + +#elif defined(EFM32GG11B820F2048GL120) +#include "efm32gg11b820f2048gl120.h" + +#elif defined(EFM32GG11B820F2048GL152) +#include "efm32gg11b820f2048gl152.h" + +#elif defined(EFM32GG11B820F2048GL192) +#include "efm32gg11b820f2048gl192.h" + +#elif defined(EFM32GG11B820F2048GM64) +#include "efm32gg11b820f2048gm64.h" + +#elif defined(EFM32GG11B820F2048GQ100) +#include "efm32gg11b820f2048gq100.h" + +#elif defined(EFM32GG11B820F2048GQ64) +#include "efm32gg11b820f2048gq64.h" + +#elif defined(EFM32GG11B820F2048IL120) +#include "efm32gg11b820f2048il120.h" + +#elif defined(EFM32GG11B820F2048IL152) +#include "efm32gg11b820f2048il152.h" + +#elif defined(EFM32GG11B820F2048IM64) +#include "efm32gg11b820f2048im64.h" + +#elif defined(EFM32GG11B820F2048IQ100) +#include "efm32gg11b820f2048iq100.h" + +#elif defined(EFM32GG11B820F2048IQ64) +#include "efm32gg11b820f2048iq64.h" + +#elif defined(EFM32GG11B840F1024GL120) +#include "efm32gg11b840f1024gl120.h" + +#elif defined(EFM32GG11B840F1024GL152) +#include "efm32gg11b840f1024gl152.h" + +#elif defined(EFM32GG11B840F1024GL192) +#include "efm32gg11b840f1024gl192.h" + +#elif defined(EFM32GG11B840F1024GM64) +#include "efm32gg11b840f1024gm64.h" + +#elif defined(EFM32GG11B840F1024GQ100) +#include "efm32gg11b840f1024gq100.h" + +#elif defined(EFM32GG11B840F1024GQ64) +#include "efm32gg11b840f1024gq64.h" + +#elif defined(EFM32GG11B840F1024IL120) +#include "efm32gg11b840f1024il120.h" + +#elif defined(EFM32GG11B840F1024IL152) +#include "efm32gg11b840f1024il152.h" + +#elif defined(EFM32GG11B840F1024IM64) +#include "efm32gg11b840f1024im64.h" + +#elif defined(EFM32GG11B840F1024IQ100) +#include "efm32gg11b840f1024iq100.h" + +#elif defined(EFM32GG11B840F1024IQ64) +#include "efm32gg11b840f1024iq64.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif +#endif /* EM_DEVICE_H */ +#ifdef __cplusplus +} +#endif + diff --git a/cpu/efm32/families/efm32gg11b/include/vendor/system_efm32gg11b.h b/cpu/efm32/families/efm32gg11b/include/vendor/system_efm32gg11b.h new file mode 100644 index 0000000000000..031f5423f811f --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/include/vendor/system_efm32gg11b.h @@ -0,0 +1,198 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M4 System Layer for EFM32 devices. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SYSTEM_EFM32_H +#define SYSTEM_EFM32_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup EFM32GG11B EFM32GG11B + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/* Interrupt vectortable entry */ +typedef union { + void (*pFunc)(void); + void *topOfStack; +} tVectorEntry; + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ + +#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */ +#define __Vectors __vector_table +#endif +extern const tVectorEntry __Vectors[]; +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); /**< Reset Handler */ +void NMI_Handler(void); /**< NMI Handler */ +void HardFault_Handler(void); /**< Hard Fault Handler */ +void MemManage_Handler(void); /**< MPU Fault Handler */ +void BusFault_Handler(void); /**< Bus Fault Handler */ +void UsageFault_Handler(void); /**< Usage Fault Handler */ +void SVC_Handler(void); /**< SVCall Handler */ +void DebugMon_Handler(void); /**< Debug Monitor Handler */ +void PendSV_Handler(void); /**< PendSV Handler */ +void SysTick_Handler(void); /**< SysTick Handler */ + +void EMU_IRQHandler(void); /**< EMU IRQ Handler */ +void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ +void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ +void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ +void SMU_IRQHandler(void); /**< SMU IRQ Handler */ +void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ +void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ +void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ +void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */ +void ADC0_IRQHandler(void); /**< ADC0 IRQ Handler */ +void IDAC0_IRQHandler(void); /**< IDAC0 IRQ Handler */ +void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ +void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ +void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ +void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ +void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */ +void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */ +void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */ +void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */ +void USART2_RX_IRQHandler(void); /**< USART2_RX IRQ Handler */ +void USART2_TX_IRQHandler(void); /**< USART2_TX IRQ Handler */ +void UART0_RX_IRQHandler(void); /**< UART0_RX IRQ Handler */ +void UART0_TX_IRQHandler(void); /**< UART0_TX IRQ Handler */ +void UART1_RX_IRQHandler(void); /**< UART1_RX IRQ Handler */ +void UART1_TX_IRQHandler(void); /**< UART1_TX IRQ Handler */ +void LEUART0_IRQHandler(void); /**< LEUART0 IRQ Handler */ +void LEUART1_IRQHandler(void); /**< LEUART1 IRQ Handler */ +void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ +void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */ +void PCNT1_IRQHandler(void); /**< PCNT1 IRQ Handler */ +void PCNT2_IRQHandler(void); /**< PCNT2 IRQ Handler */ +void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */ +void CMU_IRQHandler(void); /**< CMU IRQ Handler */ +void MSC_IRQHandler(void); /**< MSC IRQ Handler */ +void CRYPTO0_IRQHandler(void); /**< CRYPTO0 IRQ Handler */ +void CRYOTIMER_IRQHandler(void); /**< CRYOTIMER IRQ Handler */ +void FPUEH_IRQHandler(void); /**< FPUEH IRQ Handler */ +void USART3_RX_IRQHandler(void); /**< USART3_RX IRQ Handler */ +void USART3_TX_IRQHandler(void); /**< USART3_TX IRQ Handler */ +void USART4_RX_IRQHandler(void); /**< USART4_RX IRQ Handler */ +void USART4_TX_IRQHandler(void); /**< USART4_TX IRQ Handler */ +void WTIMER0_IRQHandler(void); /**< WTIMER0 IRQ Handler */ +void WTIMER1_IRQHandler(void); /**< WTIMER1 IRQ Handler */ +void WTIMER2_IRQHandler(void); /**< WTIMER2 IRQ Handler */ +void WTIMER3_IRQHandler(void); /**< WTIMER3 IRQ Handler */ +void I2C2_IRQHandler(void); /**< I2C2 IRQ Handler */ +void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */ +void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */ +void TIMER5_IRQHandler(void); /**< TIMER5 IRQ Handler */ +void TIMER6_IRQHandler(void); /**< TIMER6 IRQ Handler */ +void USART5_RX_IRQHandler(void); /**< USART5_RX IRQ Handler */ +void USART5_TX_IRQHandler(void); /**< USART5_TX IRQ Handler */ +void CSEN_IRQHandler(void); /**< CSEN IRQ Handler */ +void LESENSE_IRQHandler(void); /**< LESENSE IRQ Handler */ +void EBI_IRQHandler(void); /**< EBI IRQ Handler */ +void ACMP2_IRQHandler(void); /**< ACMP2 IRQ Handler */ +void ADC1_IRQHandler(void); /**< ADC1 IRQ Handler */ +void LCD_IRQHandler(void); /**< LCD IRQ Handler */ +void SDIO_IRQHandler(void); /**< SDIO IRQ Handler */ +void ETH_IRQHandler(void); /**< ETH IRQ Handler */ +void CAN0_IRQHandler(void); /**< CAN0 IRQ Handler */ +void CAN1_IRQHandler(void); /**< CAN1 IRQ Handler */ +void USB_IRQHandler(void); /**< USB IRQ Handler */ +void RTC_IRQHandler(void); /**< RTC IRQ Handler */ +void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */ +void LETIMER1_IRQHandler(void); /**< LETIMER1 IRQ Handler */ +void TRNG0_IRQHandler(void); /**< TRNG0 IRQ Handler */ +void QSPI0_IRQHandler(void); /**< QSPI0 IRQ Handler */ + +uint32_t SystemCoreClockGet(void); + +/***************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EFM32 CMU + * API, this variable will be kept updated. This function is only provided + * for CMSIS compliance and if a user modifies the the core clock outside + * the CMU API. + ******************************************************************************/ +static __INLINE void SystemCoreClockUpdate(void) +{ + (void)SystemCoreClockGet(); +} + +uint32_t SystemMaxCoreClockGet(void); + +void SystemInit(void); +uint32_t SystemHFClockGet(void); + +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); + +uint32_t SystemLFRCOClockGet(void); +uint32_t SystemULFRCOClockGet(void); + +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); + +/** @} End of group */ +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_EFM32_H */ diff --git a/cpu/efm32/families/efm32gg11b/system.c b/cpu/efm32/families/efm32gg11b/system.c new file mode 100644 index 0000000000000..908c8ab7d0e26 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/system.c @@ -0,0 +1,410 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M4 System Layer for EFM32 devices. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "periph_conf.h" +#include "em_device.h" + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** LFRCO frequency, tuned to below frequency during manufacturing. */ +#define EFM32_LFRCO_FREQ (32768UL) +/** ULFRCO frequency */ +#define EFM32_ULFRCO_FREQ (1000UL) + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +/* System oscillator frequencies. These frequencies are normally constant */ +/* for a target, but they are made configurable in order to allow run-time */ +/* handling of different boards. The crystal oscillator clocks can be set */ +/* compile time to a non-default value by defining respective EFM32_nFXO_FREQ */ +/* values according to board design. By defining the EFM32_nFXO_FREQ to 0, */ +/* one indicates that the oscillator is not present, in order to save some */ +/* SW footprint. */ + +#ifndef EFM32_HFRCO_MAX_FREQ +/** Maximum HFRCO frequency */ +#define EFM32_HFRCO_MAX_FREQ (72000000UL) +#endif + +#ifndef EFM32_HFXO_FREQ +/** HFXO frequency */ +#define EFM32_HFXO_FREQ (50000000UL) +#endif + +#ifndef EFM32_HFRCO_STARTUP_FREQ +/** HFRCO startup frequency */ +#define EFM32_HFRCO_STARTUP_FREQ (19000000UL) +#endif + +/* Do not define variable if HF crystal oscillator not present */ +#if (EFM32_HFXO_FREQ > 0U) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System HFXO clock. */ +static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + +#ifndef EFM32_LFXO_FREQ +/** LFXO frequency */ +#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ) +#endif +/* Do not define variable if LF crystal oscillator not present */ +#if (EFM32_LFXO_FREQ > 0U) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System LFXO clock. */ +static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock = EFM32_HFRCO_STARTUP_FREQ; + +/** + * @brief + * System HFRCO frequency + * + * @note + * This is an EFM32 proprietary variable, not part of the CMSIS definition. + * + * @details + * Frequency of the system HFRCO oscillator + */ +uint32_t SystemHfrcoFreq = EFM32_HFRCO_STARTUP_FREQ; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the current core clock frequency. + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemCoreClockGet(void) +{ + uint32_t ret; + uint32_t presc; + + ret = SystemHFClockGet(); + presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) + >> _CMU_HFCOREPRESC_PRESC_SHIFT; + ret /= presc + 1U; + + /* Keep CMSIS system clock variable up-to-date */ + SystemCoreClock = ret; + + return ret; +} + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ +#if (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ) + return EFM32_HFRCO_MAX_FREQ; +#else + return EFM32_HFXO_FREQ; +#endif +} + +/***************************************************************************//** + * @brief + * Get the current HFCLK frequency. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current HFCLK frequency in Hz. + ******************************************************************************/ +uint32_t SystemHFClockGet(void) +{ + uint32_t ret; + + switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) { + case CMU_HFCLKSTATUS_SELECTED_LFXO: +#if (EFM32_LFXO_FREQ > 0U) + ret = SystemLFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0U; +#endif + break; + + case CMU_HFCLKSTATUS_SELECTED_LFRCO: + ret = EFM32_LFRCO_FREQ; + break; + + case CMU_HFCLKSTATUS_SELECTED_HFXO: +#if (EFM32_HFXO_FREQ > 0U) + ret = SystemHFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0U; +#endif + break; + + case CMU_HFCLKSTATUS_SELECTED_USHFRCO: + switch ((CMU->USHFRCOCTRL & _CMU_USHFRCOCTRL_FREQRANGE_MASK) + >> _CMU_USHFRCOCTRL_FREQRANGE_SHIFT) { + case 7: + ret = 16000000U; + break; + case 11: + ret = 32000000U; + break; + case 13: + ret = 48000000U; + break; + case 14: + ret = 50000000U; + break; + default: + ret = 0U; + break; + } + break; + + case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2: + ret = SystemHfrcoFreq / 2; + break; + + default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */ + ret = SystemHfrcoFreq; + break; + } + + return ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT)); +} + +/***************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * HFXO frequency in Hz. + ******************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFM32_HFXO_FREQ > 0U) + return SystemHFXOClock; +#else + return 0U; +#endif +} + +/***************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + ******************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFM32_HFXO_FREQ > 0U) + SystemHFXOClock = freq; + + /* Update core clock frequency if HFXO is used to clock core */ + if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) + == CMU_HFCLKSTATUS_SELECTED_HFXO) { + /* The function will update the global variable */ + (void)SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} + +/***************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + ******************************************************************************/ +void SystemInit(void) +{ +#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)&__Vectors; +#endif + +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Set floating point coprosessor access mode. */ + SCB->CPACR |= ((3UL << 10 * 2) /* set CP10 Full Access */ + | (3UL << 11 * 2)); /* set CP11 Full Access */ +#endif + +#if defined(UNALIGNED_SUPPORT_DISABLE) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif +} + +/***************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + ******************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + /* Currently we assume that this frequency is properly tuned during */ + /* manufacturing and is not changed after reset. If future requirements */ + /* for re-tuning by user, we can add support for that. */ + return EFM32_LFRCO_FREQ; +} + +/***************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + ******************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + /* The ULFRCO frequency is not tuned, and can be very inaccurate */ + return EFM32_ULFRCO_FREQ; +} + +/***************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * LFXO frequency in Hz. + ******************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFM32_LFXO_FREQ > 0U) + return SystemLFXOClock; +#else + return 0U; +#endif +} + +/***************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + ******************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFM32_LFXO_FREQ > 0U) + SystemLFXOClock = freq; + + /* Update core clock frequency if LFXO is used to clock core */ + if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) + == CMU_HFCLKSTATUS_SELECTED_LFXO) { + /* The function will update the global variable */ + (void)SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} diff --git a/cpu/efm32/families/efm32gg11b/vectors.c b/cpu/efm32/families/efm32gg11b/vectors.c new file mode 100644 index 0000000000000..cfe1de3061a17 --- /dev/null +++ b/cpu/efm32/families/efm32gg11b/vectors.c @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2015-2018 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_efm32gg11b + * @{ + * + * @file + * @brief Startup code and interrupt vector definition + * + * @author Hauke Petersen + * @author Bas Stottelaar + * + * @} + */ + +#include "vectors_cortexm.h" + +/* define a local dummy handler as it needs to be in the same compilation unit + * as the alias definition */ +void dummy_handler(void) +{ + dummy_handler_default(); +} + +/* Silicon Labs specific interrupt vector */ +WEAK_DEFAULT void isr_emu(void); +WEAK_DEFAULT void isr_wdog0(void); +WEAK_DEFAULT void isr_ldma(void); +WEAK_DEFAULT void isr_gpio_even(void); +WEAK_DEFAULT void isr_smu(void); +WEAK_DEFAULT void isr_timer0(void); +WEAK_DEFAULT void isr_usart0_rx(void); +WEAK_DEFAULT void isr_usart0_tx(void); +WEAK_DEFAULT void isr_acmp0(void); +WEAK_DEFAULT void isr_adc0(void); +WEAK_DEFAULT void isr_idac0(void); +WEAK_DEFAULT void isr_i2c0(void); +WEAK_DEFAULT void isr_i2c1(void); +WEAK_DEFAULT void isr_gpio_odd(void); +WEAK_DEFAULT void isr_timer1(void); +WEAK_DEFAULT void isr_timer2(void); +WEAK_DEFAULT void isr_timer3(void); +WEAK_DEFAULT void isr_usart1_rx(void); +WEAK_DEFAULT void isr_usart1_tx(void); +WEAK_DEFAULT void isr_usart2_rx(void); +WEAK_DEFAULT void isr_usart2_tx(void); +WEAK_DEFAULT void isr_uart0_rx(void); +WEAK_DEFAULT void isr_uart0_tx(void); +WEAK_DEFAULT void isr_uart1_rx(void); +WEAK_DEFAULT void isr_uart1_tx(void); +WEAK_DEFAULT void isr_leuart0(void); +WEAK_DEFAULT void isr_leuart1(void); +WEAK_DEFAULT void isr_letimer0(void); +WEAK_DEFAULT void isr_pcnt0(void); +WEAK_DEFAULT void isr_pcnt1(void); +WEAK_DEFAULT void isr_pcnt2(void); +WEAK_DEFAULT void isr_rtcc(void); +WEAK_DEFAULT void isr_cmu(void); +WEAK_DEFAULT void isr_msc(void); +WEAK_DEFAULT void isr_crypto0(void); +WEAK_DEFAULT void isr_cryotimer(void); +WEAK_DEFAULT void isr_fpueh(void); +WEAK_DEFAULT void isr_usart3_rx(void); +WEAK_DEFAULT void isr_usart3_tx(void); +WEAK_DEFAULT void isr_usart4_rx(void); +WEAK_DEFAULT void isr_usart4_tx(void); +WEAK_DEFAULT void isr_wtimer0(void); +WEAK_DEFAULT void isr_wtimer1(void); +WEAK_DEFAULT void isr_wtimer2(void); +WEAK_DEFAULT void isr_wtimer3(void); +WEAK_DEFAULT void isr_i2c2(void); +WEAK_DEFAULT void isr_vdac0(void); +WEAK_DEFAULT void isr_timer4(void); +WEAK_DEFAULT void isr_timer5(void); +WEAK_DEFAULT void isr_timer6(void); +WEAK_DEFAULT void isr_usart5_rx(void); +WEAK_DEFAULT void isr_usart5_tx(void); +WEAK_DEFAULT void isr_csen(void); +WEAK_DEFAULT void isr_lesense(void); +WEAK_DEFAULT void isr_ebi(void); +WEAK_DEFAULT void isr_acmp2(void); +WEAK_DEFAULT void isr_adc1(void); +WEAK_DEFAULT void isr_lcd(void); +WEAK_DEFAULT void isr_sdio(void); +WEAK_DEFAULT void isr_eth(void); +WEAK_DEFAULT void isr_can0(void); +WEAK_DEFAULT void isr_can1(void); +WEAK_DEFAULT void isr_usb(void); +WEAK_DEFAULT void isr_rtc(void); +WEAK_DEFAULT void isr_wdog1(void); +WEAK_DEFAULT void isr_letimer1(void); +WEAK_DEFAULT void isr_trng0(void); +WEAK_DEFAULT void isr_qspi0(void); + +/* interrupt vector table */ +ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { + [ 0] = isr_emu, /* EMU */ + [ 1] = isr_wdog0, /* WDOG0 */ + [ 2] = isr_ldma, /* LDMA */ + [ 3] = isr_gpio_even, /* GPIO_EVEN */ + [ 4] = isr_smu, /* SMU */ + [ 5] = isr_timer0, /* TIMER0 */ + [ 6] = isr_usart0_rx, /* USART0_RX */ + [ 7] = isr_usart0_tx, /* USART0_TX */ + [ 8] = isr_acmp0, /* ACMP0 */ + [ 9] = isr_adc0, /* ADC0 */ + [10] = isr_idac0, /* IDAC0 */ + [11] = isr_i2c0, /* I2C0 */ + [12] = isr_i2c1, /* I2C1 */ + [13] = isr_gpio_odd, /* GPIO_ODD */ + [14] = isr_timer1, /* TIMER1 */ + [15] = isr_timer2, /* TIMER2 */ + [16] = isr_timer3, /* TIMER3 */ + [17] = isr_usart1_rx, /* USART1_RX */ + [18] = isr_usart1_tx, /* USART1_TX */ + [19] = isr_usart2_rx, /* USART2_RX */ + [20] = isr_usart2_tx, /* USART2_TX */ + [21] = isr_uart0_rx, /* UART0_RX */ + [22] = isr_uart0_tx, /* UART0_TX */ + [23] = isr_uart1_rx, /* UART1_RX */ + [24] = isr_uart1_tx, /* UART1_TX */ + [25] = isr_leuart0, /* LEUART0 */ + [26] = isr_leuart1, /* LEUART1 */ + [27] = isr_letimer0, /* LETIMER0 */ + [28] = isr_pcnt0, /* PCNT0 */ + [29] = isr_pcnt1, /* PCNT1 */ + [30] = isr_pcnt2, /* PCNT2 */ + [31] = isr_rtcc, /* RTCC */ + [32] = isr_cmu, /* CMU */ + [33] = isr_msc, /* MSC */ + [34] = isr_crypto0, /* CRYPTO0 */ + [35] = isr_cryotimer, /* CRYOTIMER */ + [36] = isr_fpueh, /* FPUEH */ + [37] = isr_usart3_rx, /* USART3_RX */ + [38] = isr_usart3_tx, /* USART3_TX */ + [39] = isr_usart4_rx, /* USART4_RX */ + [40] = isr_usart4_tx, /* USART4_TX */ + [41] = isr_wtimer0, /* WTIMER0 */ + [42] = isr_wtimer1, /* WTIMER1 */ + [43] = isr_wtimer2, /* WTIMER2 */ + [44] = isr_wtimer3, /* WTIMER3 */ + [45] = isr_i2c2, /* I2C2 */ + [46] = isr_vdac0, /* VDAC0 */ + [47] = isr_timer4, /* TIMER4 */ + [48] = isr_timer5, /* TIMER5 */ + [49] = isr_timer6, /* TIMER6 */ + [50] = isr_usart5_rx, /* USART5_RX */ + [51] = isr_usart5_tx, /* USART5_TX */ + [52] = isr_csen, /* CSEN */ + [53] = isr_lesense, /* LESENSE */ + [54] = isr_ebi, /* EBI */ + [55] = isr_acmp2, /* ACMP2 */ + [56] = isr_adc1, /* ADC1 */ + [57] = isr_lcd, /* LCD */ + [58] = isr_sdio, /* SDIO */ + [59] = isr_eth, /* ETH */ + [60] = isr_can0, /* CAN0 */ + [61] = isr_can1, /* CAN1 */ + [62] = isr_usb, /* USB */ + [63] = isr_rtc, /* RTC */ + [64] = isr_wdog1, /* WDOG1 */ + [65] = isr_letimer1, /* LETIMER1 */ + [66] = isr_trng0, /* TRNG0 */ + [67] = isr_qspi0, /* QSPI0 */ +}; From e0b70c628038f2d31abce75d3dc901b1b02551a8 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Tue, 15 Aug 2023 01:05:55 +0200 Subject: [PATCH 2/4] cpu/efm32: add EFM32GG11 family --- cpu/efm32/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/cpu/efm32/Makefile b/cpu/efm32/Makefile index 2d32d036899c9..1441d4ad3d3c7 100644 --- a/cpu/efm32/Makefile +++ b/cpu/efm32/Makefile @@ -7,6 +7,9 @@ DIRS += $(RIOTCPU)/cortexm_common ifneq (,$(filter cpu_efm32gg,$(USEMODULE))) DIRS += families/efm32gg endif +ifneq (,$(filter cpu_efm32gg11b,$(USEMODULE))) + DIRS += families/efm32gg11b +endif ifneq (,$(filter cpu_efm32gg12b,$(USEMODULE))) DIRS += families/efm32gg12b endif From 8c057c20f0af92183b72ce44b13533114ac69c72 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Tue, 15 Aug 2023 16:13:01 +0200 Subject: [PATCH 3/4] drivers/usdev_synopsys_dwc2: enable EFM32GG11B support --- drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c b/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c index de9ad72d4273b..ec194667170fc 100644 --- a/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c +++ b/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c @@ -667,13 +667,13 @@ static void _wake_periph(const dwc2_usb_otg_fshs_config_t *conf) #elif defined(MCU_EFM32) pm_block(EFM32_PM_MODE_EM2); /* switch USB core clock source either to USHFRCO or HFCLK */ -#if defined(CPU_FAM_EFM32GG12B) +#if defined(CPU_FAM_EFM32GG12B) || defined(CPU_FAM_EFM32GG11B) CMU_ClockSelectSet(cmuClock_USB, cmuSelect_USHFRCO); #elif defined(CPU_FAM_EFM32GG) || defined(CPU_FAM_EFM32LG) CMU_ClockSelectSet(cmuClock_USB, cmuSelect_HFCLK); #else #error "EFM32 family not yet supported" -#endif /* defined(CPU_FAM_EFM32GG12B) */ +#endif /* defined(CPU_FAM_EFM32GG12B) || defined(CPU_FAM_EFM32GG11B) */ #elif defined(MCU_ESP32) pm_block(ESP_PM_LIGHT_SLEEP); #elif defined(MCU_GD32V) @@ -784,7 +784,7 @@ static void _usbdev_init(usbdev_t *dev) pm_block(EFM32_PM_MODE_EM3); pm_block(EFM32_PM_MODE_EM2); -#if defined(CPU_FAM_EFM32GG12B) +#if defined(CPU_FAM_EFM32GG12B) || defined(CPU_FAM_EFM32GG11B) /* select USHFRCO as USB clock and set the tuning to 48 MHz */ CMU_ClockSelectSet(cmuClock_USB, cmuSelect_USHFRCO); CMU_USHFRCOBandSet(cmuUSHFRCOFreq_48M0Hz); From 80e99dc4b1af3a740eda1c0c937f9105fe6a07a7 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Tue, 15 Aug 2023 16:38:37 +0200 Subject: [PATCH 4/4] boards/slstk3701a: add Silabs EFM32 Giant Gecko GG11 Starter Kit --- boards/slstk3701a/Kconfig | 32 +++ boards/slstk3701a/Makefile | 5 + boards/slstk3701a/Makefile.dep | 13 ++ boards/slstk3701a/Makefile.features | 16 ++ boards/slstk3701a/Makefile.include | 12 + boards/slstk3701a/board.c | 31 +++ boards/slstk3701a/doc.txt | 288 ++++++++++++++++++++++++ boards/slstk3701a/include/board.h | 129 +++++++++++ boards/slstk3701a/include/gpio_params.h | 63 ++++++ boards/slstk3701a/include/periph_conf.h | 265 ++++++++++++++++++++++ 10 files changed, 854 insertions(+) create mode 100644 boards/slstk3701a/Kconfig create mode 100644 boards/slstk3701a/Makefile create mode 100644 boards/slstk3701a/Makefile.dep create mode 100644 boards/slstk3701a/Makefile.features create mode 100644 boards/slstk3701a/Makefile.include create mode 100644 boards/slstk3701a/board.c create mode 100644 boards/slstk3701a/doc.txt create mode 100644 boards/slstk3701a/include/board.h create mode 100644 boards/slstk3701a/include/gpio_params.h create mode 100644 boards/slstk3701a/include/periph_conf.h diff --git a/boards/slstk3701a/Kconfig b/boards/slstk3701a/Kconfig new file mode 100644 index 0000000000000..dcbd19a447c00 --- /dev/null +++ b/boards/slstk3701a/Kconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2020 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. + +config BOARD + default "slstk3701a" if BOARD_SLSTK3701A + +config BOARD_SLSTK3701A + bool + default y + select BOARD_COMMON_SILABS + select CPU_MODEL_EFM32GG11B820F2048GL192 + select HAS_PERIPH_ADC + select HAS_PERIPH_DAC + select HAS_PERIPH_I2C + select HAS_PERIPH_RTC + select HAS_PERIPH_RTT + select HAS_PERIPH_SPI + select HAS_PERIPH_TIMER + select HAS_PERIPH_UART + select HAS_PERIPH_UART_MODECFG + select HAS_PERIPH_USBDEV + + select HAVE_SAUL_GPIO + select HAVE_SI7021 + + select MODULE_SILABS_AEM if TEST_KCONFIG + select MODULE_SILABS_BC if TEST_KCONFIG + +source "$(RIOTBOARD)/common/silabs/Kconfig" diff --git a/boards/slstk3701a/Makefile b/boards/slstk3701a/Makefile new file mode 100644 index 0000000000000..39108f4589a7c --- /dev/null +++ b/boards/slstk3701a/Makefile @@ -0,0 +1,5 @@ +MODULE = board + +DIRS = $(RIOTBOARD)/common/silabs + +include $(RIOTBASE)/Makefile.base diff --git a/boards/slstk3701a/Makefile.dep b/boards/slstk3701a/Makefile.dep new file mode 100644 index 0000000000000..1208c3a05efd9 --- /dev/null +++ b/boards/slstk3701a/Makefile.dep @@ -0,0 +1,13 @@ +ifneq (,$(filter saul_default,$(USEMODULE))) + USEMODULE += efm32_coretemp + USEMODULE += saul_gpio + USEMODULE += si7021 +endif + +# add board common drivers +USEMODULE += boards_common_silabs +USEMODULE += silabs_aem +USEMODULE += silabs_bc + +# include board common dependencies +include $(RIOTBOARD)/common/silabs/Makefile.dep diff --git a/boards/slstk3701a/Makefile.features b/boards/slstk3701a/Makefile.features new file mode 100644 index 0000000000000..b4827287fcb6e --- /dev/null +++ b/boards/slstk3701a/Makefile.features @@ -0,0 +1,16 @@ +CPU = efm32 +CPU_FAM = efm32gg11b +CPU_MODEL = efm32gg11b820f2048gl192 + +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_dac +FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_rtc +FEATURES_PROVIDED += periph_rtt +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart periph_uart_modecfg +FEATURES_PROVIDED += periph_usbdev + +include $(RIOTBOARD)/common/silabs/Makefile.features diff --git a/boards/slstk3701a/Makefile.include b/boards/slstk3701a/Makefile.include new file mode 100644 index 0000000000000..52633b1c80a74 --- /dev/null +++ b/boards/slstk3701a/Makefile.include @@ -0,0 +1,12 @@ +# set default port depending on operating system +PORT_LINUX ?= /dev/ttyACM0 +PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*))) + +# setup serial terminal +include $(RIOTMAKE)/tools/serial.inc.mk + +# setup JLink for flashing +JLINK_PRE_FLASH = r + +# include board common +include $(RIOTBOARD)/common/silabs/Makefile.include diff --git a/boards/slstk3701a/board.c b/boards/slstk3701a/board.c new file mode 100644 index 0000000000000..a5ff45751fdee --- /dev/null +++ b/boards/slstk3701a/board.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2015-2020 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_slstk3701a + * @{ + * + * @file + * @brief Board specific implementations SLSTK3701A board + * + * @author Hauke Petersen + * @author Bas Stottelaar + * + * @} + */ + +#include "board.h" +#include "board_common.h" + +void board_init(void) +{ +#ifndef RIOTBOOT + /* perform common board initialization */ + board_common_init(); +#endif +} diff --git a/boards/slstk3701a/doc.txt b/boards/slstk3701a/doc.txt new file mode 100644 index 0000000000000..5535d3c6eb86b --- /dev/null +++ b/boards/slstk3701a/doc.txt @@ -0,0 +1,288 @@ +/** + * @defgroup boards_slstk3701a Silicon Labs SLSTK3701A starter kit + * @ingroup boards + * @brief Support for Silicon Labs SLSTK3701A starter kit + +## Overview + +Silicon Labs EFM32 Giant Gecko GG11 Starter Kit is equipped with the EFM32 microcontroller. +It is specifically designed for low-power applications, having energy-saving +peripherals, different energy modes and short wake-up times. + +The starter kit is equipped with an Advanced Energy Monitor. This allows you to +actively measure the power consumption of your hardware and code, in real-time. + +## Hardware + +### MCU + +| MCU | EFM32GG11B820F2048GL192 | +|-----------------|------------------------------------------------------| +| Family | ARM Cortex-M4F | +| Vendor | Silicon Labs | +| Vendor Family | EFM32 Giant Gecko 11B | +| RAM | 512.0 KiB | +| Flash | 2048.0 KiB | +| EEPROM | no | +| Frequency | up to 50 MHz | +| FPU | yes | +| MPU | yes | +| DMA | 24 channels | +| Timers | 4 x 32-bit + 7 x 16-bit + 1 x 16-bit (low power) | +| ADCs | 2 x 12-bit ADC (1 Msample/s) | +| DACs | 2 x 12-bit VDAC (500 ksamples/s), 1 x IDAC | +| I2Cs | 3 x | +| SPIs | 4 x USART | +| UARTs | 4 x USART, 1 x LEUART | +| USB | 1 x Low Energy Full-Speed USB 2.0 | +| Ethernet | Ethernet MAC 10/100 Mbps | +| Vcc | 1.85 V - 3.8 V | +| Datasheet | [Datasheet](https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf) | +| Manual | [Manual](https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf) | +| Board Manual | [Board Manual](https://www.silabs.com/documents/public/user-guides/ug287-stk3701.pdf) | +| Board Schematic | Can be downloaded using Silicon Labs' Simplicity Studio | + +### Pinout + +This is the pinout of the expansion header on the right side of the board. +PIN 1 is the bottom-left contact when the header faces you horizontally. + +| RIOT Peripheral | Name | PIN | PIN | Name | RIOT Peripheral | +|-----------------|------|-----|-----|--------|-----------------| +| | 3V3 | 20 | 19 | ID SDA | | +| | 5V | 18 | 17 | ID SCL | | +| I2C_DEV(0):SDA | PC0 | 16 | 15 | PC1 | I2C_DEV(0):SCL | +| UART_DEV(1):RX | PE9 | 14 | 13 | PB9 | | +| UART_DEV(1):TX | PE8 | 12 | 11 | PB11 | DAC_LINE(0) | +| | PE13 | 10 | 9 | PC5 | I2C_DEV(1):SCL | +| SPI_DEV(0):CLK | PE12 | 8 | 7 | PC4 | I2C_DEV(1):SDA | +| SPI_DEV(0):MISO | PE11 | 6 | 5 | PA13 | | +| SPI_DEV(0):MOSI | PE10 | 4 | 3 | PA12 | | +| | VMCU | 2 | 1 | GND | | + +**Note**: not all starter kits by Silicon Labs share the same pinout! + +**Note:** some pins are connected to the board controller, when enabled! + +### Peripheral mapping + +| Peripheral | Number | Hardware | Pins | Comments | +|-------------|---------|------------|------------------|-------------------------------------| +| ADC | 0 | ADC0:CH0 | | Internal temperature | +| ADC | 1 | ADC0:CH1 | | AVDD | +| DAC | 0 | DAC0:OUT0 | PB11 | AVVD as reference voltage | +| I2C | 0 | I2C0 | SDA:PC0, SCL:PC1 | Normal speed | +| I2C | 1 | I2C1 | SDA:PC7, SCL:PC5 | Normal speed | +| I2C | 2 | I2C2 | SDA:PI4, SCL:PI5 | Normal speed, Sensor I2C bus | +| HWCRYPTO | - | - | | AES128/AES256, SHA1, SHA224/SHA256 | +| HWRNG | - | TNRG0 | | True Random Number Generator (TRNG) | +| RTT | - | RTCC | | 1 Hz interval, either RTT or RTC | +| RTC | - | RTCC | | 1 Hz interval, either RTT or RTC | +| SPI | 0 | USART0 | MOSI:PE10, MISO:PE11, CLK:PE12 | | +| Timer | 0 | WTIMER0 + WTIMER1 | | WTIMER0 is used as prescaler | +| Timer | 1 | TIMER0 + TIMER1 | | TIMER0 is used as prescaler | +| Timer | 2 | LETIMER0 | | | +| UART | 0 | USART4 | RX:PH5, TX:PH4 | Default STDIO | +| UART | 1 | USART5 | RX:PE9, TX:PE8 | | + +### User interface + +| Peripheral | Mapped to | Pin | Comments | +|------------|-----------|-----------|------------| +| Button | PB0_PIN | PC8 | | +| | PB1_PIN | PC9 | | +| LED | LED0R_PIN | PH10 | | +| | LED0G_PIN | PH11 | | +| | LED0B_PIN | PH12 | | +| | LED1R_PIN | PH13 | | +| | LED1G_PIN | PH14 | | +| | LED1B_PIN | PH15 | | +| | LED0_PIN | LED0R_PIN | | +| | LED1_PIN | LED1R_PIN | | + +## Implementation Status + +| Device | ID | Supported | Comments | +|------------------|------------|-----------|----------------------------------------------------| +| MCU | EFM32GG11B | yes | Power modes supported | +| Low-level driver | ADC | yes | | +| | DAC | yes | VDAC, IDAC is not supported | +| | Ethernet | no | | +| | Flash | yes | | +| | GPIO | yes | Interrupts are shared across pins (see ref manual) | +| | HW Crypto | yes | | +| | I2C | yes | | +| | PWM | yes | | +| | RTCC | yes | As RTT or RTC | +| | SPI | yes | Only master mode | +| | Timer | yes | | +| | TRNG | yes | True Random Number Generator | +| | UART | yes | USART is shared with SPI. LEUART baud rate limited | +| | USB | yes | Device mode | + +## Board configuration + +### Board controller + +The starter kit is equipped with a Board Controller. This controller provides a +virtual serial port. The board controller is enabled via a GPIO pin. + +By default, this pin is enabled. You can disable the board controller module by +passing `DISABLE_MODULE=silabs_bc` to the `make` command. + +**Note:** to use the virtual serial port, ensure you have the latest board +controller firmware installed. + +**Note:** the board controller *always* configures the virtual serial port at +115200 baud with 8 bits, no parity and one stop bit. This also means that it +expects data from the MCU with the same settings. + +### Advanced Energy Monitor + +This development kit has an Advanced Energy Monitor. It can be connected to the +Simplicity Studio development software. + +This development kit can measure energy consumption and correlate this with the +code. It allows you to measure energy consumption on code-level. + +The board controller is responsible for measuring energy consumption. For +real-time code correlation, the CoreDebug peripheral will be configured to +output MCU register data and interrupt data via the SWO port. + +By default, this feature is enabled. It can be disabled by passing +`DISABLE_MODULE=silabs_aem` to the `make` command. + +Note that Simplicity Studio requires debug symbols to correlate code. RIOT-OS +defaults to GDB debug symbols, but Simplicity Studio requires DWARF-2 debug +symbols (`-gdwarf-2` for GCC). + +### Clock selection + +There are several clock sources that are available for the different +peripherals. You are advised to read [AN0004.0] +(https://www.silabs.com/documents/public/application-notes/an0004.0-efm32-cmu.pdf) +to get familiar with the different clocks. + +| Source | Internal | Speed | Comments | +|--------|----------|------------|------------------------------------| +| HFRCO | Yes | 19 MHz | Enabled during startup, changeable | +| HFXO | No | 50 MHz | | +| LFRCO | Yes | 32.768 kHz | | +| LFXO | No | 32.768 kHz | | +| ULFRCO | No | 1 kHz | Not very reliable as a time source | + +The sources can be used to clock following branches: + +| Branch | Sources | Comments | +|--------|-------------------------|------------------------------| +| HF | HFRCO, HFXO | Core, peripherals | +| LFA | LFRCO, LFXO | Low-power timers | +| LFB | LFRCO, LFXO, CORELEDIV2 | Low-power UART | +| LFE | LFRCO, LFXO | Real-time Clock and Calendar | + +CORELEDIV2 is a source that depends on the clock source that powers the core. +It is divided by 2 or 4 to not exceed maximum clock frequencies (EMLIB takes +care of this). + +The frequencies mentioned in the tables above are specific for this starter +kit. + +It is important that the clock speeds are known to the code, for proper +calculations of speeds and baud rates. If the HFXO or LFXO are different from +the speeds above, ensure to pass `EFM32_HFXO_FREQ=freq_in_hz` and +`EFM32_LFXO_FREQ=freq_in_hz` to your compiler. + +You can override the branch's clock source by adding `CLOCK_LFA=source` to your +compiler defines, e.g. `CLOCK_LFA=cmuSelect_LFRCO`. + +### Low-power peripherals + +The low-power UART is capable of providing an UART peripheral using a low-speed +clock. When the LFB clock source is the LFRCO or LFXO, it can still be used in +EM2. However, this limits the baud rate to 9600 baud. If a higher baud rate is +desired, set the clock source to CORELEDIV2. + +**Note:** peripheral mappings in your board definitions will not be affected by +this setting. Ensure you do not refer to any low-power peripherals. + +### RTC or RTT + +RIOT-OS has support for *Real-Time Tickers* and *Real-Time Clocks*. + +However, this board MCU family has support for a 32-bit *Real-Time Clock and +Calendar*, which can be configured in ticker mode **or** calendar mode. +Therefore, only one of both peripherals can be enabled at the same time. + +Configured at 1 Hz interval, the RTCC will overflow each 136 years. + +### Hardware crypto +This MCU is equipped with a hardware-accelerated crypto peripheral that can +speed up AES128, AES256, SHA1, SHA256 and several other cryptographic +computations. + +A peripheral driver interface is proposed, but not yet implemented. + +### Usage of EMLIB + +This port makes uses of EMLIB by Silicon Labs to abstract peripheral registers. +While some overhead is to be expected, it ensures proper setup of devices, +provides chip errata and simplifies development. The exact overhead depends on +the application and peripheral usage, but the largest overhead is expected +during peripheral setup. A lot of read/write/get/set methods are implemented as +inline methods or macros (which have no overhead). + +Another advantage of EMLIB are the included assertions. These assertions ensure +that peripherals are used properly. To enable this, pass `DEBUG_EFM` to your +compiler. + +### Pin locations + +The EFM32 platform supports peripherals to be mapped to different pins +(predefined locations). The definitions in `periph_conf.h` mostly consist of a +location number and the actual pins. The actual pins are required to configure +the pins via GPIO driver, while the location is used to map the peripheral to +these pins. + +In other words, these definitions must match. Refer to the data sheet for more +information. + +This MCU has extended pin mapping support. Each pin of a peripheral can be +connected separately to one of the predefined pins for that peripheral. + +## Flashing the device + +The board provides a on-board SEGGER J-Link debugger through the micro USB +board so that flashing and debugging is very easy. + +Flashing is supported by RIOT-OS using the command below: + +``` +make flash +``` + +To run the GDB debugger, use the command: + +``` +make debug +``` + +Or, to connect with your own debugger: + +``` +make debug-server +``` + +Some boards have (limited) support for emulation, which can be started with: + +``` +make emulate +``` + +## Supported Toolchains +For using the Silicon Labs SLSTK3701A starter kit we strongly recommend +the usage of the [GNU Tools for ARM Embedded Processors](https://developer.arm.com/open-source/gnu-toolchain/gnu-rm) +toolchain. + +## License information +* Silicon Labs' EMLIB: zlib-style license (permits distribution of source). + */ diff --git a/boards/slstk3701a/include/board.h b/boards/slstk3701a/include/board.h new file mode 100644 index 0000000000000..692fb17f27526 --- /dev/null +++ b/boards/slstk3701a/include/board.h @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2015-2020 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_slstk3701a + * @{ + * + * @file + * @brief Board specific definitions for the SLSTK3701A starter kit + * + * @author Hauke Petersen + * @author Bas Stottelaar + */ + +#ifndef BOARD_H +#define BOARD_H + +#include "cpu.h" +#include "periph_conf.h" +#include "periph/gpio.h" +#include "periph/spi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Xtimer configuration + * + * The timer runs at 1000 kHz to increase accuracy, or at 32.768 kHz if + * LETIMER is used. + * @{ + */ +#if IS_ACTIVE(CONFIG_EFM32_XTIMER_USE_LETIMER) +#define XTIMER_DEV (TIMER_DEV(2)) +#define XTIMER_HZ (32768UL) +#define XTIMER_WIDTH (16) +#else +#define XTIMER_DEV (TIMER_DEV(0)) +#define XTIMER_HZ (1000000UL) +#define XTIMER_WIDTH (32) +#endif +#define XTIMER_CHAN (0) +/** @} */ + +/** + * @name Board controller configuration + * + * Define the GPIO pin to enable the BC, to allow serial communication + * via the USB port. + * @{ + */ +#define BC_PIN GPIO_PIN(PE, 1) +/** @} */ + +/** + * @name Push button pin definitions + * @{ + */ +#define PB0_PIN GPIO_PIN(PC, 8) +#define PB1_PIN GPIO_PIN(PC, 9) +/** @} */ + +/** + * @name LED pin definitions + * @{ + */ +#define LED0R_PIN GPIO_PIN(PH, 10) +#define LED0G_PIN GPIO_PIN(PH, 11) +#define LED0B_PIN GPIO_PIN(PH, 12) +#define LED1R_PIN GPIO_PIN(PH, 13) +#define LED1G_PIN GPIO_PIN(PH, 14) +#define LED1B_PIN GPIO_PIN(PH, 15) +#define LED0_PIN LED0R_PIN +#define LED1_PIN LED1R_PIN +/** @} */ + +/** + * @name Macros for controlling the on-board LEDs + * @{ + */ +#define LED0_ON gpio_set(LED0_PIN) +#define LED0_OFF gpio_clear(LED0_PIN) +#define LED0_TOGGLE gpio_toggle(LED0_PIN) +#define LED1_ON gpio_set(LED1_PIN) +#define LED1_OFF gpio_clear(LED1_PIN) +#define LED1_TOGGLE gpio_toggle(LED1_PIN) +/** @} */ + +/** + * @name Display configuration + * + * Connection to the on-board Sharp Memory LCD (LS013B7DH03). + * @{ + */ +#define DISP_SPI SPI_DEV(0) +#define DISP_COM_PIN GPIO_PIN(PA, 11) +#define DISP_CS_PIN GPIO_PIN(PC, 14) +#define DISP_EN_PIN GPIO_PIN(PA, 9) +/** @} */ + +/** + * @name Temperature sensor configuration + * + * Connection to the on-board temperature/humidity sensor (Si7021). + * @{ + */ +#define SI7021_I2C I2C_DEV(2) +#define SI7021_EN_PIN GPIO_PIN(PB, 3) + +#define SI70XX_PARAM_I2C_DEV SI7021_I2C +/** @} */ + +/** + * @brief Initialize the board (GPIO, sensors, clocks). + */ +void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/slstk3701a/include/gpio_params.h b/boards/slstk3701a/include/gpio_params.h new file mode 100644 index 0000000000000..699df52cc39bf --- /dev/null +++ b/boards/slstk3701a/include/gpio_params.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2016-2020 Bas Stottelaar + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_slstk3701a + * @{ + * + * @file + * @brief Board specific configuration of direct mapped GPIOs + * + * @author Bas Stottelaar + */ + +#ifndef GPIO_PARAMS_H +#define GPIO_PARAMS_H + +#include "board.h" +#include "saul/periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO pin configuration + */ +static const saul_gpio_params_t saul_gpio_params[] = +{ + { + .name = "LED 0", + .pin = LED0_PIN, + .mode = GPIO_OUT + }, + { + .name = "LED 1", + .pin = LED1_PIN, + .mode = GPIO_OUT + }, + { + .name = "Button 1", + .pin = PB0_PIN, + .mode = GPIO_IN_PU, + .flags = SAUL_GPIO_INVERTED + }, + { + .name = "Button 2", + .pin = PB1_PIN, + .mode = GPIO_IN_PU, + .flags = SAUL_GPIO_INVERTED + } +}; + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_PARAMS_H */ +/** @} */ diff --git a/boards/slstk3701a/include/periph_conf.h b/boards/slstk3701a/include/periph_conf.h new file mode 100644 index 0000000000000..a188846d496e7 --- /dev/null +++ b/boards/slstk3701a/include/periph_conf.h @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2015-2020 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_slstk3701a + * @{ + * + * @file + * @brief Configuration of CPU peripherals for the SLSTK3701A starter kit + * + * @author Hauke Petersen + * @author Bas Stottelaar + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#include "cpu.h" +#include "periph_cpu.h" +#include "em_cmu.h" +#include "usbdev_cfg_otg_fs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock configuration + * @{ + */ +#ifndef CLOCK_HF +#define CLOCK_HF cmuSelect_HFXO +#endif +#ifndef CLOCK_CORE_DIV +#define CLOCK_CORE_DIV cmuClkDiv_1 +#endif +#ifndef CLOCK_LFA +#define CLOCK_LFA cmuSelect_LFXO +#endif +#ifndef CLOCK_LFB +#define CLOCK_LFB cmuSelect_LFXO +#endif +#ifndef CLOCK_LFE +#define CLOCK_LFE cmuSelect_LFXO +#endif +/** @} */ + +/** + * @name ADC configuration + * @{ + */ +static const adc_conf_t adc_config[] = { + { + .dev = ADC0, + .cmu = cmuClock_ADC0, + } +}; + +static const adc_chan_conf_t adc_channel_config[] = { + { + .dev = 0, + .input = adcPosSelTEMP, + .reference = adcRef1V25, + .acq_time = adcAcqTime8 + }, + { + .dev = 0, + .input = adcPosSelAVDD, + .reference = adcRef5V, + .acq_time = adcAcqTime8 + } +}; + +#define ADC_DEV_NUMOF ARRAY_SIZE(adc_config) +#define ADC_NUMOF ARRAY_SIZE(adc_channel_config) +/** @} */ + +/** + * @name DAC configuration + * @{ + */ +static const dac_conf_t dac_config[] = { + { + .dev = VDAC0, + .ref = vdacRefAvdd, + .cmu = cmuClock_VDAC0, + }, +}; + +static const dac_chan_conf_t dac_channel_config[] = { + { + .dev = 0, + .index = 0, + }, +}; + +#define DAC_DEV_NUMOF ARRAY_SIZE(dac_config) +#define DAC_NUMOF ARRAY_SIZE(dac_channel_config) +/** @} */ + +/** + * @name I2C configuration + * @{ + */ +static const i2c_conf_t i2c_config[] = { + { + .dev = I2C0, + .sda_pin = GPIO_PIN(PC, 0), + .scl_pin = GPIO_PIN(PC, 1), + .loc = I2C_ROUTELOC0_SDALOC_LOC4 | + I2C_ROUTELOC0_SCLLOC_LOC4, + .cmu = cmuClock_I2C0, + .irq = I2C0_IRQn, + .speed = I2C_SPEED_NORMAL + }, + { + .dev = I2C1, + .sda_pin = GPIO_PIN(PC, 7), + .scl_pin = GPIO_PIN(PC, 5), + .loc = I2C_ROUTELOC0_SDALOC_LOC0 | + I2C_ROUTELOC0_SCLLOC_LOC0, + .cmu = cmuClock_I2C1, + .irq = I2C1_IRQn, + .speed = I2C_SPEED_NORMAL + }, + { + .dev = I2C2, + .sda_pin = GPIO_PIN(PI, 4), + .scl_pin = GPIO_PIN(PI, 5), + .loc = I2C_ROUTELOC0_SDALOC_LOC7 | + I2C_ROUTELOC0_SCLLOC_LOC7, + .cmu = cmuClock_I2C2, + .irq = I2C2_IRQn, + .speed = I2C_SPEED_NORMAL + } +}; + +#define I2C_NUMOF ARRAY_SIZE(i2c_config) +#define I2C_0_ISR isr_i2c0 +#define I2C_1_ISR isr_i2c1 +#define I2C_2_ISR isr_i2c2 +/** @} */ + +/** + * @name RTT configuration + * @{ + */ +#ifndef RTT_FREQUENCY +#define RTT_FREQUENCY (1U) +#endif +/** @} */ + +/** + * @name SPI configuration + * @{ + */ +static const spi_dev_t spi_config[] = { + { + .dev = USART0, + .mosi_pin = GPIO_PIN(PE, 10), + .miso_pin = GPIO_PIN(PE, 11), + .clk_pin = GPIO_PIN(PE, 12), + .loc = USART_ROUTELOC0_TXLOC_LOC0 | + USART_ROUTELOC0_RXLOC_LOC0 | + USART_ROUTELOC0_CLKLOC_LOC0, + .cmu = cmuClock_USART0, + .irq = USART0_RX_IRQn + } +}; + +#define SPI_NUMOF ARRAY_SIZE(spi_config) +/** @} */ + +/** + * @name Timer configuration + * + * The implementation uses two timers in cascade mode. + * @{ + */ +static const timer_conf_t timer_config[] = { + { + .prescaler = { + .dev = WTIMER0, + .cmu = cmuClock_WTIMER0 + }, + .timer = { + .dev = WTIMER1, + .cmu = cmuClock_WTIMER1 + }, + .irq = WTIMER1_IRQn, + .channel_numof = 3 + }, + { + .prescaler = { + .dev = TIMER0, + .cmu = cmuClock_TIMER0 + }, + .timer = { + .dev = TIMER1, + .cmu = cmuClock_TIMER1 + }, + .irq = TIMER1_IRQn, + .channel_numof = 3 + }, + { + .prescaler = { + .dev = NULL, + .cmu = cmuClock_LETIMER0 + }, + .timer = { + .dev = LETIMER0, + .cmu = cmuClock_LETIMER0 + }, + .irq = LETIMER0_IRQn, + .channel_numof = 2 + } +}; + +#define TIMER_NUMOF ARRAY_SIZE(timer_config) +#define TIMER_0_ISR isr_wtimer1 +#define TIMER_1_ISR isr_timer1 +#define TIMER_2_ISR isr_letimer0 +/** @} */ + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = USART4, + .rx_pin = GPIO_PIN(PH, 5), + .tx_pin = GPIO_PIN(PH, 4), + .loc = USART_ROUTELOC0_RXLOC_LOC4 | + USART_ROUTELOC0_TXLOC_LOC4, + .cmu = cmuClock_USART4, + .irq = USART4_RX_IRQn, + }, + { + .dev = USART5, + .rx_pin = GPIO_PIN(PE, 9), + .tx_pin = GPIO_PIN(PE, 8), + .loc = USART_ROUTELOC0_RXLOC_LOC4 | + USART_ROUTELOC0_TXLOC_LOC4, + .cmu = cmuClock_USART5, + .irq = USART5_RX_IRQn, + } +}; + +#define UART_NUMOF ARRAY_SIZE(uart_config) +#define UART_0_ISR_RX isr_usart4_rx +#define UART_1_ISR_RX isr_usart5_rx +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */